IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 4, APRIL 2012 625
Studies on the Thermal Cycling Reliability of BGASystem-in-Package (SiP) with an Embedded Die
Seon Young Yu, Yong-Min Kwon, Jinsu Kim, Taesung Jeong, Seogmoon Choi,and Kyung-Wook Paik, Member, IEEE
Abstract— Nowadays, major trends in the design of electronicproducts are toward multifunction and miniaturization. To meetthese trends, system-in-package (SiP) has been adapted as one ofthe core packaging technologies for many product applications.Among the various types of SiPs, SiP with embedded dies hasbecome important due to the smaller size achieved throughembedded dies and better electrical performance by the shorterinterconnection length. However, reliability data of the SiP withembedded dies have not been reported yet. Therefore, it isnecessary to investigate the reliability of the SiPs with embeddeddies and the effect of the embedded die on the SiP reliability.Of the several reliability tests, a detailed thermal cycling test(T/C test) was performed on board-level packaged samples. Afinite element method (FEM) simulation was also performed tofind out the stress and strain distribution of ball grid array(BGA) solder positions and to predict the potential failure sitesunder the T/C test. Through this paper, it was found that thefailure position of the BGA changed from the corner solder ballposition of the conventional BGA package, where the largestdistance from neutral point was, to the inner BGA solder ballpositions, where the edge of embedded die was located, due to thecomplicated structure of embedded die SiPs. Furthermore, FEMresults showed that the inner site of the BGA is more vulnerablethan the corner BGAs. This was well matched with experimentalresults.
Index Terms— Embedded die, finite element method, solderjoint reliability, system-in-package, thermal cycling reliability.
I. INTRODUCTION
AS THE requirements for small-size electronic prod-ucts have increased, electronic components have been
developed to downsize and integrate more functional blocks.System-in-package (SiP), which is one of the solutions of thisneed for providing multiple functions, is a combination ofmultiple active and passive electronic components that havedifferent functionalities in a single package. Therefore, the
Manuscript received December 22, 2010; revised July 26, 2011; acceptedJuly 27, 2011. Date of publication January 31, 2012; date of current versionMarch 30, 2012. Recommended for publication by Associate Editor A.Chandra upon evaluation of reviewers’ comments.
S. Y. Yu, Y.-M. Kwon, and K.-W. Paik are with the Department of MaterialsScience and Engineering, Korea Advanced Institute of Science and Technol-ogy, Daejeon 305-701, Korea (e-mail: [email protected]; [email protected];[email protected]).
J. Kim and S. Choi are with the Corporate Research and DevelopmentInstitute, Samsung Electro-Mechanics, Gyunggi-do 443-743, Korea (e-mail:[email protected]; [email protected]).
T. Jeong is with the Advanced Circuit Interconnection Division, Sam-sung Electro-Mechanics, Gyunggi-do 443-743, Korea (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2011.2166555
application fields of SiP are getting broader because of severaladvantages: high performance, ultralight weight, microscopicsize, shorter time-to-market, and performance optimization.Also, the SiP with an embedded die is one of the solutionsto make the package size even smaller and obtain higherelectronic performance [1].
Although several reliability tests of the SiP packages havebeen reported [2], reliability data of the SiP with an embeddeddie are insufficient and more studies are needed to investigatethe effects of embedded dies on board-level reliability data ofthese SiPs. Among the various reliability tests, thermal cycling(T/C) tests were performed, and the results are analyzed in thispaper. Also, the difference between the SiP with an embeddeddie and similar ball grid array (BGA) packages was alsoinvestigated using a finite element method (FEM) simulationduring the T/C test.
The reliability data and failure analysis of the SiP packagewith an embedded die and the information about effects of theembedded die on SiP under T/C test will provide a guidelinefor more reliable SiPs with embedded dies.
II. EXPERIMENTAL
A. Test Samples Preparation
The SiP was packaged as a BGA format and consisted oftwo parts: molding with epoxy molding compounds (EMC)and substrate layers. Fig. 1 shows a schematic of the cross-sectional view of the SiP with an embedded die assembled ona printed circuit board (PCB) test board.
First, in the substrate layers, there was an embedded diewith 1.9 × 1.9 mm size and 0.18 mm thickness at the centerof the substrate. The core layer had a cavity to accommodatethe embedded die, and had the same thickness as the embed-ded die.
Second, the EMC molding was applied just on the substratelayers. On the substrate layers, there were several passivecomponents, saw filters, and a flip-chip (FC) die. The FC diewas placed at the center of the substrate.
The SiP was basically assembled on another PCB test boardby using BGA solder balls. Two solder compositions wereused in this paper: Sn–Ag3–Cu0.5 (wt.%) (SAC 305) andSn–Ag1–Cu0.5 (wt.%) (SAC 105). Two kinds of metal padfinishes were used at the BGA PCB substrate: electroplatedNi/Au (Au-EP) and Cu-organic solderability preservative (Cu-OSP). The PCB board finishes were: 1) electroless Ni/Au(ENIG), and 2) Cu-OSP, as shown in Fig. 2.
626 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 4, APRIL 2012
SiP Substratelayers
FC die
Embedded die
BGA
EMC molding
PCB test board
Failuremeasurement
Fig. 1. Cross-sectional view of the test sample.
SiP Au-EP
ENIG sample Cu-OSP sample
Cu-OSPENIGSiP
BoardBoard
Fig. 2. Pad finish combinations of the test samples.
(a) (b)
Fig. 3. Two kinds of resistance measurement positions.(a) BGA solder. (b) Embedded die bump.
(a)
(b)
PassivesSaw filter
FC die
EmbeddeddiePCB
Fig. 4. 3-D quarter modeling of SiP assembled board using ABAQUSsimulation program. (a) SiP modeling. (b) Inside structure of SiP.
On the PCB test board, five test SiPs were mounted,and electrical failures at either the BGA or the embeddeddie bumps could be identified. There were two resistancemeasurement sites, i.e., corner and inner sites, to find outat what position the bumps were failing among 156 BGAand 151 embedded die bump positions. In Fig. 3, red colorrepresents BGA balls and embedded die bumps that are placedat a corner site, and yellow color represents those placed atan inner position.
(a)
(b)
(c)
(d)
Fig. 5. Four kinds of 3-D quarter modeling of SiP. (a) SiP modeling withoutembedded die. (b) SiP modeling without FC die. (c) SiP modeling withembedded die in SiP substrate filled only with PCB core material. (d) SiPmodeling with only EMC molding and SiP substrate filled only with PCBcore material.
B. T/C Test
T/C test was performed in the −40 to 125 °C temperaturerange per JEDEC standard. During the T/C test, the resistanceof the BGA solders and embedded die bumps were measuredevery 200 cycles up to 3200 cycles using a resistance meter.The failure criterion was twice the initial resistance and, thelifetime of each sample was obtained from a Weibull plot.
C. FEM Simulation
The FEM was used to simulate the T/C test condition ofthe SiP assembled at the PCB board level using the ABAQUS6.9 program. A quarter of the SiP assembled board was usedto make the simulation model, as shown in Fig. 4, because ofthe bilaterally symmetric structure of the SiP assembled board.
YU et al.: THERMAL CYCLING RELIABILITY OF BGA SYSTEM-IN-PACKAGE (SiP) WITH AN EMBEDDED DIE 627
Fig. 6. Failure rate of SAC 305 samples during T/C test. (a) SAC 305 jointedsamples with ENIG to Au-EP pad finish samples. (b) SAC 305 jointed sampleswith Cu-OSP to Cu-OSP pad finish samples.
Therefore, X-symmetric and Y-symmetric boundary conditionswere given.
The thermal load was applied from −40 to 125 °C, andthe element type was fully coupled temperature–displacementto analyze the problem where the simultaneous solutionof the temperature and stress/displacement fields is neces-sary [3]. A fully coupled thermal stress analysis was per-formed since the mechanical and thermal solutions affecteach other strongly and, therefore, they must be obtainedsimultaneously. Using FEM simulation, the strain distributionof the BGA solders resulting from the coefficient of thermalexpansion (CTE) mismatch was observed during temperaturecycling.
In addition, component effects such as from the FC die,embedded die, and SiP substrate were also observed usingthe ABAQUS 6.9 program. Four kinds of modeling werecompleted SiP modeling: 1) without embedded die; 2) withoutthe FC die; 3) with embedded die in SiP substrate filledonly with a core material; and 4) with only EMC moldingand SiP substrate filled only with core material, as shownin Fig. 5.
III. RESULTS AND DISCUSSION
A. T/C Reliability Test
In the case of SAC 305 jointed samples with ENIG (PCBboard side pad) to Au-EP (SiP PCB side pad) and SAC 305jointed samples with Cu-OSP to Cu-OSP (both PCB side
SAC 305
Au-EP pad
ENIG pad
SAC 305
Fig. 7. Cross-sectional scanning electron microscope (SEM) images of crackpropagation at SAC 305 BGA solder jointed samples with ENIG to Au-EPpad finish samples during a T/C test.
SAC 305
OSP pad
OSP pad
Fig. 8. Cross-sectional SEM images of crack propagation at SAC 305 BGAsolder jointed samples with Cu-OSP to Cu-OSP pad finish samples during aT/C test.
pads), the ENIG pad finish sample showed higher failurerate than Cu-OSP pad finish, and all failures were detectedon the BGA solders. Fig. 6 shows the failure rate of SAC305 with ENIG to Au-EP, and SAC 305 with Cu-OSP toCu-OSP samples. From these graphs, it was found that theinner position of BGA solders of the SiP package was morevulnerable than the corner of BGA solders, and this is due tothe position of embedded die which is located at the centerof the SiP. This result is quite different from the conventionalBGA failure case under a T/C test where the outmost cornersolder balls are the most vulnerable ones because of the largestdistance from neutral point (DNP).
Figs. 7 and 8 show the cross-sectional SEM images ofpad finish samples of SAC 305 jointed samples with ENIGto Au-EP, and SAC 305 jointed samples with Cu-OSP toCu-OSP during a T/C test. The cracks near Au-EP and ENIGpad finish propagated along intermetallic compound (IMC),but the cracks near Cu-OSP and Cu-OSP pad finish propagatedmore into the solder bulk than the IMCs.
In the case of SAC 105, BGA solder failures were alsodetected. The failure rate of these samples is shown in Fig. 9.
628 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 4, APRIL 2012
0 500 1000 1500 2000 2500 30000
20
40
60
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fai
lure
rat
e(%
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20
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100BGA-inner
BGA-corner
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Fig. 9. Failure rate of SAC 105 samples during T/C test. (a) SAC 105 jointedsamples with ENIG to Au-EP pad finish samples. (b) SAC 105 jointed sampleswith Cu-OSP to Cu-OSP pad finish samples.
SAC 305
ENIG pad
Au-EP pad
Fig. 10. Cross-sectional SEM images of BGA solder failures on SAC 105jointed samples with ENIG to Au-EP pad finish samples during T/C test.
The ENIG pad finish sample showed lower failure rate thanCu-OSP pad finish and the failures were detected on the BGAsolders. Through these graphs, it was noticed that inner andcorner BGA solder failures were more than embedded diefailures. The embedded die bump showed lower failure ratesthan BGAs in Figs. 6 and 9. This is due to the fact that theembedded bumps were surrounded by the substrate layers andtherefore were safer than BGAs.
Figs. 10 and 11 show the cross-sectional SEM imagesof SAC 105 samples during a T/C test. The ENIG pad
SAC 305
SAC 305
OSP pad
OSP pad
Fig. 11. Cross-sectional SEM images of BGA solder failures on SAC 105jointed samples with Cu-OSP to Cu-OSP pad finish samples during T/C test.
Probability Plot of ENIG105, OSP105, ENIG305, OSP305Weibull
99
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N5
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P>0.250
0.0870.055
>0.250
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Mean time to failure
Early failure
Fig. 12. Weibull plot of all T/C test samples SAC 305 and 105 jointedsamples with ENIG to Au-EP and Cu-OSP to Cu-OSP pad finish samples.
finish samples showed failures on both ENIG and Au-EP padfinish. Also, Cu-OSP pad finish samples showed the samephenomenon.
The cracks near Au-EP and ENIG pad finish propagatedbetween IMC and the solder bulk, while the cracks nearCu-OSP to Cu-OSP pad finish propagated more into the solderbulk than in Au-EP and ENIG pad finish samples. All the BGAinner and corner solder failures showed these failure modes.
The Weibull plot of SAC 105 samples is shown in Fig. 12.To compare with SAC 305 solder balls, the Weibull plotsof both solders are combined. As seen from Fig. 12, themean times to failures (MTTFs) of the sample were compared,MTTF gives the mean time until a failure occurs after whichthe product cannot be repaired. At 63.2% failure, all samplesshow the same lifetime. Therefore, the lifetimes were com-pared with early failure, which is given by the x-intercept. Interms of early failure, SAC 305 jointed samples with Cu-OSPpad finish sample showed the best T/C reliability.
To summarize the T/C test result, SAC 305 solder withCu-OSP to Cu-OSP pad finish sample showed the best T/Creliability.
In addition, the creep property of solder bulk may affectthe T/C reliability. Fig. 13 shows the creep strain results of
YU et al.: THERMAL CYCLING RELIABILITY OF BGA SYSTEM-IN-PACKAGE (SiP) WITH AN EMBEDDED DIE 629
TABLE I
MATERIAL PROPERTIES FOR FEM SIMULATION OF SiP WITH AN EMBEDDED DIE
Thermal conductivity(W/mmK)
Density (g/mm3) Temperature(°C)
Young’s modulus(N/mm2)
Poisson’sratio
Cu 0.393 0.0089 - 110000 0.343
EMC (Tg = 150 °C) 9.4e-04 -20 26000 0.35
200 900 0.35
FR4 1.7e-03 0.0019 - 17000 0.28
Si 0.148 0.0023 - 112400 0.28
solder 0.022 0.00736 - 45000 0.35
Core (Tg = 200 °C) 4.4e-4 0.002120 29000 0.17
250 18000 0.17
Passive 2.61e-3 0.00584 - 370000 0.22
PPG (Tg = 200 °C) 4.4e-4 0.002120 4000 0.3
250 400 0.3
Underfill (Tg = 110 °C) 1.7e-3 0.001620 10000
0.35150 200
Solder resist (Tg = 114 °C) 2.4e-4 -20 3400 0.29
150 320 0.29
Die bump layer (Tg = 200)20 4000 0.3
250 400 0.3
Saw filter die (TaO3) 4.6e-3 0.00745 80700 0.3
CTE (ppm/°C) Specific heat (J/gK) Yield strength (N/mm2) Strain
Cu 16.4 0.385 69 0/0.01/0.1 At 20 °C
EMC (Tg = 150 °C)11
- - -49
FR4 17 0.800 - -
Si 2.5 0.700 - -
20 0.22630 0
solder 45 0.01180 0.1
Core (Tg = 200 °C)14
1 - -5
Passive 7.4 0.434 - -
PPG (Tg = 200 °C)46
1 - -120
Underfill (Tg = 110 °C)25
0.8 - -93
Solder resist (Tg = 114 °C)60
- - -130
Die bump layer (Tg = 200)46120
Saw filter die (TaO3) 3
SAC 305 and 105 solders. Comparing SAC 305 and 105, thecreep strain of SAC 105 is larger than that of SAC 305. Thismeans that SAC 305 solder can be deformed less than SAC105 resulting in less crack propagation when they are exposedto 125 °C (higher temperature of the T/C test). As a result,SAC 305 solder and Cu-OSP pad finish combination showedthe highest T/C reliability among others.
B. FEM Simulation of SiP with an Embedded Die During aT/C Test
The FEM simulation of SiP with an embedded die under aT/C test was performed to find out how strain was distributedin an SiP package. The material properties of this simulationare shown in Table I.
As shown in the FEM simulation results, the whole packagewas under internal stress from CTE mismatch. To find out the
solder position at which failure can occur, the yield surfacesize of each solder was investigated. The plastic deformationis expressed in terms of the sum of the equivalent creepstrain (CEEQ) and the equivalent plastic strain (PEEQ). Thesevalues were obtained from FEM simulation results to definethe total accumulation of plastic strain. The PEEQ in a materialis a scalar variable used to represent the material’s inelasticdeformation behavior and, if the PEEQ is greater than zero,the material will yield. In addition, the CEEQ is also used todefine the amount of yield caused by a creep strain, becauseat 125 °C (the high temperature of T/C test) solders are underthe creep deformation region [5].
In this paper, three T/C test cycle modeling was simulated,which is shown in Fig. 14. The CEEQ value was moredominant than the PEEQ in the BGA solder. This means thatthe creep deformation dominates the BGA solder deformation
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0.08SAC 105, RFT = 25 °Cσ = 15 MPa
SAC 105, RFT = 25 °Cσ = 15 MPa
Aging Conditions
As Reflowed100 °C, 1 Month100 °C, 2 Months100 °C, 3 Months100 °C, 4 Months
Aging Conditions
As Reflowed100 °C, 1 Month100 °C, 2 Months100 °C, 3 Months100 °C, 4 Months
0.06
0.04
Stra
in, ε
0.02
0.000 2000 4000
Time, t (sec)(a)
6000 8000
0 2000 4000Time, t (sec)
(b)
6000 8000
0.08
0.06
0.04
Stra
in, ε
0.02
0.00
Fig. 13. Creep strain of SAC solders tested at room temperature after agingat 100 °C according to time. (a) SAC 105. (b) SAC 305 [4].
during a T/C test, and only the CEEQ value needs to be usedto explain the simulation data.
Fig. 15(a) shows the SAM image of the bottom surface ofthe SiP package showing the BGA solder balls positions.
Fig. 15(b) shows the CEEQ distribution result on the wholeBGA solders of SiP modeling as shown in Fig. 4(a). The solderballs at the far left row [number 1 in Fig. 15(b)] are those atthe outside edge of BGA package, and solders at right edge(the row number 9) were placed in the center of the BGApackage as shown in yellow bow in Fig. 15(a). All the solderballs were marked in numerical order from edge 1 to the centerhalf solder 9 in each row and the first, second, and third layerof each column, and then the CEEQ values were presented asdifferent colors.
In Fig. 16, the CEEQ values of row numbers 5 to 7BGA solders in the first column increased compared withthe outer lower number row solder balls, while the CEEQvalues of all the solder balls at the second and third columnsdecreased as solders moved toward the center of BGApackage.
The effects of the embedded die, FC die, and SiP substrateduring a T/C reliability test were investigated by comparingwith the SiP modeling result in Fig. 15(b). Four kinds ofmodeling were completed and simulated, as shown in Fig. 5.
First, the SiP modeling without embedded die shown inFig. 5(a) showed that the embedded die did not affect onthe CEEQ distribution as shown in Fig. 17(a). The maximumCEEQ value of SiP modeling [marked in red in the Fig. 15(b)]
0 1000 2000 3000 4000 50000.0
0.1
0.2
0.3
0.4
0.5
0.6
Time (sec)
CE
EQ
PE
EQ
CEEQ
PEEQ
BGA solder
Fig. 14. Comparison of the CEEQ and PEEQ values of a BGA solder of anSiP package during a T/C test using the ABAQUS simulation program.
Fig. 15. (a) SAM image of bottom surface of SiP and BGA solder ballsposition. (b) CEEQ distribution on the BGA solder balls marked in a numericalorder from edge 1 to center solder 9 during a T/C test in the 3-D quarter SiPmodeling.
was higher than that of the modeling without embedded die[marked green in Fig. 17(a)]. This means that the embeddeddie caused the increased CEEQ value resulting in more yieldof the solder balls.
Second, the SiP modeling without FC die [as shown in theFig. 5(b)] and the SiP modeling with SiP substrate filled onlycore material and embedded die [as shown in Fig. 5(c)] werealso investigated as shown in Fig. 17(b) and (c). The CEEQdistributions and maximum CEEQ values in Fig. 17(b) and (c)
YU et al.: THERMAL CYCLING RELIABILITY OF BGA SYSTEM-IN-PACKAGE (SiP) WITH AN EMBEDDED DIE 631
0 1000 2000 3000 4000 5000
0.0
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EQ
2
4
6
7
8
(a)
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EQ
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(c)
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0.1
0.2
0.3
0.4
0.5
0.6
CE
EQ
3
4
6
7
8
Fig. 16. CEEQ values on each row of BGA solder balls at (a) first,(b) second, and (c) third columns during a T/C test.
did not show any difference compared with the actual FEMsimulation results of SiP modeling shown in Fig. 15(b). Theseresults mean that an FC die and SiP substrate filled only thecore material and an embedded die did not make any changeon the CEEQ value of BGA solders.
Additionally, the SiP modeling with only EMC molding andsubstrate filled core material [as shown in Fig. 5(d)] was alsosimulated. Fig. 17(d) shows a quite different behavior from theother modeling results. The maximum CEEQ value decreasedsignificantly by one-fifth as expected. Also the BGA solderposition of maximum CEEQ value was changed comparedwith that of actual SiP modeling in [6, Fig. 15(b)]. Fig. 18shows the CEEQ values of row 1 (edge) to 9 (center) of
Fig. 17. CEEQ distribution on BGA solders in simulation modeling duringT/C test. (a) SiP modeling without an embedded die. (b) SiP modeling withouta FC die. (c) SiP modeling with PCB substrate filled only a core materialand an embedded die. (d) SiP modeling with only EMC molding and PCBsubstrate filled only a core material.
0 1000 2000 3000 4000 5000
0.000
0.001
0.002
0.003
0.004
0.005
0.006
0.007
CE
EQ
Time (sec)
12345678
9
Fig. 18. CEEQ values of the row 1 (edge) to 9 (center) of the first column ofBGA solder balls in the SiP modeling with only EMC molding and substratefilled only core.
the first column of BGA solder balls in the SiP modelingwith only EMC molding and substrate filled only core, andit is well matched with the highest strain value at the cornersite solder ball in conventional BGA package. However, inthe SiP package modeling in Fig. 4, which is similar to
632 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 4, APRIL 2012
actual SiP package sample, the position of BGA solder undermaximum CEEQ value was changed to the inside the fifthto seventh row solder balls of the first column as shown inFig. 15(b).
These simulation results show that the complex structureof SiP package, especially the embedded die and the FC dieeffects the change of the maximum creep strain position fromthe corner solder ball of BGA to inner solder balls of theBGA layer. Also, this simulation results were well matchedwith more BGA inner solder ball failures than BGA cornerfailures during T/C test.
IV. CONCLUSION
In this paper, the T/C reliability of BGA type SiP with anembedded die was investigated.
First, in the T/C test, the SAC 305 solder with Cu-OSPpad finish sample showed the best reliability, and all failureoccurred on inner BGA solder balls rather than the cornersolder ball with the largest DNP. In addition, there was nofailure observed at the embedded die bump interconnection.The better T/C reliability was presumably due to the highercreep property of SAC 305 solder.
Second, through FEM simulation, the presence of FC and asubstrate filled only with a core material and an embedded die,instead of actual SiP substrate layer, did not make any changeon the CEEQ distribution of BGA solders and the maximumCEEQ value.
However, the SiP modeling showed that the maximumCEEQ value is located at the inner site of BGA solderballs, while the conventional BGA SiP modeling shows themaximum CEEQ value on the corner BGA solder balls. Thissimulation result is well matched with the T/C test result whichshowed that failure occurred on the inner site of BGA solderballs which is near the embedded die position.
In summary, the effect of an embedded die on the T/Creliability of an SiP was experimentally investigated, and itwas shown that the failure position of BGA solders duringT/C test was well matched with the FEM simulation.
REFERENCES
[1] D. J. Pedder, “System-in-package (SiP): A guide for electronics designengineers, SiP technology - introduction, categories and benefits,” Elec-tronics Knowledge Transfer Network, Cambridge Univ., Cambridge,U.K., TWI Rep. 18333/1/08, Oct. 2008.
[2] M. Dreiza, G. Dunn, L. Smith, N. Vijayaragavan, and J. Werner,“Package on package (PoP) stacking and board level relaibility, resultsof joint industry study,” in Proc. Int. Microelectron. Packag. Soc., 2006,pp. 1–8.
[4] Y. Zhang, Z. Cai, J. C. Suhling, P. Lall, and M. J. Bozack, “The effects ofaging temperature on SAC solder joint material behavior and reliability,”in Proc. 58th Electron. Comp. Technol. Conf., Lake Buena Vista, FL,May 2008, pp. 99–112.
[5] S. Wen, “Thermal and thermo-mechanical analyses of wire bond versus3-D packaged power electronics modules,” M.S. thesis, Dept. PowerElectron. Syst., Virginia Polytechnic Inst. State Univ., Blacksburg,1999.
[6] C. M. Liu, C. C. Lee, and K. N. Chiang, “Enhancing the reliabilityof wafer level packaging by using solder joints layout design,” IEEETrans. Comp. Packag. Technol., vol. 29, no. 4, pp. 877–885, Dec.2006.
Seon Young Yu received the B.S. degree in mate-rials science and engineering from the Universityof Seoul, Seoul, South Korea, in 2009, and theM.S. degree in materials science and engineeringfrom the Korea Advanced Institute of Science andTechnology, Daejeon, South Korea, in 2011.
Her current research interests include reliability ofembedded packages and finite element analysis.
Yong-Min Kwon received the B.S. and Ph.D.degrees in materials science and engineering fromthe Korea Advanced Institute of Science and Tech-nology, Daejeon, South Korea, in 2003 and 2011,respectively.
He joined the Lighting Package DevelopmentGroup, Samsung LED, Suwon, South Korea, in2011, as a Senior Engineer, where he is involvedwith the development of light emitting diode pack-aging technologies. His current research interestsinclude reliability improvement of flip-chip and
wafer-level packages using solder joints.
Jinsu Kim received the B.S. degree in metallurgyand the Masters degree in material science andengineering from Korea University, Seoul, Korea, in1999 and 2001.
He is currently a Senior Research Engineer withCentral Research and Development Institute, Sam-sung Electro-Mechanics Company Ltd., Suwon,South Korea. His current research interests includethe long term reliability and the accelerated life testof solder joints and power semiconductor modules.
Taesung Jeong received the B.S. degree in chemicalengineering from Dongkuk University, Seoul, SouthKorea, in 1991.
He is currently a Principal Engineer with theAdvanced Circuit Interconnection Division, Sam-sung Electro-Mechanics Company Ltd., Suwon,South Korea. His current research interests includedevice embedding technology for semiconductor andmobile application products.
Seogmoon Choi received the B.S., M.S., and Ph.D.degrees in mechanical engineering from Yonsei Uni-versity, Seoul, Korea, in 1989, 1991, and 2003,respectively.
He joined Research and Development Institute,Samsung Electro-Mechanics Company Ltd., Suwon,South Korea, where he conducted research as aSenior Research Engineer. In 1998, he joined theDr. Sang-Jo Lee’s Micromachining & Manufactur-ing Group, Yonsei University, where he conductedresearch as a Graduate Research Assistant. His
research in micromachining and microelectromechanical systems (MEMS)includes design and fabrication of sensors and microactuators. He is currentlya Principal Research Engineer with Central Research and DevelopmentInstitute, Samsung Electro-Mechanics Company Ltd. His current researchinterests include MEMS and packaging.
YU et al.: THERMAL CYCLING RELIABILITY OF BGA SYSTEM-IN-PACKAGE (SiP) WITH AN EMBEDDED DIE 633
Kyung-Wook Paik (M’95) received the B.Sc.degree in metallurgical engineering from SeoulNational University, Seoul, South Korea, the M.Sc.degree from the Korea Advanced Institute of Scienceand Technology (KAIST), Daejeon, South Korea,and the Ph.D. degree in materials science and engi-neering from Cornell University, Ithaca, NY, in1979, 1981, and 1989, respectively.
He was a Research Scientist at KAIST from 1982to 1985, where he was responsible for the develop-ment of gold bonding wires. From 1989 to 1995,
he was a Senior Technical Staff Member with General Electric CorporateResearch and Development where he involved in interconnect multichipmodule technology and power integrated circuits packaging. He rejoined
KAIST as a Professor in the Department of Materials Science and Engineeringin 1995. He was a Visiting Professor at the Packaging Research Center,Georgia Institute of Technology, Atlanta, from March 1999 to February 2000,where he was involved in packaging education and integrated passives researchprograms. He was also a Visiting Professor with Portland State University,Portland, OR, from February to August 2005, where he worked in the areas offlip-chip polymer materials evaluation. He is currently with Nano-Packagingand Interconnect Laboratory working in the areas of flip-chip bumping andassembly, adhesives flip-chip, embedded capacitors, and display packagingtechnologies. He has published more than 80 technical papers and holds 16U.S. patents with another four pending.
Prof. Paik is a member of the International Microelectronics and PackagingSociety, SEMI, and MRS. He has been the Chairman of the Korean IEEEComponents Packaging and Manufacturing Technology Chapter since 1995.
