etfi

r

s

d

a

power conversion efciency and reducing standby power consumption in a yback converter. In addition, an asynchronous-

www.ietdl.orgtype secondary side post regulator is applied to the converter for minimising standby energy leakage and improving cross-regulation performance for a multiple output channel yback converter. Operational principles, control schemes, switchstresses and power consumptions are analysed using a converter small signal model and mathematical equations of converterwaveforms. The superiority of the proposed converter is veried using experimental results on 110 W prototype.

1 Introduction

Single-ended active clamp converters have recently gainedwidespread acceptance for many medium power ofinedcdc converter applications. The active clamp techniquefor absorbing leakage energy offers many well-documentedadvantages over traditional single-ended reset techniques,including lower voltage stress on the main switch, theability to switch at zero voltage, reduced electromagneticinterference (EMI) and duty cycle operation above 50%.Typically, the clamp switch is kept on during the off-timeof the main switch. As a result, the clamp capacitor absorbsand returns parasitic energy during every cycle withminimal losses. Several publications have compared theperformance advantages of the active clamp over the morewidely used RCD clamp [13]. In addition, theory,operation and applications of these converters have beenreported in many previous publications [414].Many small switch mode power supplies (SMPSs) have

been designed with a single controller and multiple outputchannels to meet the needs of multiple voltages and lowcost under various loading conditions including standbymode. In this case, only a single output can be tightlycontrolled while others not. Using multiple output sensingmethods, a single controller can control several sensedoutputs, however, it cannot tightly regulate the outputvoltage. This cross-regulation problem is especiallysignicant when output channel loads are extremely

unbalanced; a phenomenon that can lead to output voltageuctuations.To improve the cross-regulation performance, magnetic

ampliers (magamp) have been developed [1518]. Themagamp is a well-known post-regulation method. Asaturable core in the inductive component is utilised forpost-regulation. A synchronous post regulator (SPR) wasalso proposed as another method to improve cross-regulation performance [19]. Researches have addressed itscontrol methods [2023], analysis [24] and application[25]. The SPR uses series metaloxide semiconductor eld-effect transistors (MOSFETs) connected between thecathode of the rectifying diodes and the output capacitors. Itis controlled using a pulse-width modulation (PWM)algorithm synchronised with the main switch of theconverter. The additional inductive component in themagamp will also contribute to loss in efciency. The SPRneeds a complex control scheme and an elaborate drivecircuit, which makes the SPR more expensive. There isresearch to improve the cross-regulation of a switchedresonant converter [26, 27]. It uses a secondary side postregulator (SSPR) controlled by asynchronous gate voltagelevels and a simple control circuit, however, falls short ofconsidering standby-mode operation.In this paper, a novel control method of the active clamp

switch and the SSPR are proposed. The active clamptechnique can save leakage energy in its clamp capacitorduring normal power conversion, however, conduction lossPublished in IET Power ElectronicsReceived on 12th October 2010Revised on 18th April 2011doi: 10.1049/iet-pel.2010.0363

Flyback converter with novsecondary side post regulaconsumption under high-efJ.-H. Jung1 S. Ahmed2

1New and Renewable Energy System Research Center, SmaInstitute, Changwon, Republic of Korea2Department of Electrical and Computer Engineering, TexaDoha, QatarE-mail: jeehoonjung@keri.re.kr

Abstract: Flyback converters are widely used in industrial anstructure and low cost. Energy and environmental conservatiopower consumption in switch mode power supply applicsimultaneously because of conicting design considerations. A1058

& The Institution of Engineering and Technology 2011ISSN 1755-4535

l active clamp control andor for low standby powerciency operation

t Grid Research Division, Korea Electrotechnology Research

A&M University at Qatar, PO Box 23874, Education City,

commercial products because of their advantages of simplen have prompted interest in high efciency and low standbytions. However, it is difcult to satisfy both conditionsnovel active clamp control method is proposed for improvingIET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363

www.ietdl.orgcaused by continuous primary current and additionalswitching loss consumed by the active clamp switch inducehigh power loss in standby-mode operation. The activeclamp switchs proposed control method can reduce theconduction and switching losses using a switch disablesignal in standby mode. Additionally, the proposed SSPRprevents energy leakage in standby mode by disconnectingunused output channels from the load. Cross-regulationperformance is also improved by the SSPR withoutadditional switching operations, complicated control anddrive circuits. Operational principles, design considerationsand proposed control schemes of the active clamp switchand the SSPR will be presented. Improvements in powerconversion efciency and cross-regulation performance inthe normal and standby modes will be veriedexperimentally on 110 W prototype converter.

2 Operational principles and designconsiderations

2.1 Flyback converter with active clamp

The incorporation of an active clamp circuit into the ybacktopology is shown in the primary side in Fig. 1a. In thisgure, the yback transformer is replaced with anequivalent circuit model showing the magnetising andleakage inductances on the primary side, Lm and Llk,respectively. Explanations of the topological states,operational waveforms and design guidelines of the activeclamp yback converter are well documented in theliterature [414].The proposed converter uses a high-side clamp structure to

decrease the voltage across the clamp capacitor and reducesMOSFET cost compared to a low-side clamp structure. Inthe case of a low-side clamp structure as shown in Fig. 1b,the maximum voltage of the clamp capacitor, vc,max, can bederived from (1)

vc, max =Vi

1 Dmax(1)

where Vi is the dc input voltage and Dmax is the maximumduty ratio of S1 as shown in (2)

Dmax =nVo1

nVo1 + Vi,min(2)

where n is the turn ratio between the transformer primarywinding and secondary winding, Vo1 is the controlled mainoutput voltage and Vi,min is the minimum dc input voltage,respectively. Since clamp capacitor voltage stress isproportional to the input voltage, low-side clamps aredisadvantageous to their high-side counterpart.Additionally, a more expensive P-channel MOSFET is alsoneeded because of the body diode direction.The maximum clamp capacitor voltage vc,max of the high-

side clamp structure can be calculated as in (3)

vc,max =Dmax

1 DmaxVi (3)

Here, the input voltage is scaled down by the duty cycle;hence, the clamp capacitor has lower voltage stress.Additionally, a cheaper N-channel device can be used as aclamp MOSFET. Another consideration is the complexityIET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363of the gate drive of the active clamp MOSFET. Typically, ahigh-side clamping MOSFET requires an additional boot-strap driver or gate transformer, however, the proposedconverter uses a self-driven gate driver merged with thetransformer. It does not require the boot-strap driver or gatetransformer but needs an additional transformer winding,resistor and zener diode.The schematic of the self-driven gate driver and its standby

control used in the converter are shown in Figs. 1c and d,respectively. A design procedure of the gate driver issuggested covering the additional gate drive windingincluded in the transformer T, gate resistor Rg, and zenerdiode Dz. First, the winding turn ratio should consideraverage and peak voltages applied to the primary windingof the transformer because the induced voltage on theprimary winding determines the gate voltage of the activeclamp MOSFET, S2. This induced voltage is transferredthrough the gate winding. Second, the gate resistanceshould consider the gate-source capacitance of S2 to obtaina proper switching speed. The switching speed of S2 isdetermined by the multiplication value of Rg and the gate-source capacitance. Finally, the zener breakdown voltage of

Fig. 1 Schematics of the proposed converter and circuits

a Flyback with high-side active clamp circuit and SSPRb Low-side active clamp circuitc Self-driven gate driver for active clamp MOSFETd Standby control for active clamp gate driver1059

& The Institution of Engineering and Technology 2011

www.ietdl.orgDz should consider the maximum rating of the gate voltage ofS2 to protect the switch. The standby controller of the activeclamp gate driver in Fig. 1d will be discussed in the nextsection.

2.2 Secondary side post regulator

Fig. 2a shows the control and drive circuits of the proposedSSPR. This circuit is composed of three parts: voltagereference generation, intelligent function control and gatevoltage control. The voltage reference circuit is designedusing a shunt voltage regulator to generate the outputreference voltage. In Fig. 2a, this circuit is composed of theshunt regulator, R4, R5 and R6. The anode and reference ofthe shunt regulator are connected to the output voltage, Vo2,and its cathode, respectively. Resistor R4 supplies theoperating energy of the shunt regulator from a secondaryauxiliary winding. If the reference voltage of the shuntregulator is Vsr, then the output reference voltage, Vr2, isdetermined by R5 and R6 as in (4)

Vr2 =R6

R5 + R6(Vo2 + Vsr) (4)

The error amplier is implemented using an opamp and aproportional integral (PI) feedback loop. If the entire systemis stable, the output voltage, Vo2, will equal the referencevoltage, Vr2, at steady state. In this case, the two opamp-inputs become virtually shorted. Therefore the outputvoltage regulated by the SSPR can be calculated from (5)accounting for the ratio of the resistances R5 and R6,k R6/(R5+ R6).

Vo2 = Vr2 =Vsr

1 k (5)

From (5), the voltage reference circuit can be designed to setthe required output voltage.

Fig. 2 Control and operation of the proposed SSPR

a Drive circuitb Operating point of the SSPR series MOSFET1060

& The Institution of Engineering and Technology 2011The principle of operation of the SSPR is as follows: thedifference between the output voltage controlled by theSSPR and the reference voltage set by the voltage referencecircuit is amplied by the error amplier to generate thegate voltage of the SSPRs series MOSFET. Fig. 2billustrates the relation between the gate voltage level andthe operating point of the SSPR series MOSFET. Bycontrolling the operating point, the SSPR can regulate theoutput voltage by changing its drain-source impedance. InFig. 2b, the drain-source impedance, RQ, at the operatingpoint Q, can be obtained from (6)

RQ =VSQISQ

(6)

where VSQ and ISQ are the operating voltage and current of theSSPRMOSFET, respectively. Therefore in Fig. 1a, the outputvoltage, Vo2, which is regulated by the proposed SSPR can beexpressed as in (7)

Vo2 = VCs RsIs (7)

where VCs is the voltage across the stabilising capacitor Cs,and Rs and Is are the drain-source resistance and current ofSs, respectively. From (7), the output voltage, Vo2, can beregulated by proper selection of the series MOSFETresistance, Rs, controlled by the SSPR.

3 Novel control schemes

3.1 Control scheme of the active clamp switch

The active clamp circuit contributes to the switching powerloss of the two MOSFETs and increased conduction lossdue to the primary current. In standby mode, a limitedswitching operation such as burst mode or skip cycleoperation is required to reduce power losses. The self-driven active clamp gate driver with the proposed standbycontrol input was illustrated in Fig. 1c. The gate transformerwinding of the self-driven driver is coupled to main powertransformer windings. When the primary switch S1 turns on,the zener diode Dz in the gate driver conducts and theactive clamp switch S2 turns off. In contrast, when S1 turnsoff, the current generated by the gate transformer windingpasses through the gate resistor Rg and gate voltage isinduced, consequently S2 turns on. Gate resistance Rg limitsthe gate current and the switching speed of S2. The zenerdiode Dz clamps the maximum gate voltage of S2 to itsbreakdown voltage.In Fig. 1c, the proposed active clamp switch can be

controlled using the standby control signal. If the standbycontrol signal is high, the photo coupler turns on and thegate voltage of S2 becomes zero, disabling the active clampcircuit. When the control signal is low, the active clampcircuit will operate with the gate voltage generated by theself-driven gate driver. The standby control circuit uses thephoto coupler due to galvanic isolation between the primaryand secondary sides. Standby-mode information is usuallyobtained from the converters secondary side. Amicrocontroller can be used to measure the output channelvoltage and to issue the needed control signals. When theactive clamp switch is disabled, the converter can operateunder the burst or skip cycle modes to reduce switchinglosses in standby mode. The voltage clamping operation isnot required in standby mode, since a much smaller leakageIET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363

www.ietdl.orgcurrent induces much lower voltage spikes on the powerswitch.

3.2 Control scheme of SSPR

In this subsection, output voltage control of the SSPR isanalysed using a small signal model. Assuming that thestabilising capacitor, Cs, is large enough to emulate a stiffvoltage source, the power stage of the second outputchannel can be changed to the small signal model inFig. 3a, where the input voltage source is Vin, the seriesMOSFET current is Is, the effective series resistance (ESR)of Co2, rc2 and the series MOSFET channel resistance, Rs.The variables vin, rs, is and vo2 are the small signals of Vin,Rs, Is and Vo2, respectively. Ze is the output lterimpedance seen from the series MOSFETs side. Thetransfer function between vo2 and rs, Gr(s), can be derivedby assuming time-invariant Vin ( vin = 0) and small rc2 asin (8).

Gr(s) =vo2rs

= Vo2Ro2 + Rs

1+ sCo2Ro21+ s(Co2Ro2(Rs + rc2)/(Ro2 + Rs))

( )(8)

In Fig. 2a, the PI controllers gain is determined by C1, C2and R2. Assuming that the SSPR operates at steady state,the two opamp-inputs are virtually shorted. Then, using (5),the amplied gate voltage of the series MOSFET, Vg, canbe obtained in the Laplace domain as in (9)

Vg(s) =Zc(s)

R1Vo2 + 1

Zc(s)

R1

( )Vsr

1 k (9)

Fig. 3 Small signal models of the output channel and SSPR

a Power stageb Entire power and control stageIET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363where Zc is the impedance of the controllers feedback loopand can be expressed as in (10).

Zc(s) =sC1R2

s(C1 + C2)(1 s(C1C2/(C1 + C2)R2))(10)

Because Vsr is a time-invariant reference voltage, the PIcontroller transfer function, Gc(s), can be obtained usingsmall signal modelling as in (11)

Gc(s) =vgvo2

= 1+sC1R2s(C1+C2)R1[1+s(C1C2/(C1+C2))R2]

(11)

where vg is the small signal of Vg.Fig. 3b shows the entire small signal model of the closed-

loop SSPR system. In Fig. 3b, Gm is the small signal gain ofthe MOSFET channel resistance, Rs, for different gatevoltage, Vg, as in (12)

Gm =rsvg

(12)

where rs is the small signal of Rs.Gm can be obtained from theturn-on drain-source resistance against gate voltage data inthe manufacturers data sheets. From (8), (11) and (12), theclosed-loop gain of the entire SSPR, T (s), can be derived asin (13).

T (s) = Gr(s)GmGc(s) (13)

Table 1 shows the SSPR parameters of the passivecomponents used in the prototype 110 W converter. From(13) and the parameters, the stability and dynamics of theoverall SSPR system can be analysed. Fig. 4 showsthe bode diagram of T (s) with the designed parameters. Thegain and phase margins of the SSPR overall system areinnite and 1528, respectively. The SSPR is a highly stablesystem whose stability is not affected by its gain. It alsopossesses considerable phase margin. Hence, it istheoretically acceptable for the controllers gain to tend toinnity since overshoots and/or oscillations will be dampedby the high phase margin.

4 Performance improvements

4.1 Improvements in normal mode

The leakage energy, Elk, not transferred to the secondarypower stage can be calculated from (14)

Elk =1

2Llki

2p,max (14)

Table 1 Parameters of the SSPR control and drive circuit

Parameter Value, V Parameter Value

Ro 1.0 103 Co 1.5 1023 FRs 10 C1 4.7 1026 FR1 1.0 104 C2 4.7 1027 FR2 1.2 102 Vo 2.4 101 VR5 2.0 103 Vsr 2.5 VR6 2.0 104 rc 1.0 1022 V1061

& The Institution of Engineering and Technology 2011

www.ietdl.orgwhere ip,max is the maximum primary current. The activeclamp circuit can save this energy in the clamp capacitorand transfer it to the secondary side during the turn-offphase of the main power switch, S1. Additionally, the activeclamping operation can suppress voltage spikes of thepower switch in a lossless fashion. Without the clampcircuit, the leakage energy charges the output capacitance,Cs1, with a high voltage spike. The maximum voltage of S1including the voltage spike can be calculated using (14) asshown in (15)

Vs1,max = Vi + nVo1 + ip,maxNameMeNameMeNameMeNameMeLlkCs1

(15)

Compared to the output voltage, Vo1, the forward voltage dropof the rectier is small enough and can be ignored.If a conventional RCD clamp circuit is used, the maximum

switch voltage can be calculated from (16), where Rc is theclamp resistor and fs is the switching frequency, respectively.

Vs1,max = Vi +nVo12+ 12

NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMe(nVo1)

2 2RcLlki2p,max fs

(16)

The RCD clamp capacitor, Ccl, is selected using (17).

Ccl =Cs1Llk Vs1,max Vi

ip,max fsRc(17)

By proper resistor and capacitor selection, voltage spikes onthe power switch can be suppressed. However, the powerdissipation from the RCD clamp circuit, Pc, increasesproportionally with the square of the maximum primarycurrent as shown in (18)

Pc =1

2i2p,max Llk fs

Vs1,max ViVs1,max Vi nVo1

(18)

Therefore the RCD clamp reduces the power conversionefciency. The maximum switch voltage with the activeclamp is given by (19).

Vs1,max =Vi

1 Dmax(19)

Fig. 4 Bode plot of the SSPR with gain and phase margins1062

& The Institution of Engineering and Technology 2011Without any power loss in the active clamp circuit, thevoltage spike on the power switch is limited by the activeclamping operation.From (7), the SSPR can regulate the uncontrolled output

voltage; therefore it can improve cross-regulationperformance among multiple output channels. Moreover,the operating power consumption of the SSPR is lower thanthe power consumption of conventional SPRs. Theswitching loss of the SPR series MOSFET, Ploss,SS, is givenby (20) [28]

Ploss,SS = QgVgr fs +1

2CssV

2ss fs (20)

where Qg is the total gate charge, Vgr is the gate voltage, Css isthe equivalent output capacitance and Vss is the drain-sourcevoltage of the series MOSFET, respectively. Since Vssdepends on the output voltage, it is relatively low for lowoutput voltages. The main switching loss component iscaused by the rst term of (20), which is governed by Qgand fs.The power loss of a SPRs control circuit, Ploss,SC, is given

by (21)

Ploss,SC = VccIop (21)

where Vcc is the supply voltage and Iop is the averageoperating current of SPRs control circuit. This controlcircuit consumes operating energy comparable to that of thePWM controller because of its synchronous switching. Iopwill be in the order of mA, and Ploss,SC will also behundreds of mW. Therefore Ploss,SC as well as Ploss,SS aresignicant power loss components in the SPR.On the other hand, the proposed SSPR consumes much less

energy than the SPR. Switching losses do not exist becausethere are no switching operations in the SSPR, instead, thecontroller only changes the value of gate voltage. Thereforethe power loss caused by Qg is much smaller than that ofthe SPR. In the SSPR control circuit, power consumption isdetermined by the opamp adopted for the error amplier. Inthe proposed SSPR, the ON Semiconductor MC33072 isused. This device consumes 50 mW when powered using a12 V rail. Consequently, the drive and control circuit of theproposed SSPR consume much less operating power thanthe SPR case. The output voltage regulation of the proposedSSPR is similar to the regulation action of the conventionallinear low-dropout (LDO) regulator. However, there is noconsideration of the reduction of standby powerconsumption in the LDO regulator.

4.2 Improvements in standby mode

With the active clamp topology, zero voltage switching of themain power switch S1 requires sufcient energy stored in theleakage inductance to completely discharge the MOSFEToutput capacitance [4, 7]. However, this leakage energy isnot enough to fully discharge the capacitance in standbymode because the primary current becomes minimal. Underthis situation, the summation of turn-on switching and gatedrive losses of the main and active clamp MOSFETs,Psw,AC, can be calculated as in (22)

Psw,AC =1

2Cs1

Vi1 D

( )2fs + 2QgsVgs fs (22)IET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363

www.ietdl.orgwhere D is the duty ratio of S1, Qgs and Vgs are the total gatecharge and gate voltage of S1 and S2, respectively. From (22),the switching loss of the MOSFET is proportional to theswitching frequency. In addition, the conduction loss of theprimary side, Pc,AC, can be calculated using the rms valueof the primary current as in (23)

Pc,AC =ReqViD

3

3fs(Lm + Llk)(23)

where Req is the equivalent series resistance of the primaryside, including winding resistance of the transformer anddrain-source turn-on resistance of the power MOSFET.In burst mode, the summation of turn-on switching and

gate drive losses of the power switch, Psw,BM is as shownin (24), where fb is the switching frequency of the burst mode.

Psw,BM =1

2Cs1V

2i fb + QgsVgs fb (24)

fb is usually several orders of magnitude lower than thenormal switching frequency fs. Therefore the total switchingloss in burst mode is signicantly lower than the switchingloss of the active clamping operation. Additionally, theconduction loss in burst mode can be calculated as in (25)

Pc,BM =ReqViD

3b

3fb(Lm + Llk)(25)

where Db is the duty ratio of S1 under burst mode. Although fbis lower than fs, Pc,BM is less than Pc,AC because Db is smallerthan the normal mode duty ratio, D, and the conduction loss isproportional to the duty ratio cubed.Figs. 5a and b show the converters secondary circuit with

and without the proposed SSPRs turn-off function,respectively. Without disconnection of the unused outputchannels in Fig. 5a, the additional power loss in standbymode, Ploss,S, can be calculated from (26)

Ploss,S = PD2 + Prc2 + Po2,st (26)

where PD2 , Prc2 and Po2,st are the power losses due to theforward voltage drop of the output diode, Vf, the ESR ofthe output capacitor, rc2, and the output resistance instandby mode, Ro2,st, respectively. PD2 can be derived as in(27), where Vo2,r is the peak-to-peak value of the output

Fig. 5 Output power loss comparison in standby mode

a Without the SSPRb With the SSPRIET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363ripple voltage

PD2 = 2Co2VfVo2,r fs +VfVo2Ro2,st

(27)

The output voltage, Vo2, has DC and AC components becauseof the converters switching operation. Vo2 can be described interms of these two components as follows

Vo2 = Vo2,DC +Vo2,r2

(28)

where Vo2,DC is the DC value of Vo2. From (27) it is observedthat the load impedance and the voltage ripple caused by thePWM switching affect the power consumption in the outputrectier, D2. The load impedance is also a dominant factorin PD2 because Vo2,r is much smaller than Vo2.Prc2 can be calculated as in (29)

Prc2 = 4C2o2V

2o2,r f

2s rc2 (29)

From (29), Prc2 will be a relatively small value since rc2 issmall and Vo2,r is also small in standby mode. Po2,st is givenby (30)

Po2,st =V 2o2Ro2,st

(30)

Therefore the disconnection of unused output channels by theSSPR is an important and efcient method to eliminate powerleakage through the output channels.In Fig. 5b, there is no power loss in the unused output

channel when the SSPR turns off. It is assumed that thepower losses caused by the ESR of the stabilising capacitor,Cs, and by the output rectier, D2, are negligible. This isdue to the fact that the stabilising capacitor will have verylow ripple voltage, hence capacitor ESR will have littleeffect. Additionally, only the capacitor discharge currentpasses through D2, which is also negligible. Thus,compared to the case without a SSPR, apparent power lossadvantages exist.

4.3 Soft turn-on function of the SSPR

In Fig. 2a, there are two switches controlled by the standbycontrol signal to turn on and off the SSPR. The turn-offfunction can disconnect the unused output channel(s) fromthe load to eliminate the power leakage in standby mode. Asoft turn-on is also required to protect power devices of theSSPR from high voltage or current stress. An instant turn-on of the secondary regulator can cause electrical damageto the load devices and the regulator itself due to currentand voltage spikes. The proposed SSPR uses a soft turn-onfunction to prevent high voltage and current pulses causedby discharged output capacitors in the converters outputchannels. Degradation and/or damage of the outputcapacitors, the SSPRs MOSEFT and diode may otherwiseresult. Voltage uctuation of other output channels causedby the inrush current is also prevented using the soft turn-on.This function can be realised using the soft turn-on

capacitor, C3, in Fig. 2a. The voltage across R6, VR6 , can be1063

& The Institution of Engineering and Technology 2011

www.ietdl.orgcalculated from (31)

VR6 (t) = k(Vo2 + Vsr) 1 exptR6C3

( )[ ](31)

where t is the time parameter. The time duration of the softturn-on, tst, can be evaluated using (32). Larger values ofR6 and C3 will result in a long turn-on time duration.

tst = R6C3 (32)

5 Experimental results

5.1 Switch voltage and efficiency

Figs. 6a and b show the prototype 110 W SMPS and theSSPR printed circuit board (PCB) layout used in theexperiment, respectively. This converter has a singlecontroller, two outputs, an active clamp circuit, and its non-feedback controlled output channel is regulated using theproposed SSPR. In normal operation, the active clampcircuit suppresses voltage spikes of the main switch and theSSPR regulates the voltage of the non-feedback outputchannel. In standby mode, the active clamp switch andSSPR turn off to reduce unnecessary power consumption.Figs. 7a and b show voltage and current waveforms of the

conventional quasi-resonant (QR) yback converter with theRCD clamp and the proposed converter with the active clampand SSPR. Input voltage of the two converters was 220 Vrms

Fig. 6 Photograph of real circuit

a 110 W converter sampleb PCB assembly of the SSPR1064

& The Institution of Engineering and Technology 2011and rated output power was 110 W. In Fig. 7b, the maximumdrain-source voltage stress of S1 is limited to 512 V by theactive clamp operation. In Fig. 7a, the RCD clampsuppresses the voltage spike to 580 V. A clamp resistancecan suppress the voltage spike of S1 to less than 580 V;however, it consumes more energy. A lower value clampresistance reduces power conversion efciency in normaloperation and standby modes.Fig. 8 shows power conversion efciency curves of the QR

yback converter with the RCD clamp and the SSPR, and theproposed active clamp yback converter with the SSPRaccording to the level of output power. Under low to mid-loadconditions, the efciency of the converter including theproposed methods is lower than the efciency of the

Fig. 7 Voltage and current waveforms under full-load condition

a With RCD clampb With active clamp

Fig. 8 Efciency curves of the proposed and RCD clamp ybackconvertersIET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363

www.ietdl.orgconventional QR yback converter with the RCD clampbecause of additional power losses caused by the drivecircuits of the active clamp and the SSPR. The powerconversion efciency of the converter containing the RCDclamp and the SSPR is located between the efciencies of theother two converters, since no power loss is caused by anactive clamp. However, the power conversion efciency of theproposed converter is similar to the efciency of theconventional converter under high loads. Even thoughthe conduction loss of the SSPRs series MOSFET increasesthe power loss during the power conversion, the activeclamping operation can compensate this power loss byrecycling leakage energy. Compared to the efciency of theconventional RCD clamped converter including the SSPR, theproposed converter shows 3.3% efciency improvement at110 W rated output power. From Fig. 8, the power losscaused by the SSPR increases proportionally with load currentbecause of its conduction loss. Using the active clamp circuit,however, the power loss can be compensated under highloads. Additionally, the next subsection will illustrate howemploying the SSPR can save standby power consumption.

5.2 Standby power consumption

Figs. 9a and b show voltage and current waveforms of theactive clamp and burst operation cases in standby mode.The operating frequency of the burst mode is 2.94 kHz,which is much lower than the 40 kHz switching frequencyof the active clamp operation. In Fig. 9b, the maximum

Fig. 9 Voltage and current waveforms under standby mode

a Active clamp operation caseb Burst mode operation case with active clamp turned-offIET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067doi: 10.1049/iet-pel.2010.0363voltage stress of the power switch is limited to 512 Vwithout any clamp circuits because of the extremely lowleakage current.Table 2 shows the power consumption of the SMPS under

the no load and standby mode conditions for a laser printerapplication. The output power consumption in standby modeis almost 0.3 W (5 V/60 mA) in this application. The leftside of Table 2 shows the power consumption using aconventional converter without the proposed switch controlmethod and SSPR. The right side is the standby powerconsumption when the proposed techniques are used.Standby power is saved by inhibiting the active clampoperation, reducing the switching frequency using burstmode and preventing energy leakage using the SSPR.Reduction ratios at the no load and standby mode conditionsare 83 and 63.7 %, respectively. From Table 2 it can beconcluded that power consumption due to the active clampsincreased conduction current, and power leakage through theunused channel is approximately 2.2 W for this laser printer.Without preventing these power losses, it would be verychallenging to reduce standby mode power consumption.

5.3 Cross-regulation and soft turn-on

Table 3 shows the specic cross-regulation performance datafor the worst-case scenario. Since the rst output voltage, Vo1,is always tightly controlled by the PWM controller, onlyvariations in the second output voltage, Vo2, are regulatedby the SSPR in Table 3. When the Vo1 load is maximumand the Vo2 load is zero, the regulation of Vo2 deterioratesdrastically. The actual output voltage shows 150% increaseagainst the 24 V reference for Vo2 under these conditions.The proposed SSPR suppressed this non-feedbackcontrolled output voltage to under 25 V. Thus, the SSPRcan regulate its output voltage to within 4%.Figs. 10a and b show the output voltage and current

waveforms of the SSPR in the hard and soft turn-on cases.From (31) and (32), larger values of R6 and C3 will result ina long turn-on time duration. Without the soft turn-onfunction of the SSPR, there is a high is current spike up to28 A. In addition, the voltage uctuation of Vo1 and theovershoot of Vo2 are shown. The abnormal current spikecaused by the hard turn-on of the SSPRs MOSFETinuences the regulation of Vo1 since this disturbance can betransferred to another output channel through the transformer.However, the current spike is limited to 15 A by the softturn-on function of the SSPR, as shown in Fig. 10b, and nouctuation and/or overshoot occurs on the output voltages.

Table 2 Standby power consumption

Active clamp Burst mode with SSPR

No load Standby No load Standby

2.65 W 3.04 W 0.45 W 0.86 W

Table 3 Cross-regulation performance

Output voltage

(Vr2 24 V)Load conditions

5 V/0 A, 24 V/4 A 5 V/3 A, 24 V/0 A

without SSPR 22.8 V 36.2 V

with SSPR 22.7 V 24.9 V1065

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www.ietdl.org6 Conclusions

This work proposes control schemes for an active clampswitch and a SSPR for multiple output yback converters.The active clamp circuit is adopted to reduce the voltagestress on the main power switch and recycle leakage energyto increase power conversion efciency in the mid to high-load ranges. The active clamp switch is turned off duringburst-mode operation to decrease the converters switchingand conduction losses in standby mode. The proposedSSPR improves the cross-regulation performance andprevents energy leakage from the unused output channel.Soft turn-on of the SSPR is employed to reduce outputvoltage distortions and inrush current stress of the SSPRsseries MOSFET. The prototype 110 W converter consumedonly 0.45 and 0.86 W in the no load and standby modes,respectively. The second output voltage was regulated towithin 4% perturbation. A 54% reduction in the SSPRsMOSFET current stress was achieved without outputvoltage distortions. Finally, the conduction loss caused bythe SSPR was compensated using the active clampingoperation in the mid to full-load ranges, and the proposedconverter showed 3.3% efciency improvement at the ratedload.

7 Acknowledgment

This work was made possible by the advanced researchproject The Standardisation of Next Generation SMPSs forLaser Printers, which was supported by the Digital Printing

Fig. 10 Voltage and current waveforms of the SSPR

a Without the soft turn-on functionb With the soft turn-on function1066

& The Institution of Engineering and Technology 2011Division of SAMSUNG Electronics Co., Ltd, and by thesupport of an NPRP grant from the Qatar National ResearchFund.

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