(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
8 9
5-3-1-1 is possible but 6-4-1-1 is not because there is no way to represent 3 or 9 Alternate Solutions
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
11
(A + B + C + D) (A + B + C + E) (A + B + C + F)= A + B + C + DEF
Apply second distributive law (Th 8D) twice
See FLD p 626 for solution21
Unit 2 Problem Solutions
22 (a) In both cases if X = 0 the transmission is 0 and if X = 1 the transmission is 1
22 (b) In both cases if X = 0 the transmission is YZ and if X = 1 the transmission is 1
For the answer to 23 refer to FLD p 62623
F = [(Amiddot1) + (Amiddot1)] + E + BCD = A + E + BCD24 (a) Y = (AB + (AB + B)) B + A = (AB + B) B + A = (A + B) B + A = AB + B + A = A + B
24 (b)
(A + B) (C + B) (D + B) (ACD + E) = (AC + B) (D + B) (ACD + E) By Th 8D = (ACD + B) (ACD + E) By Th 8D = ACD + BE By Th 8D
25 (a) (A + B + C) (A + C + D) (B + D) = (A + C + BD) (B + D) By Th 8D with X = A + C= AB + BC + BBD + AD + CD + BDD = AB + AD + CB + CD
25 (b)
AB + CD = (AB + C) (AB + D) = (A + C) (B + C) (A + D) (B + D)
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
12 13
ABC + (ABC) = 1 By Th 5
A + B + CD(A + B) = A + B + CD By Th 11D
[AB + (CD) +EF]CD = ABCD + EFCD By Th 8
F1 = AA + B + (B + B) = 0 + B + B = B
F3 = [(AB + C)D][(AB + C) + D] = (AB + C)D (AB + C) + (AB + C) D= (AB + C) D By Th 5D amp Th 2D
ACF(B + E + D)
A(B + CD) + B + CD = B + CD By Th 10
(AB + CD)(AB + CE) = AB + CDE By Th 8D
(A + BC)(DE + F) + (DE + F) = DE + F + A + BC By Th 11D
211 (a)
212 (a) (W + X + YZ)(W + X + YZ) = X+ YZ By Th 9D
(V + WX)(V + WX + YZ) = V + WX By Th 10D
(V + U + W)(WX + Y + UZ) + (WX + UZ + Y) = WX + UZ + Y By Th 10
(X + YZ)(X + YZ) = 0 By Th 5
(VW + X) (X + Y + Z + VW) = (VW + X) (Y + Z) By Th 11
(W + X)YZ + (W + X)YZ = YZ By Th 9
213 (a) F2 = AA + AB = A + AB = A + B
Z = [(A + B)C] + (A + B)CD = [(A + B)C] + DBy Th 11D with Y = [(A + B) C] = AB + C + D
214 (a) W + Y + Z + VUX
211 (c)
211 (e)
211 (b)
211 (d)
211 (f)
212 (c)
212 (e)
212 (b)
212 (d)
212 (f)
213 (c)
213 (b)
213 (d)
214 (b)
F = [(A + B) + (A + (A + B))] (A + (A + B)) = (A + (A + B)) By Th 10D with X=(A+(A+B))
= A(A + B) = AB
29 (a) G = [(R + S + T) PT(R + S)] T = (R + S + T) PT(R + S) + T = T + (RST) P(RS)T = T + PRSTT = T
29 (b)
XY
X Y
X
Y
XY X Y
X Y
X
B
A
Z Y Z
XB
AC
B
AC
Y
X
Z
X
Y Z
X
Y
XX
Y
X
210 (a) 210 (b)
210 (c)210 (d)
210 (e) 210 (f)
12 13
ABC + BCD + EF = ABC + BCD + EF = BC (A + D) + EF = (BC + EF) (A + D + EF) = (B + E) (B + F) (C + E) (C + F ) (A + D + E) (A + D + F)
WXY + WX + WY = X(WY + W) + WY = X(W + Y) + WY = (X + W) (X + Y) (W + Y + W) (W + Y + Y) = (X + W) (X + Y) (W + Y)
AB + (CD + E) = AB + (C + E)(D + E) = (AB + C + E)(AB + D + E) |= (A + C + E)(B + C + E)(A + D + E)(B + D + E)
ABC + ADE + ABF = A(BC + DE + BF) = A[DE + B(C + F)] = A(DE + B)(DE + C + F) = A(B + D)(B + E)(C + F + D)(C + F + E)
[(XY) + (X + Y)Z] = X + Y + (X + Y)Z = X + Y + Z By Th 11D with Y = (X + Y)
[(A + B) + (ABC) + CD] = (A + B)ABC(C + D) = ABC
215 (d)
216 (a)
217 (a) (X + (Y(Z + W))) = XY(Z + W) = XYZW
(A + B) CD + (A + B) = CD + (A + B) By Th 11D with Y = (A + B)
= CD + AB
HI + JK = (HI + J)(HI + K) = (H + J)(I + J)(H + K)(I + K)
ABC + ABC + CD = C(AB + AB + D) = C[(A + B)(A + B) + D] = C(A + B + D)(A + B + D)
AB + ACD + ADE = A(B + CD + DE) = A[B + D(C + E)] = A(B + D)(B + C + E)
215 (a)
215 (b)
215 (c)
215 (e)
215 (f)
216 (b)
216 (c) 216 (d)
W + XYZ = (W + X)(W + Y) (W + Z) VW + XY + Z = (V+X+Z)(V+Y+Z)(W+X+Z)(W+Y+Z)
ABC + BCD + BE = B(AC + CD + E) = B[E + C(A + D)] = B(E + C)(E + A + D)
217 (c)
217 (b)
217 (d)
F = [(A + B)B]C + B = [A + B + B]C + B = C + B
H = [WX(Y + Z)] = W + X + YZ
218 (a)
219
220 (a)
G = [(AB)(B + C)]C = (AB + BC)C = ABC
F = (V + X + W) (V + X + Y) (V + Z)= (V + X + WY)(V + Z) = V + Z (X + WY) By Th 8D with X = V
F = ABC + ABC + ABC + ABC = BC + ABC + ABC (By Th 9)
= C (B + AB) + ABC = C (A+ B) + ABC (By Th 11D)
= AC + BC + ABC = AC + B (C + AC) = AC + B (A + C) = AC + AB + BC
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
12 13
ABC + BCD + EF = ABC + BCD + EF = BC (A + D) + EF = (BC + EF) (A + D + EF) = (B + E) (B + F) (C + E) (C + F ) (A + D + E) (A + D + F)
WXY + WX + WY = X(WY + W) + WY = X(W + Y) + WY = (X + W) (X + Y) (W + Y + W) (W + Y + Y) = (X + W) (X + Y) (W + Y)
AB + (CD + E) = AB + (C + E)(D + E) = (AB + C + E)(AB + D + E) |= (A + C + E)(B + C + E)(A + D + E)(B + D + E)
ABC + ADE + ABF = A(BC + DE + BF) = A[DE + B(C + F)] = A(DE + B)(DE + C + F) = A(B + D)(B + E)(C + F + D)(C + F + E)
[(XY) + (X + Y)Z] = X + Y + (X + Y)Z = X + Y + Z By Th 11D with Y = (X + Y)
[(A + B) + (ABC) + CD] = (A + B)ABC(C + D) = ABC
215 (d)
216 (a)
217 (a) (X + (Y(Z + W))) = XY(Z + W) = XYZW
(A + B) CD + (A + B) = CD + (A + B) By Th 11D with Y = (A + B)
= CD + AB
HI + JK = (HI + J)(HI + K) = (H + J)(I + J)(H + K)(I + K)
ABC + ABC + CD = C(AB + AB + D) = C[(A + B)(A + B) + D] = C(A + B + D)(A + B + D)
AB + ACD + ADE = A(B + CD + DE) = A[B + D(C + E)] = A(B + D)(B + C + E)
215 (a)
215 (b)
215 (c)
215 (e)
215 (f)
216 (b)
216 (c) 216 (d)
W + XYZ = (W + X)(W + Y) (W + Z) VW + XY + Z = (V+X+Z)(V+Y+Z)(W+X+Z)(W+Y+Z)
ABC + BCD + BE = B(AC + CD + E) = B[E + C(A + D)] = B(E + C)(E + A + D)
217 (c)
217 (b)
217 (d)
F = [(A + B)B]C + B = [A + B + B]C + B = C + B
H = [WX(Y + Z)] = W + X + YZ
218 (a)
219
220 (a)
G = [(AB)(B + C)]C = (AB + BC)C = ABC
F = (V + X + W) (V + X + Y) (V + Z)= (V + X + WY)(V + Z) = V + Z (X + WY) By Th 8D with X = V
F = ABC + ABC + ABC + ABC = BC + ABC + ABC (By Th 9)
= C (B + AB) + ABC = C (A+ B) + ABC (By Th 11D)
= AC + BC + ABC = AC + B (C + AC) = AC + B (A + C) = AC + AB + BC
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
(A + B + C + D) (A + B + C + D) (A + C) (A + D) (B + C + D)
= (B + C + D) (A + C) (A + D) = (B + C + D) (AD + AC) Using (X + Y) (X + Z) = XY + XZ with X = A= ADB + ADC + AD + ABC + AC + ACD = AD + AC
36 (b)
37 (a) BCD + CD + BCD + CD
= CD + C(D + BD) = (C + D) [C + (D + BD)] Using (X + Y) (X + Z) = XY + XZ with X=C= (C + D) [C + (D + B) (D + D)] = (C + D) (C + D + B)
37 (b) ACD + ABD + ACD + BD
= D (AC + AB) + D (AC + B) = D [(A + B) (A + C)] + D [(B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) twice inside the brackets= [D + (A + B) (A + C)] [D + (B + A) (B + C)] Using XY + XZ = (X + Y) (X + Z) with X = D = (D + A + B) (D + A + C) (D + B + A) ( D + B + C) Using the Distributive Law
38F = AB oplus [(A equiv D) + D] = AB oplus (AD + AD + D) = AB oplus (AD + D) = AB oplus (A + D) = (AB) (A + D) + AB(A + D) = (A + B) (A + D) + AB(AD) = A + BD + ABD Using (X + Y) (X + Z) = X + YZ = A + BD + BD Using X + XY = X + Y
39 A oplus BC = (A oplus Β) (Α oplus C) is not a valid distributive law PROOF Let A = 1 B = 1 C = 0 LHS A oplus BC = 1 oplus 1 middot 0 = 1 oplus 0 = 1 RHS (A oplus B) (A oplus C) = (1 oplus 1) (1 oplus 0) = 0 middot 1 = 0
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
= ABC + A (B + C) + BD + ACD = ABC + AB + AC + BD + ACD
= ABC + AB + AC + AD + BD + ACD(Add consensus term AD eliminate ACD)
= ABC + AB + AC + BD(Remove consensus term AD)
(X + W) (Y oplus Z) + XW = (X + W) (YZ + YZ) + XW
= XYZ + XYZ + WYZ + WYZ + XW
Using Consensus TheoremWYZ + WYZ + XW
310 (c) (A + C + D) (A + B + C) (A + B + D) (A + C + D)
= (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + C + D) Add consensus term
= (A + B + C) (A + B + D) = (A + C + D) (B + C + D) (A + C + D) Removing consensus terms
314 (a) ABCD + ABCD + CD = ABCD + CD = C(ABD + D) = C(D + AB) By Th 11D with Y = D = CD + ABC
311 (A + B + C + E) (A + B +D + E) (B + C + D + E) = [A + B + (C + E) (D + E)] (B + C + D + E) = (A + B + DE + CE) (B + C + D + E) = B + (A + DE + CE) (C + D + E) CD Add consensus term
= B + AC + AD + AE + CDE + DE + DE + CDE = B + AC + AD + AE + CD +CDE + DE
= B + AC + AE + CD + DE
312 ACDE + ABD + ABCE + ABD = ABD + ABD + BCDE
Proof LHS ACDE + BCDE + ABD + ABCE + ABD Add consensus term to left-hand side and use it to eliminate two consensus terms = BCDE + ABD + ABD This yields the right-hand sidethere4 LHS = RHS
(A + B + C) (A + C + D) (A + B) (A + D) (A + C + D)
= [A + D (B + C)] [A + B ( C + D)] = AD (B + C) + AB (C + D) = ADB + ADC + ABC + ABD
(A + C + D) (A + C) (B + C + D) (A + B + C) (C + D)
= (C + DB + AD) (C + AD) = C (BD + AD) + (CAD) Using XY + XZ = (X + Z)(X + Y) with X = C= CBD + CAD + CAD
313 (a)
313 (b)
(A + B + C) (A + D) (A + B + D) (A + B) (A + C + D)
= [A + (B + C) ( B + D)] (A + BD) = (A + BC + BD) (A + BD) By Th 14 with X = B= A (BC + BD) + ABD By Th 14 with X = A
= ABC + ABD + ABD
(A + B + C) (A + B + D) (A + B + C) (A + B + D) = ( A + B + CD) (A + B + CD)= A ( B + CD) + A( B + CD) By Th 14 with X = A = AB + ACD + AB + ACD
(A + B + C) (A + C + D) (A + B + C) (A + C + D) = (A + C + BD) (A + C + BD) = A(C + BD) + A(C + BD) = AC + ABD + AC + ABD
Alt solns AC + AC + BCD + BCD (or) AC + AC + ABD + BCD (or) AC + AC + ABD + BCD
313 (c)
313 (d)
313 (e)
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
16 17
(A + B) (A + B + D) (B + C + D) = B + A (A + D) (C + D) = B + AD (C + D) = B + ACD
ABC + CD + BCD = ABC + D(C + BC) = ABC + D(C + B) = ABC + CD + BD
314 (c)
314 (b)
ABC + ACD + ABC + BCD = C (AD + BD) + C (AB + AB) = C [(A + D) (B + D)] + C [(A + B) (A + B)] By Th 14 twice with X = D and X = B= [C + (A + D) (B + D) ] [C + (A + B) (A + B)] By Th 14 with X = C= (C + A + D) (C + B + D) (C + A + B) (C + A + B) By Distributive Law
315 (a)
314 (d)
AB + AB + BCD + BCD = B (A + CD) + B (A + CD) = (B + A + CD) (B + A + CD) By Th 14 with X = B= (B + A + C) (B + A + D) (B + A + C) (B + A + D)
315 (b)
(A + B + C + D) (A + C + D + E) (A +C + D + E) AC = [A + C + (B + D) (D + E) (D + E)] AC By Th 8D twice with X = A + C = [A + C + (B + D)D] AC = [A + C + D] AC = ACD
AB + ABC + BCD + BCD = B [AC + CD] + B [A + CD] = B [(C + D) (C + A)] + B [(A + C) (A + D)]= [B + (C + D) (C + A)][B + (A + C) (A + D)] = (B + C + D) (B + C + A) (B + A + C) (B + A + D)
315 (c)
ACD + ABD + ACD + BD = D (AC + B) + D (AB + AC) = D ( B + A) (B + C) + D (B + A) (A + C) = [D + (B + A) (B + C)] [D + (B + A) (A + C)] = (D + B + A) (D + B + C) (D + B + A) (D + A + C)
315 (d)
WXY + WXY + WYZ + XYZ = WY (X + X + Z) + XYZ = WY + XYZ = Y (W + XZ) = Y (W + X) (W + Z)315 (e)
(AB oplus C) + CD = (AB)C + ABC + CD = (A + B) C + ABC + CD = C (A + B) + C (AB + D) = (C + A + B) ( C + D + AB) = (C + A + B) (C + D + A) (C + D + B)
316 (a)
C (A oplus D) + CD + AD = C [AD + AD] + CD + AD = ACD + ACD + CD + AD = ACD + D (C + AC + A) = ACD + D (C + A + C) = ACD + D = D + AC = (A + D) (C + D)
316 (b)
(X oplus Y) oplus Z = X oplus (Y oplus Z) Proof LHS Let X oplus Y = AA oplus Z = AZ + AZ = (X oplus Y) Z + (X oplus Y) Z = (X oplus Y ) Z + (X equiv Y) Z By (3-18) on FLD p 61)= (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y oplus Z = B X oplus B = XB + XB = X (Y oplus Z) + X (Y oplus Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (a)
(X equiv Y) equiv Z = X equiv (Y equiv Z) Proof LHS Let X equiv Y = A(A equiv Z) = AZ + AZ = (X equiv Y) Z + (X equiv Y) Z = (X equiv Y ) Z + (X oplus Y) Z = (XY + XY) Z + (XY + XY) Z = XYZ + XYZ + XYZ + XYZRHS Let Y equiv Z = B (X equiv B) = XB + XB = X (Y equiv Z) + X (Y equiv Z) = X (Y equiv Z) + X (Y oplus Z) = X [YZ + YZ] + X [YZ + YZ] = XYZ + XYZ + XYZ + XYZ there4 LHS = RHS
317 (b)
BCD + ABC + ACD + ABD + ABD = BCD + ABC + ABD + ABD = ABC + ABD + ABD318 (a)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
18 19
(B + C + D) (A + B + C) (A + C + D) (B + C + D) = (A + B + C) (A + C + D) (B + C + D)318 (c)
Z = ABC + DE + ACF + AD + ABE = A (BC + CF + D + BE) + DE = (A + DE) (DE + BC + CF + D + BE) By Th 8D with X = DE
= (A + D) (A + E) (BC + CF + D + E + BE) = (A + D) (A + E) (D + E + B + BC + CF) Since E + BE = E + B = (A + D) (A + E) (D + E + B + C + CF) Since B + BC = B + C = (A + D) (A + E) (D + E + B +C) Since C + CF = C = (A + DE) (D + E + B + C)
= AD + AE + AB + AC + DE + DEB + DEC eliminate consensus term AE use X + XY = X where X = DE
= (X + Y) (X + Z) (Y + Z) Alt (X + Y) (Y + Z) (X + Z) by adding (Y + Z) as consensus in 3rd step
xy + xyz + yz = y (x + xz) + yz = xy + yz + yz = xy + y = y
Alternate Solution xy + xyz + yz = y (x + xz + z) = y (x + z + z) = y (x + 1) = y
322 (a) 322 (b)
322 (c) xy + z + (x + y) z = xy + (x + y) By Th 11D with Y = z= xy + x + y = x + x + y = 1 + y = 1Alt xy + z + (x + y) z = (xy + z) + (xy + z) = 1
322 (d)
(xy + z) (x + y) z = (xy + xz + yz) z = xyz + xz + yz = xz + yz
Alternate Solution (xy + z) (x+y) z = z ( x + y)
= zx + zy
ad (b + c) + ad (b + c) +(b + c) (b + c)
= abd + acd + abd + acd + bc + bc
= abd + abd + bc + bcOther Solutions bc + bc + acd + abd bc + bc + acd + acd bc + bc + abd + acd
318 (f) (A + B + C) (B + C + D) (A + B + D) (A + B + D) = (A + B + C) (B + C + D) (A + B + D)
F = AB + AC + BCD + BEF + BDF = (A + B) (A + C) + B (CD + EF + DF) = [(A + B) (A + C) + B] [(A + B) (A + C) + CD + EF + DF] = (A + B) (A + C + B) (A + B + CD + EF + DF) (A + C + CD + EF + DF ) B + C C + D= (A + B) (A + C + B) (C + B) (A + B + CD + EF + DF) (A + C + D + EF + DF)
= (A + B) ( B + C) (A + C + D + FE + DF) = (A + B) (B + C) (A + C + D + F + FE) = (A + B) (B + C) (A + C + D + F) = (B + AC) (A + C + D + F)
= (AB + BC + BD + BF + AC + ACD + ACF = AB + BD + BF + AC use consensus X + XY = X where X = AC
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
18 19
322 (e) wx + xy + yz + wz + xz Add redundant term
= wx + xy + yz + wz + xz
= xy + yz + wz + xz Remove redundant term
= xy + yz + wz322 (f)
322 (g) [(a + d + bc) (b + d + ac)] + bcd + acd = ad (b + c) + bd (a + c) +bcd + acd = abd + acd+ abd + bcd + bcd + acd
cd bd= abd + abd + bd + cd = abd + bd + cd
ABCD + ABCD+ BEF+ CDEG+ADEF+ABEF
= ABD + BEF + CDEG + ADEF (consensus)
= ABD + BEF + CDEG
324 325 (a)
325 (b) NOT VALID Counterexample a = 0 b = 1 c = 0 LHS = 0 RHS = 1 there4 This equation is not always validIn fact the two sides of the equation are complements [(a + b) (b + c) (c + a)] = [(b + ac) (a + c)] = [ab + ac + bc] = (a + b) (a + c) (b + c)
325 (c) VALID Starting with the right side add consensus termsRHS = abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + acd + acd
= abc + abc + bcd + bcd + ad = LHS
VALID ab + bc + ca = ab (c + c) + (a + a) bc + (b + b) ac = abc + abc + abc + abc + abc + abc
= ac + bc + ab Alternate Solution ab + bc + caAdd all consensus terms ab bc cathere4 We get = ab + bc + ca + ab + bc + ca
= ab + bc + ca
323 (a) 323 (b)ACD + AC + BCD + ACD + ABC + ABC
= AD + AC + BCD + ABC consensus
= AD + AC + BCD
ABC + ABD + AC + ACD + ACD + ABC
= BC + ABD + AC + ACD
= BC + ABD + AC
WXY + (WY equiv X) + (Y oplus WZ) = WXY + WYX + (WY) X + Y (WZ) + YWZ = WXY + WXY + (W + Y) X + Y (W + Z) + YWZ
325 (e) NOT VALID Counterexample x = 0 y = 1 z = 0 then LHS = 0 RHS = 1 there4 This equation is not always valid In fact the two sides of the equations are complementsLHS = (x + y) (y + z) (x + z) = [(x + y) + (y + z) + (x + z)] = (xy + yz + xz) = [x (y + z) + yz]=[(x + yz) (y + z + yz)] = [(x + y) (x + z) (y + z)] ne (x + y) (y + z) (x + z)
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
20
AC + BC + AB + ABD + BCD + ACD Consensus terms (1) BC using AC + AB (2) AB using AC + BC (3) AC using AB + BC (4) ABD using BCD + ACDUsing 1 2 3 AC + BC + AB + ABD + BCD + ACD + BC + AB + AC = AC + BC + AB (Using the consensus theorem to remove the added terms since the terms that generated them are still present)
consensus terms abd abd= abc + abc + bcd + bcd + abd + abd adabc + abc + ad + bcd + bcd = RHS
VALID [A + B = C] rArr [D (A + B) = D(C)] [A + B = C] rArr [AD + BD = CD]
327 (a) NOT VALID Counterexample A = 1 B = C = 0 and D = 1 then LHS = 0 0 + 0 0 = 0 RHS = 0 1 = 0 = LHSbut B + C = 0 + 0 = 0 D = 1 ne B + Cthere4 The statement is false
327 (b)
VALID [A + B = C] rArr [(A + B) + D = (C) + D] [A + B = C] rArr [A + B + D = C + D]
327 (c) NOT VALID Counterexample C = 1 A = B = 0 and D = 1 then LHS = 0 + 0 + 1 = 1 RHS = 1 + 1 = 1 = LHSbut A + B = 0 + 0 = 0 ne Dthere4 The statement is false
327 (d)
328 (a) ACD + BCD + ABC + ABC Consensus terms (1) ABC using ACD + BCD (2) ACD using ABC + BCD (3) BCD using ACD + ABC (4) ABD using ACD + ABC (5) ABD using BCD + ABCUsing 1 ACD + BCD + ABC + ABC + AB which is the minimum solution
328 (b)
LHS = ABC + ACD + ABD + ACD = AC (B + D) + AD (B + C) = (A + D (B + C)) (A + C(B + D)) = (A + D) (A + B + C) (A + C) (A + B + D) = (A + D) (A + B + C) (A + C) (A + B + D) (B + C + D)
consensus B + C + D= (A + D) (A + B + C) (A + C) (B + C + D) = (A + D) (A + C) (B + C + D) = RHS
326 (c)
326 (b) LHS = (W + X + Y) (W + X + Y) (W + Y + Z) = (W + X + Y) (W + (X + Y) (Y + Z)) = (W + X + Y) (W + (XY + YZ)) = (W (XY + YZ) + W (X + Y )) = WXY + WYZ + WX + WY
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
21
x y z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
1 These truth table entries were made dont cares because ABC = 110 and ABC = 010 can never occur
2 These truth table entries were made dont cares because when F is 1 the output Z of the OR gate will be 1 regardless of its other input So changing D and E cannot affect Z
3 These truth table entries were made dont cares because when D and E are both 1 the output Z of the OR gate will be 1 regardless of the value of F
4 These truth table entries were made dont cares because when one input of the AND gate is 0 the output will be 0 regardless of the value of its other input
Of the four possible combinations of d1 amp d5 d1 = 1 and d5 = 0 gives the best solutionF = ABC + ABC + ABC + ABC = AB + AB
46 (a)
46 (b) By inspection G = C when both donrsquot cares are set to 0
Unit 4 Problem Solutions
See FLD p 628 for solution
A B C D E y z0 0 0 0 0 (less than 10 gpm) +1 0 0 0 0 (at least 10 gpm) +1 1 0 0 0 (at least 20 gpm) + +1 1 1 0 0 (at least 30 gpm) +1 1 1 1 0 (at least 40 gpm) +1 1 1 1 1 (at least 50 gpm)
42 Y = ABCDE + ABCDE + ABCDE
Z = ABCDE + ABCDE + ABCDE
42 (a)
42 (b)
F1 = sum m(0 4 5 6) F2 = sum m(0 3 4 6 7) F1 + F2 = sum m(0 3 4 5 6 7)General rule F1 + F2 is the sum of all minterms that are present in either F1 or F2
Proof Let F1 = ai mi F2 = bj mj F1 + F2 = ai mi + bj mj = a0m0 + a1m1 + a2m2 +
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
22 23
Exactly one variable not complemented F = ABC + ABC + ABC = sum m(1 2 4)
A B C D F0 0 0 0 0 times 0 = 0 le 2 10 0 0 1 0 times 1 = 0 le 2 10 0 1 0 0 times 2 = 0 le 2 10 0 1 1 0 times 3 = 0 le 2 10 1 0 0 1 times 0 = 0 le 2 10 1 0 1 1 times 1 = 1 le 2 10 1 1 0 1 times 2 = 2 le 2 10 1 1 1 1 times 3 = 3 gt 2 01 0 0 0 2 times 0 = 0 le 2 11 0 0 1 2 times 1 = 2 le 2 11 0 1 0 2 times 2 = 4 gt 2 01 0 1 1 2 times 3 = 6 gt 2 01 1 0 0 3 times 0 = 0 le 2 11 1 0 1 3 times 1 = 3 gt 2 01 1 1 0 3 times 2 = 6 gt 2 01 1 1 1 3 times 3 = 9 gt 2 0
48
F(A B C D) = sum m(0 1 2 3 4 5 6 8 9 12)Refer to FLD for full term expansion
48 (a)
F(A B C D) = Π M(7 10 11 13 14 15)Refer to FLD for full term expansion
48 (b)
F = abc + b (a + a) (c + c) = abc + abc + abc + abc + abc F = sum m(0 1 4 5 6)
49 (a)
Remaining terms are maxterms F = prod M(2 3 7)49 (b)
Maxterms of F are minterms of F F = sum m(2 3 7)
49 (c)
Minterms of F are maxterms of FF = prod M(0 1 4 5 6)
49 (d)
411 (a) difference di = xi oplus yi oplus bi bi+1 = bi xi + xiyi + bi yi
411 (b) di = si bi+1 is the same as ci+1 with xi replaced by xi
See FLD p 629 for solution
410 (a) F = sum m(1 4 5 6 7 10 11)
F = sum m(0 2 3 8 9 12 13 14 15)
410 (b) F = prod M(0 2 3 8 9 12 13 14 15)
F = prod M(1 4 5 6 7 10 11)410 (c) 410 (d)
F(a b c d) = (a + b + d) (a + c) (a + b + c) (a + b + c + d)
= (a + b + c + d) (a + b + c + d) (a + c + bb + dd) (a + b + c + d) (a + b + c + d) (a + b + c + d) = (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
(a + b + c + d) (a + b + c + d) (a + b + c + d)
410
47 (a)
412
Remaining terms are maxterms F = prod M(0 3 5 6 7) = (A + B + C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
The buzzer will sound if the key is in the ignition switch and the car door is open or the seat belts are not fastened B K D Sthere4 The two possible interpretations are B = KD + S and B = K(D + S)
415 (a)
You will gain weight if you eat too much or you do not exercise enough and your metabolism rate is too low W F E Mthere4 The two possible interpretations are W = (F + E) M and W = F + EM
415 (b)
The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful D V M Sthere4 The two possible interpretations are D = VM + S and D = V (M + S)
415 (c)
The roads will be very slippery if it snows or it rains and there is oil on the road V S R Othere4 The two possible interpretations are V = (S + R) O and V = S + RO
415 (d)
Z = AB + AC + BC416 Z = (ABCDE + ABCDE) Y = ABCDE417
1310 = D16 = 0001101 there4 X = ABCDEFG418 (a) 1010 = 0001010 there4 Y = ABCDEFG418 (b)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
F (A B C D) = prod M(0 1 2 6 7 13 15)F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
424 (a) F (A B C D) = sum m(0 3 4 7 8 9 11 12 13 14) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD m0 m3 m4 m7 m8 m9+ ABCD + ABCD + ABCD + ABCD
m11 m12 m13 m14
F (A B C D) = prod M(1 2 5 6 10 15) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) M1 M2 M5 M6(A + B + C + D) (A + B + C + D) M10 M15
424 (b)
F1F2 = prod M(0 3 4 5 6 7) General rule F1F2 is the product of all maxterms that are present in either F1 or F2Proof
Let F1 = (ai + Mi) F2 = (bj + Mj) F1F2 = (ai + Mi) (bj + Mj)
Maxterm Mi is present in F1F2 iff aibi = 0 Maxterm Mi is present in F1 iff ai =0 Maxterm Mi is present in F2 iff aj = 0 Therefore maxterm Mi is present in F1F2 iff it is present in F1 or F2
419
2nndash1
Πi = 0
2nndash1
Πj = 0
2nndash1
Πi = 0
2nndash1
Πj = 0
3nndash1
Πi = 0
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
24 25
427 (a) G1(A B C) = sum m(0 7) = prod M(1 2 3 4 5 6) 427 (b) G2(A B C) = sum m(0 1 6 7) = prod M(2 3 4 5)
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
428 (b) Y = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
Z = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
425 (a) If dont cares are changed to (1 1) respectively F1 = ABC + ABC + ABC + ABC = AB + AC
A B C D E F Z0 0 0 1 1 X2 00 0 1 0 1 X2 10 1 0 0 X2 1 10 1 1 X1 X1 X1 X1 0 0 0 1 X2 11 0 1 0 X2 1 11 1 0 X1 X1 X1 X1 1 1 1 X2 1 0
426 1 These truth table entries were made dont cares because ABC = 110 and ABC = 011 can never occur2 These truth table entries were made dont cares because when one input of the OR gate is 1 the output will be 1 regardless of the value of its other input
425 (b) If dont cares are changed to (1 0) respectivelyF2 = ABC+ ABC + ABC + ABC = C
425 (c) If dont cares are changed to (1 1) respectivelyF3 = (A + B + C) (A + B + C) = A + B
425 (d) If dont cares are changed to (0 1) respectivelyF4 = ABC + ABC + ABC + ABC = BC + BC
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
26
A B C D S T U V W X Y Z0 0 0 0 0 times 5 = 00 0 0 0 0 0 0 0 00 0 0 1 1 times 5 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 5 = 10 0 0 0 1 0 0 0 00 0 1 1 3 times 5 = 15 0 0 0 1 0 1 0 10 1 0 0 4 times 5 = 20 0 0 1 0 0 0 0 00 1 0 1 5 times 5 = 25 0 0 1 0 0 1 0 10 1 1 0 6 times 5 = 30 0 0 1 1 0 0 0 00 1 1 1 7 times 5 = 35 0 0 1 1 0 1 0 11 0 0 0 8 times 5 = 40 0 1 0 0 0 0 0 01 0 0 1 9 times 5 =45 0 1 0 0 0 1 0 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = A U = B V = C W = 0 X = D Y = 0 Z = D
430 A B C D S T U V W X Y Z0 0 0 0 0 times 4 + 1 = 01 0 0 0 0 0 0 0 10 0 0 1 1 times 4 + 1 = 05 0 0 0 0 0 1 0 10 0 1 0 2 times 4 + 1 = 09 0 0 0 0 1 0 0 10 0 1 1 3 times 4 + 1 = 13 0 0 0 1 0 0 1 10 1 0 0 4 times 4 + 1 = 17 0 0 0 1 0 1 1 10 1 0 1 5 times 4 + 1 = 21 0 0 1 0 0 0 0 10 1 1 0 6 times 4 + 1 = 25 0 0 1 0 0 1 0 10 1 1 1 7 times 4 + 1 = 29 0 0 1 0 1 0 0 11 0 0 0 8 times 4 + 1 = 33 0 0 1 1 0 0 1 11 0 0 1 9 times 4 + 1 =37 0 0 1 1 0 1 1 1
Note Rows 1010 through 1111 have dont care outputs
S = 0 T = 0 U = BD + BC + A V = BCD + BCD + A W = BCD + BCD X = BCD + BD Y = BCD + BCD + A Z = 1
431
Notice that the sign bit X3 of the 4-bit number is extended to the leftmost full adder as well
432
X Y Sum Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
433
HA
S3
C2 HA
S2
C1 HA
S1
C0 HA
S0
X0X1X2X31
C4 FA
S4
C3 FA
S3
C2 FA
S1
C0
X1
FA
S0
X0
0
X3
Y1 Y0
FA
S2
C1
X2Y2Y3Y4
XY
Sum
Cout
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
27
Unit 5 Problem Solutions
53 (a) f1
ab c 0 1
00
01
11
10
1
1
1
1
f1 = ac + a bc + b c
53 (b) 53 (c) f3
rs t 0 1
00
01
11
10
1
1
1
1
1
1
f3 = r + t
53 (d) f4
xy z 0 1
00
01
11
10
0
1
1
1
1
0
1
1
f4 = xz + y + x z
54 (a)F
A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
F = (A + B+ D) (B + C + D)
54 (b) 54 (c)
f2d
e f 0 100
01
11
10
1
1
1
1
f2 = de + df + ef f4 = xz + y + xz
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = B D + BC D + A B C + A B CD + BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = D + BC + A B
See FLD p 630 for solution
21 1 112 11 11Z = C X X + C X X + C C X X + C X X + C X X2 22221
C CX X 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
1 21 2
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 11221
21 1 212 11 11Z = C X X + C X X + C C X X + C X X + C C X2 21221
Alt
55 (b)
56 (a)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1 1
1
1
F = ABC + AD + BC D + A B D + B C D
F = ABC + AD + BC D + A B D + AB C
Alt
56 (b) A BC D 00 01 11 10
00
01
11
10
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
F = AC + BD + B D + AB
F = AC + BD + B D + AD
Alt
BDrarrm13 or m15 ACrarrm3 BDrarrm8 or m10
A () indicates a minterm that makes the corresponding prime implicant essential
AD rarrm5 ABCrarrm0 BCDrarrm11ABDrarrm12
() Indicates a minterm that makes the corresponding prime implicant essential
55 (a)
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
28 29
57 (b)F
A BC D 00 01 11 10
00
01
11
10
X
1
1
X
1
X
1
F = AB + ACD + A B C
57 (c)F
A BC D 00 01 11 10
00
01
11
10
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0F = BCD + A BC + AB C + B CD + A D
57 (d)
A BC D 00 01 11 10
00
01
11
10
0
X
0
1
0
1
0
1
0
X
1
1
X
1
1
X
F = D + A C
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = (C+ D) (B+ C) (A + B + C ) (A+ C + D )
58 (a)
58 (b)A B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = (A+ C ) (B+ D) (B + D ) (B+ C)
F = (A+ C ) (B+ D) (B + D ) (C+ D )
Alt
F = BCD + ABC + ABC + BCD + AD
FA B
C D 00 01 11 1000
01
11
10
0
0
1
X
1
1
0
X
0
1
1
0
0
1
X
X
F = AB C + A CD + BC D
FA B
C D 00 01 11 1000
01
11
10
0
1
X
1
1
0
0
X
X
0
0
1
X
0
X
X
F = ABD + B CD + C D
56 (c)F
A BC D 00 01 11 10
00
01
11
10
1
X
X
X
1
0
1
0
1
X
1
1
1
0
0
0
F = AD + B + CD
CDrarrm12 ADrarrm6 Brarrm10 or m11
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
F = ACD + AC D + BCD + A B C D + ABC
F = ACD + AC D + BCD + A B C D + ABD
Alt
57 (a)
() Indicates a minterm that makes the corresponding prime implicant essential
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
28 29
59 (a)F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0F = (A+ B+ C + E ) (A+ B + C+ D) (A + B+ C+ E ) (B+ D + E )
(A + C+ D) (A+ C + D + E) (A+ B+ C+ E)
59 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
X
0
1
1
0
1
1
0
1
0
X
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1F = (A+ B+ E ) (A+ C+ D + E ) (C + D+ E) (A + B + D+ E )
(A + B + C ) (B+ D + E)
F = (A + B + C + E) (A + B + C + D) (A + B + C + E) (B + D + E) (A + C + D) (A + C + D + E) (A + B + C + E)
F = (A + B + E) (A + C + D + E) (C + D + E) (A + B + D + E) (A + B + C) (B + D + E)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
X
X
0
1
1
0
1
1
X
X
0
0
1
1
0
1
X
1
1
0
0
0
0
0
1
0
0
1
0 F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABE
F = ACE + ACD + AD E + A BC D + CD E + A B C D E + BCE + ABD
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
511
(A + B + C + D ) (A+B+ C + D ) (C + D + E)
0
B CD E
A
01
00 01 11 10
00
01
11
10
0
X
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
X
1
F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)
(A + B + C + D ) (A+B+ C + E ) (C + D + E)F = (A+ B + C) (A+ D+ E ) (A + B+ E) (A + C + E)Alt
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = ABC + A B D + A CD
512 (b)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
512 (c)
513 F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
Minterms m0 m1 m2 m3 m4 m10 and m11 can be made donrsquot cares individually without changing the given expression However if m13 or m14 is made a donrsquot care the term BCD or the term ACD (respectively) is not needed in the expression
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
32 33
520 (d)A B
C D 00 01 11 1000
01
11
10
0
X
0
X
1
X
0
0
1
0
1
1
0
0
1
1
F = AB C + A BD + A C
521 (a)F
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
X
X
0
F = (C+ D ) (A+ B + D) (A + B+ C ) (A + D ) F = (B+ C ) (A+ B + C) (A + D ) (C+ D )
A BC D 00 01 11 10
00
01
11
10
0
1
0
1
0
0
X
X
1
1
0
0
X
0
0
1
F = (B+ C ) (A+ B + C) (A + D ) (B+ D )Alt
521 (b)
522 (b)
FA B
C D 00 01 11 1000
01
11
10
0
1
0
1
1
X
1
X
1
1
0
0
0
1
0
0
F = CD + A BC + AB + AD
w xy z 00 01 11 10
00
01
11
10
1
X
0
1
0
1
X
1
1
1
1
X
1
1
X
0
F = (w + x+ z ) (w + y+ z ) (w+ x+ y)
F = (w + x+ z ) (w + y+ z ) (w+ y+ z)
Alt
w xy z 00 01 11 10
00
01
11
10
1
X
0
1
0
1
X
1
1
1
1
X
1
1
X
0
F = xy + w y + wz + w z
F = xy + w y + wz + w x
F = xy + wz + yz + w z
Alt
FA B
C D 00 01 11 1000
01
11
10
0
1
0
1
1
X
1
X
1
1
0
0
0
1
0
0
F = (A+ B+ D ) (A+ C) (A + B + D )
522 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
X
1
1
1
1
1
X
F = BD + AD + CD
523
Notice that abcd = 0101 and 1111 never occur so minterms 5 and 15 are donrsquot cares
524 (a)
F = prod M(0 1 9 12 13 14) = (A + B + C + D) (A + B + C + D) (A + B + C + D ) (A + B + C + D) (A + B + C + D) (A + B + C + D)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = A BD + AB + AC + C D
34 35
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
1
X
1
1
1
X
1
11
1
1
1
1
1
1
1
X
1
F = ABC + AB C + A BCD + CDE + A B D + B C D E + ABE
F = ABC + AB C + A BCD + CDE + A B D + B C D E + ACE
Alt
529 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = A B D + ABC + A CD
524 (b) 524 (c)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
525F
A BC D 00 01 11 10
00
01
11
10
1
1
X
1
X
X
1
1
1
F = D + A B C
Prime implicants for f abce acd abe ace bcde cde ade
Prime implicants for f ade ace ace bde abc bce bcde acde abcd abde
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
34 35
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
1
X
1
1
1
X
1
11
1
1
1
1
1
1
1
X
1
F = ABC + AB C + A BCD + CDE + A B D + B C D E + ABE
F = ABC + AB C + A BCD + CDE + A B D + B C D E + ACE
Alt
529 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
F = A B D + ABC + A CD
524 (b) 524 (c)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
F = (A+ B+ D ) (A + B + C ) (A+ C + D)
525F
A BC D 00 01 11 10
00
01
11
10
1
1
X
1
X
X
1
1
1
F = D + A B C
Prime implicants for f abce acd abe ace bcde cde ade
Prime implicants for f ade ace ace bde abc bce bcde acde abcd abde
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
34 35
F = ABCD + BCDE + BCD + BCDE + ABCD + ABCE + ADE
530
529 (b) B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
1
1
1
1 1
1
1 1
1
1
ABDE + ABC EF = ABCE + AB CD + B C D E + A BDE + A B D E + A C DE +
BC DE + ABC EF = ABCE + AB CD + B C D E + A BDE + A B D E + A C DE +
BC DE + AC D EF = ABCE + AB CD + B C D E + A BDE + A B D E + A C DE +
Alt
1
FB C
D E
A
01
00 01 11 10
00
01
11
10
1
0 0
00
0
0
00
1 1
1
1 1
1
11 1
1
1
1
1
1
0
0
00
0
0
0
0
1 F = ABCD + B CD E + B C D + BC D E + A B CD +ABC E + A DE
532 (a)F
w xy z
v
01
00 01 11 10
00
01
11
10
0
X
X
0
1
0
0
0
0
1
1
0
1
0
0
0
X
X
0
1
0
1
0
1
0
1
1
1
1
1
1
1
F = vx yz + xyz + v z + w xy z + v w x
531F
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
1
X
X
1
X
1
1
1 X
1
11
F = A BC DE + B CD + A B D E + ABCE +ACD E + AC DE
F = ABCDE + BCD + ABDE + ABCE + ACDE + ACDE
Fw x
y z
v
01
00 01 11 10
00
01
11
10
0
X
X
0
1
0
0
0
0
1
1
0
1
0
0
0
X
X
0
1
0
1
0
1
0
1
1
1
1
1
1
1
F = (x + y + z ) (v + y+ z) (v + x+ z) (v + x+ y) (v+ w + z )
532 (b) B CD E
A
01
00 01 11 10
00
01
11
10
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
F = (C + D + E ) (A+ B ) (A + B) (B + C+ D+ E)
F = (C + D + E ) (A+ B ) (A + B) (A + C+ D+ E)
Alt
533 (a)
F = (x + y + z) (v + y + z) (v + x + z) (v + x + y) (v + w + z)
36
535 (b)F
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
1
F = CD + B D + A B
536 (a)
m4
Fw x
y z
v
01
00 01 11 10
00
01
11
10
X
X
1
1
1
1
1
X
X
1
1
1
1
1
1
1
1 1
F = vx y + vw z + x y z + v wxz + v wy z + wyz
F = vx y + vw z + x y z + v wxz + v wx y + wyz
F = vx y + vw z + x y z + v wxy + v wy z + wyz
F = vx y + vw z + x y z + v wxy + v wy z + wx zm31m8
Changing m1 to a dont care removes CD from the solution
vwzrarrm8 xyzrarrm31 vxyrarrm4536 (b)
534 (a) w xy z
v
01
00 01 11 10
00
01
11
10
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
0
1
1 F = (v+ w+ x+ y + z) (w + y+ z) (v + y) (w + x + y )(v+ w+ x + z ) (x + y+ z)
F = (v+ w+ x+ y + z) (w + y+ z) (v + y) (w + x + y )(v+ w+ x + z ) (w+ x + y)
F = (v+ w+ x+ y + z) (w + y+ z) (v + y) (w + x + y )(v+ x + y + z ) (w+ x + y)
Alt
534 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
X
0
0
0
0
0
0
X
0
0
0
0
0 0
0
0
X
XF = (C + D + E ) (A+ C+ D) (A+ B + C + D ) (A + C+ D )
(B + D+ E ) (A + C + E )
F = (C + D + E) (A + C + D) (A + B + C + D) (A + C + D) (B + D + E) (A + C + E)
535 (a) A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
m m or m change the minimumsum of products removing AC BCDor ACD respectively
4 13 14
533 (b) B CD E
A
01
00 01 11 10
00
01
11
10
X
1
X
X
X
1
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
0
1
1F = (C + D) (A + D+ E) (A + B+ C ) (B+ C + E)
(A+ B+ C+ D ) (B + C+ E )
F = (C + D) (A + D+ E) (B+ C + E) (A+ B+ C+ D )(A + C + E ) (B + C+ E )
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
36
535 (b)F
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
1
F = CD + B D + A B
536 (a)
m4
Fw x
y z
v
01
00 01 11 10
00
01
11
10
X
X
1
1
1
1
1
X
X
1
1
1
1
1
1
1
1 1
F = vx y + vw z + x y z + v wxz + v wy z + wyz
F = vx y + vw z + x y z + v wxz + v wx y + wyz
F = vx y + vw z + x y z + v wxy + v wy z + wyz
F = vx y + vw z + x y z + v wxy + v wy z + wx zm31m8
Changing m1 to a dont care removes CD from the solution
vwzrarrm8 xyzrarrm31 vxyrarrm4536 (b)
534 (a) w xy z
v
01
00 01 11 10
00
01
11
10
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
0
1
1 F = (v+ w+ x+ y + z) (w + y+ z) (v + y) (w + x + y )(v+ w+ x + z ) (x + y+ z)
F = (v+ w+ x+ y + z) (w + y+ z) (v + y) (w + x + y )(v+ w+ x + z ) (w+ x + y)
F = (v+ w+ x+ y + z) (w + y+ z) (v + y) (w + x + y )(v+ x + y + z ) (w+ x + y)
Alt
534 (b)F
B CD E
A
01
00 01 11 10
00
01
11
10
X
0
0
0
0
0
0
X
0
0
0
0
0 0
0
0
X
XF = (C + D + E ) (A+ C+ D) (A+ B + C + D ) (A + C+ D )
(B + D+ E ) (A + C + E )
F = (C + D + E) (A + C + D) (A + B + C + D) (A + C + D) (B + D + E) (A + C + E)
535 (a) A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = A C D + B CD + BC + AC
m m or m change the minimumsum of products removing AC BCDor ACD respectively
4 13 14
533 (b) B CD E
A
01
00 01 11 10
00
01
11
10
X
1
X
X
X
1
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
0
1
1F = (C + D) (A + D+ E) (A + B+ C ) (B+ C + E)
(A+ B+ C+ D ) (B + C+ E )
F = (C + D) (A + D+ E) (B+ C + E) (A+ B+ C+ D )(A + C + E ) (B + C+ E )
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
1 5 7 9 11 12 14 151 5 acd times times1 9 bcd times times5 7 abd times times9 11 abd times times12 14 abd times times7 15 bcd times times11 15 acd times times14 15 abc times times
63 (a)
0 1 3 5 6 7 8 10 14 151 3 5 7 ad times times times times6 7 14 15 bc times times times times0 1 abc times times0 8 bcd times times8 10 abd times times10 14 acd times times
f = abd + acd + abd + bcd f = abd + bcd + abd + acd
63 (b)
f = ad + bc + abc + abdf = ad + bc + bcd + abdf = ad + bc + bcd + acd
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
1 3 4 5 6 7 10 12 131 3 5 7 ad times times times times1 5 9 13 cd times times times2 3 6 7 ac times times times4 5 6 7 ab times times times times4 5 12 13 bc times times times times5 7 13 15 bd times times times2 10 bcd times
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
38 39
9 12 13 15P1 (1 5 9 13) cd times timesP2 (4 5 12 13) bc times timesP3 (5 7 13 15) bd times timesP4 (8 9 12 13) ac times times timesP5 (9 11 13 15) ad times times timesP6 (12 13 14 15) ab times times times
65(contd)
F = (AC + BD) or (AD + BC) or (AD + AC) or (AB + AD) or (AB + AC) or (AB + CD) P4 P3 P5 P2 P5 P4 P6 P5 P6 P4 P6 P1
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
0 3 4 5 7 9 11 130 4 acd times times4 5 abc times times3 7 acd times times3 11 bcd times times5 7 abd times times5 13 bcd times times9 11 abd times times9 13 acd times times
68 (a)
2 4 5 6 9 10 11 12 13 152 6 acd times times2 10 bcd times times4 6 abd times times10 11 abc times times4 5 12 13 bc times times times times9 11 13 15 ad times times times times
68 (b)
f = acd + acd + abd + bcdf = acd + acd + abd + bcd
f = bc + ad + acd + bcdf = bc + ad + acd + abcf = bc + ad + abd + bcd
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
40 41
f = bc + bcd + cd + bd + abf = bc + bcd + cd + ad + abf = bc + bcd + cd + ad + ac
2 3 4 7 9 11 12 13 144 12 bcd times times1 3 9 11 bd times times times2 3 10 11 bc times times times3 7 11 15 cd times times times9 11 13 15 ad times times times10 11 14 15 ac times times12 13 14 15 ab times times times
0 1 5 6 8 9 11 135 7 abd times6 7 abc times0 1 8 9 bc times times times times1 5 9 13 cd times times times times8 9 10 11 ab times times times8 9 12 13 ac times times times
69 (c) f = ab + bc + abc + bd + cd f = ab + bc + abc + ad + cdf = ab + bc + abc + ad + ac
610 Prime implicants abc bcd abd bcd ac abd
f = abc + bcd + ac + abd + abd f = abc + bcd + ac + abd + bcd
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
0 2 6 7 8 10 11 12 13 14 16 18 19 29 306 7 ABCD times times18 19 ABCD times times13 29 BCDE times times14 30 BCDE times times21 29 ACDE times0 2 16 18 BCE times times times times8 9 10 11 ABC times times times8 9 12 13 ABD times times times0 2 4 6 8 10 12 14 AE times times times times times times times
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
0 1 2 3 6 8 9 10 11 17 20 21 23 25 28 30 312 6 ABDE times times17 21 ABDE times times20 21 ABCD times times20 28 ACDE times times21 23 ABCE times times28 30 ABCE times times23 31 ACDE times times30 31 ABCD times times1 9 17 25 CDE times times times times0 1 2 3 8 9 10 11 AC times times times times times times times times
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
1 2 3 16 17 18 19 26 32 39 48 6315 ABCDEF39 ABCDEF times63 ABCDEF times16 48 BCDEF times times32 48 ACDEF times times18 26 ABDEF times times26 30 ABCEF times28 29 ABCDE28 30 ABCDF1 3 17 19 ACDF times times times times2 3 18 19 ACDE times times times times16 17 18 19 ABCD times times times times
Essential prime implicants are underlined in 615 (a)
If there were no dont cares prime implicants 15 (26 30) (28 29) and (28 30) are omitted There is only one minimum solution Same as (a) except delete the second equation
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
44 45
617 Prime implicants AC AD AB CD BD AD
Minimum solutions (AD + CD) (AD + BD) (AB + BD) (AB + CD) (AB + AD)
FA B
C D 00 01 11 1000
01
11
10
1
E
X
1
1
X
E
1
1
618 (a)
F = ACD + BCD + AD + E (ABC + BD) MS0 MS1
618 (b)Z
A BC D 00 01 11 10
00
01
11
10
G
X
1
X
X
1
1
1
F
E
E
X
X
Z = CD + ACD + E (BC + BD) + F(CD) + G (AC) MS0 MS1 MS2 MS3
619 (a)
B CD E
A
01
00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
X
X
1
11
1
X
X 1
F = ACD + AB + A BD + ACE + B C D EF = ACD + AB + A BD + ACE + A C D E
616 (b) Essential prime implicants are underlined in 616(a)
616 (c) If there are no donrsquot cares the prime implicants areABDEF ABCDF ABCDEF ACDEF
619 (b) Prime implicants ACD AB ABD ACE ACDE BCDE BCDE
F = ACD + AB + ABD + ACE + ACDEF = ACD + AB + ABD + ACE + BCDE
Each minterm of the four variables A B C D expands to two minterms of the five variables A B C D E For example m4(ABCD) = ABCD = ABCDE + ABCDE = m8(ABCDE) + m9(ABCDE)
620 C DE F 00 01 11 10
00
01
11
10
A
1
A
1
1
A
A
B
1
This square contains 1 + B which reduces to 1
G = CEF + DEF + A (DF) + B (DF) MS0 MS1 MS2
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
46 47
Unit 7 Problem Solutionsf
a bc d 00 01 11 10
00
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = (a+ b) (a + b ) (a + c + d) (b + c+ d)
f = (a+ b) (a + b ) (b + c+ d) (b+ c + d)
f = (a+ b) (a + b ) (a + c + d) (a+ c+ d)
f = (a+ b) (a + b ) (b+ c + d) (a+ c+ d)
fa b
c d 00 01 11 1000
01
11
10
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
f = a bd + a bc + ab c + ab d
f = ab (c + d) + ab (c + d)2 2
2
3 3
71 (a)
Sum of products solution requires 5 gates 16 inputs
Beginning with a minimum product of sums solution we can get
Beginning with the minimum sum of products solution we can get
F = (AD + B) (E + C) + ADE
2 22
22
3
F = (E + FG) [A + B (C + D)]2
22
2
2
2
71 (b)
ACD + ADE + BE + BC + ADE = E (AD + B) + ADE + C (AD + B)
Product of sums solution requires 5 gates 14 inputs so product of sums solution is minimum
5 gates 12 inputs
f = (a + b) (a + b) (d + ac + ac))2 222 3
36 gates 14 inputs
So sum of products solution is minimum
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
46 47
ac
ab
d
F
NOR-NOR
d
ac
ab F
AND-NOR NAND-AND
d
ac
ab F
OR-ANDac
ab
d
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = (A + B ) (D ) (A+ C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
F = A CD + AB D
NAND-NAND OR-NAND
F
abdacd
NOR-ORabdacd
F
abdacd
F
AND-ORabdacd
F
73 F (a b c d)n = abd + acd or d (ab + ac) = d (a + b) (a + c) You can obtain this equation in the product of sums form using a Karnaugh map as shown below
F (A B C D) = sum m(5 10 11 12 13) F = ABC + BCD + ABC = BC (A + D) + ABC
4 gates 10 inputs
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
48 49
75Z
A BC D 00 01 11 10
00
01
11
10
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
Z = (A + C + D ) (A+ D) (A+ C) (A+ B)
Z = (A + C + D) (A + BCD)
23
2
3
BC
ADZA
CD
4 gates 10 inputs
76 BC D
A
CD
Z
Z = ABC + AD + CD = A (BC + D) + CD
C
DF
B A EZ
77 Z = AE + BDE + BCEF= E (A + BD + BCF) = E [A + B (D + CF)]
For the solution to 78 see FLD P 633
79F1
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
F1 = A C D + A D + ABD
F2A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1 11
F2 = AD + ABD + A C D6 gates
78
710
F1A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F1 = A BD + BC D + AB D
F2A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
F2 = A BC + BC D + B CD + A CD
F2 = A BC + BC D + B CD + A BD
F3A B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
F3 = A BC + BC D + AB C
11 gates
f1 (A B C D) = sum m(3 4 6 9 11)f2 (A B C D) = sum m(2 4 8 10 11 12)f3 (A B C D) = sum m(3 6 7 10 11)
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
48 49
712 F1A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
F1 = (A+B+C)(B+D)
F3A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
F3 = (B+C+D)(A+C)(B+C)
9 gates
713 (a) Using F = (F) from Equations (7-23(b)) p 194f1 = [(ABD) (ABD) (ABC) (BC)] f2 = [C (ABD)] f3 = [(BC) (ABC) (ABD)]
ABD
BC
ABDABC
f1
ABD f2
C BC
ABCABD
f3
F2A B
C D 00 01 11 1000
01
11
10
0
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
F2 = (A+B+C)(B+C+D)(A+C)
711F1
A BC D 00 01 11 10
00
01
11
10
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
F1 = (A + C) (A + B) (A+B+C)(A+B+C)
F2A B
C D 00 01 11 1000
01
11
10
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
F2 = (B+C+D)(A+B+C)(A+C)(A+B+C)
F2 = (A+B+D)(A+B+C)(A+C)(A+B+C)
8 gates
713 (b) Using F = (F) from Equations derived in problem 712f1 = [(A + B + C) + (B + D)]f2 = [(A + B + C) + (B + C + D) + (A + C)]f3 = [(B + C + D) + (A + C) + (B + C)]
BD
ABC
f1
AC
ABCBCD
f2
BC
BCDAC f3
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
50 51
714 (a)
acdacdabab
F
cd a
b
cd a
b
F
5 gates 16 inputs
and f = ab + ab + bcd + acd f = ab + ab + acd + bcd
(two other minimun solutions)5 gates 14 inputs minimal
714 (b) Beginning with the sum of products solution we get
f = ab + ab + d (ac + ac)= ab + ab + d (a + c) (a + c) mdash 6 gates 14 inputs
But beginning with the product of sums solution above we get
f = (a + b + cd) (a + b + cd) mdash 5 gates 12 inputs which is minimum
acdacdabab
F
cd a
b
cd a
b
F
fa b
c d 00 01 11 1000
01
11
10
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
f = (a + b + c ) (a + b + d) (a+ b+ d) (a+ b+ c)f = a cd + ac d + ab + a b
715 (a)
cb
ac
F
a
cd
cb
ac
F
a
cd a
d
F
bc
c
From K-mapsF = ac + bcd + acd mdash 4 gates 11 inputsF = (a + b + c) (c + d) (a + c) mdash 4 gates 10
inputs minimal
715 (b) From K-mapsF = cd + ac + bc mdash 4 gates 9 inputsF = (b + c) (a + c + d) mdash 3 gates 7 inputs
minimal
db
ac
F
a
ad
ab
Fac
bd d
b
ac
F
a
ad
ab
Fac
bd
715 (c) From K-mapsF = ad + acd + bcd = ad + acd + abc mdash 4 gates 11 inputsF = (a + c) ( a + d) (a + b + d) mdash 4 gates 10
inputs minimal
715 (d) From K-mapsF = ab + ac + bd mdash 4 gates 9 inputs minimalF = (a + b) (a + c + d) (a + b + c) = (a + b) (a + c + d) (b + c + d) mdash 4 gates
11 inputs
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
50 51
AB
F
A
C
DA
C
B
C
A
C
D
F = ABE (F + G) + AC (D + E)
22
2
4 3
716 (a) In this case multi-level circuits do not improve the solution From K-maps F = ABC + ACD + ABC + ACD mdash 5 gates 16
inputs minimalF = (A + B + C) (A + C + D) (A + C + D)
(A + B + C) mdash 5 gates 16 inputs also minimal
Either answer is correct
AB
F
A
C
DA
C
B
C
A
C
D
G
F
E
EAC
BA
D
716 (b) Too many variables to use a K-map use algebraAdd ACE by consensus then use X + XY = X
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
52 53
718 (b)
NAND-NANDabc
bcd
Fabc
abc
bcd
F
OR-NAND
abc
AND-ORabc
bcd
Fabc
F
NOR-ORabc
bcd
abc
F(a b c d) = sum m(4 5 8 9 13)From KmapF = abc + abc + bcdF = abc + abc + acd
F = c (a + b) (a + b + d)
wxy
wz
wxy
wxy
wz
wxy
NAND-NAND
F F
OR-NANDAND-ORwxy
wz
Fwxy
F
NOR-ORwxy
wz
wxy
x
zy
x
zy
x
zy
x
zy
x
zy
x
zy
x
zy
w
F
AND-NOR
w
F
NOR-NOR
w
F
NAND-AND
x
zw
F
OR-AND
y
F (w x y z) = (x + y + z) (x + y + z) w718 (a)
From Karnaugh map F = wxy + wxy + wz
b
c
aba
dF
AND-NORaba
dc
F
NOR-NOR
b
c
aba
dF
NAND-AND
b
aba
dc
F
OR-AND
b
52 53
719 (a)
y
xy
z
z
f
y
xy
z
z
f
Fx
y z 0 100
01
11
10
1
1
0
1
1
0
0
1
F = (y+ z ) (x+ y + z)
From KmapF = (y + z) (x + y + z)
xy
yz
yz
f
xz
()
orxy
yz
yz
f
xz
()
or
Fx
y z 0 100
01
11
10
1
1
0
1
1
0
0
1
F = y z + yz + xz
F = y z + yz + xy
719 (b)
720 (b)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
F = (B+ C ) (B+ D ) (A+ C ) (A+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
F = AB + C D
Using OR and NOR gates720 (a)
f f
ab
cd
ab
cd
c
d
b
a
f
d
c
a
b
c
d
b
a
f
d
c
a
bUsing NOR gates only
54 55
721 (a) NAND gatesF = D + BC + AB(Refer to problem 54 for K-map)NOR gatesF = (A + B + D) (B + C + D)
721 (b) NAND gatesF = abc + acd + bcd(Refer to problem 58(a) for K-map)NOR gatesF = (b + c) (c + d) (a + b + c) (a + c + d)
721 (c) NAND gatesF = abd + bcd + cd(Refer to problem 58(b) for K-map)NOR gatesF = (b + d) (b + d) (a + c) (b + c)F = (b + d) (b + d) (a + c) (c + d)
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
52 53
719 (a)
y
xy
z
z
f
y
xy
z
z
f
Fx
y z 0 100
01
11
10
1
1
0
1
1
0
0
1
F = (y+ z ) (x+ y + z)
From KmapF = (y + z) (x + y + z)
xy
yz
yz
f
xz
()
orxy
yz
yz
f
xz
()
or
Fx
y z 0 100
01
11
10
1
1
0
1
1
0
0
1
F = y z + yz + xz
F = y z + yz + xy
719 (b)
720 (b)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
F = (B+ C ) (B+ D ) (A+ C ) (A+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
F = AB + C D
Using OR and NOR gates720 (a)
f f
ab
cd
ab
cd
c
d
b
a
f
d
c
a
b
c
d
b
a
f
d
c
a
bUsing NOR gates only
54 55
721 (a) NAND gatesF = D + BC + AB(Refer to problem 54 for K-map)NOR gatesF = (A + B + D) (B + C + D)
721 (b) NAND gatesF = abc + acd + bcd(Refer to problem 58(a) for K-map)NOR gatesF = (b + c) (c + d) (a + b + c) (a + c + d)
721 (c) NAND gatesF = abd + bcd + cd(Refer to problem 58(b) for K-map)NOR gatesF = (b + d) (b + d) (a + c) (b + c)F = (b + d) (b + d) (a + c) (c + d)
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
54 55
721 (a) NAND gatesF = D + BC + AB(Refer to problem 54 for K-map)NOR gatesF = (A + B + D) (B + C + D)
721 (b) NAND gatesF = abc + acd + bcd(Refer to problem 58(a) for K-map)NOR gatesF = (b + c) (c + d) (a + b + c) (a + c + d)
721 (c) NAND gatesF = abd + bcd + cd(Refer to problem 58(b) for K-map)NOR gatesF = (b + d) (b + d) (a + c) (b + c)F = (b + d) (b + d) (a + c) (c + d)
ACD + BCE + ABE(Refer to problem 59(a) for K-map)NOR gatesF = (B + D + E) (A + C + D) (A + B + C + D)
(A + B + C + E ) (A + B + C + E) (A + C + D + E) (A + B + C + E)
721 (e) NAND gatesF=ACD+ABE+CDE+ABCD+BDE+ABDEF=ACD+ABE+CDE+ABCE+ABCD+BDEF=ACD+ABE+CDE+ABDE+ABCE+BDEF=ACD+ABE+CDE+ABDE+ABCE+BCE(Refer to problem 59(b) for K-map)NOR gatesF = (A + C + D + E) (C + D + E) (A + B + E)
(A + B + D + E) (A + B + C) (B + D + E)
721 (f) NAND gatesF = CD + AB + AD + ABC(Refer to problem 522(a) for K-map)NOR gatesF = (A + B + D) (A + B + D) (A + C)
721 (g) NAND gatesf = xy + wy + wz+ wzf = xy + wy + wx + wzf = xy + wy + yz+ wz(Refer to problem 522(b) for K-map)NOR gatesf = (w + x + z) (w + y + z) (w + y + z)f = (w + x + z) (w + y + z) (w + x + y)
ae b
de
d
bcacd
F
722 (a) 722 (b) f = (b + d + ae) (b + c + de) (a + c + d)F
B CD E
A
01
00 01 11 10
00
01
11
10
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
F = (B + C+ D ) (B + C+ E) (B+ D+ E ) (A + C + D ) (A + B+ D)f = (b + c + d) (b + c + e) (b + d + e) (a + c + d) (a + b + d)
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
54 55
bd
cd
a
ab
f
723F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
F = (A+ D ) (A+ B + C ) (A + B) f = (a + d) (a + b + c) (a + b) = (a + b) [a + d (b + c)] = (a + b) (a + bd + cd)
724 (a)
ghcda
b
ef
zghcde
f
ab
z
Z= (a + b +e + f)(c + a + b)(d + a + b)(g+h) = [a + b + cd (e + f)] (g + h)
Z = abef + cef + def + gh= ef (ab + c + d) + gh
724 (b)
727 (a) FA B
C D 00 01 11 1000
01
11
10
1
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
F = (B + C + D) (B+ D ) (A+ D ) (A+ B+ C)
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1 1
1
F = B CD + BC D + ABD + AB D
F = B CD + BC D + ABD + AC D
F
aed
b
c
bc
a
725 F = abde + ab + c= (a + b) (a + bde) + c= (a + b + c) (a + c + bde)
726
yx
fzw
z
xvy
f = xyz + xvyw + xvyz = xyz + xvy (z + w)
Draw AND-OR circuit and replace all gates with NANDs
Alternate F = (a + b + c) (b + c + ade)
727 (b)
Draw OR-AND circuit and replace all gates with NORs
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
56 57
A
C
B
D
BF
D
C
D
D
A
F = B (AD + CD) + B (AD + CD)727 (c)
FA B
C D 00 01 11 1000
01
11
10
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
F = (A + C + D) (B + C+ D ) (A + B+ C ) (A + B+ D) (A+ B + D )(A+ B +C) (B+ C + D) (A+ C+ D )
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
F = A B C D + A B CD + A BCD + AB C D + ABC D + ABCD
728 (a)
F = (A + C + D) (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C) (B + C + D) (A + C + D)
F = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
728 (b)
D
D
D
D
C
B
B
B
B
C
C
CF
A
A
728 (c) Many solutions exist Here is one drawn with alternate gate symbolsF = A (BCD + BCD + BCD) + A (BCD + BCD + BCD)
= A (B(CD + CD) + BCD) + A (B(CD + CD) + BCD)
Alternative F = A (BD + BD) + D (BC + BC)
= D (AB + BC) + B (AD + CD)= A (BD + CD) + D (BC + BC)=D (AC + BC) + B (AD + CD)
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
56 57
729 (a)
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
FA B
C D 00 01 11 1000
01
11
10
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
F = ABC + BD + AC + BCD = B (D + AC) + C (A + BD)
Many NOR solutions exist Here is one F = (B + C) (A + C + D) (A + B + D) (A + B + C + D)
= (B + C) [A + (B + D) (B + C + D)] (A + C + D)= (B + C) [A (C + D) + A (B + D) (B + C + D)]= (B + C) [A (C + D) + A (B(C + D) + BD)]
CD
BD
CD
AA
BCB
F
A BC D 00 01 11 10
00
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = (A + C ) (B + D ) (A+ B + C) (B+ C + D)
F = (B + C + D) (A + B + C) (B + D) (A + C) = (C + A (B + D)) (B + D (A + C))
730F
A BC D 00 01 11 10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
1
1
F = AB + AC + D + A B C
F = sum m(0 1 2 3 4 5 7 9 11 13 14 15)F = D + AB + AC + ABC
= D + A (B + C) + ABC
Alternate solutionF = D + (A + BC) (A + B + C)
729 (b)
F = C (B + AD) + A (BCD + BD)= C (B + AD) + A[(B + D) (B + CD)]
BD
B
F
AC
A
D
C
AD
DC
B
B
BD
A
C
F
FA B
C D 00 01 11 1000
01
11
10
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
F = AC D + B C + A BCD + A B D
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
58 59
AB
BC
CA
DF
AB
BC
CA D
F
AB
CA D F
BC
730 (a) 730 (b)
AB
BC
CA D
F
AB
BC
C
A DF
730 (c)
731
BD
F
GH
F E
C A
BD
F
GH
F E
C A
Z = A [BC + D + E(F + GH)]
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
58 59
732f1
a bc d 00 01 11 10
00
01
11
10
X X
1
1
1
X
1
f 1 = b cd + a c
f2a b
c d 00 01 11 1000
01
11
10
1
X
1 1
1
X
X
f 2 = bc + b cd
f3a b
c d 00 01 11 1000
01
11
10
1
X X
1
X
1
1
1
f 3 = a b + a d + b cd
8 gates
734f1
xy z 0 1
00
01
11
10 1
1
1
1
f1 = xy z + x y z + x y
f2x
y z 0 100
01
11
10
1
1
1
1
f 2 = y z + xy z + x y z
f3x
y z 0 100
01
11
10
1
1
1
1
1
f 3 = x y + yz + xy z + x y z
8 gates
735 (a) a bc d 00 01 11 10
00
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
733F
A BC D 00 01 11 10
00
01
11
10 1
1
1
1
1
1
1
F = AC + AB D + A BD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
F = AB + AB D + A BD
6 gates
f1 = (a + b + d) (b + c + d) (b + d) mdash 6 gatesf2 = (a + b + d) (b + c + d) (b + d)
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
60 61
735 (b)a b
c d 00 01 11 1000
01
11
10
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
f2
Circle 1s to get sum-of-products expressions f1 = bcd + abd + bd mdash 6 gatesf2 = bcd + abd + bdThen convert directly to NAND gates
736 (a)f1a b
c d 00 01 11 1000
01
11
10
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
f1 = (a + c + d) (b+ c) (c+ d)
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = (a + c + d) (a + c) (a + b + d)
Circle 0rsquos
7 gates
f1a b
c d 00 01 11 1000
01
11
10
0
1
1
0
0 0 0 0
1
1
1
1
1
1
00
f1 = a c + cd + bc d
f2a b
c d 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
f2 = ad + c d + bc d
Circle 1s to get sum-of-products expressions
7 gates
Then convert directly to NAND gates736 (b)
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
60 61
bcbcdabc
bd
d
f1
f2
b
c
b
c
d
a
bc
d
d
df1
f2
c
f1a b
c d 00 01 11 1000
01
11
10
1
1
1 1
1
1
1
f1 = b c + bc d + a b cd
f2a b
c d 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
f2 = b d + bc d + a b cd
f1a b
c d 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f1 = (b + d) (c + d) (b + c) (a + c + d)
f2A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
0
f2 = (b + d) (b + c) (a + c + d) (b+c+d)
737 (a)
738 (a)f1
a bc d 00 01 11 10
00
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = ad + ab c d+ a c d
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = ac + ab c d+ a c d
f1a b
c d 00 01 11 1000
01
11
10
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
f 1 = (a+ c ) (a+ d) (c + d) (b + c+ d)
f2a b
c d 00 01 11 1000
01
11
10
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
f 2 = (a+ c ) (a+ d) (b + c+ d) (a + c + d )
738 (b)
737 (b)
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
62
739 (a)
ab
c d
h
f
g
F1
e
F2
ab
ef g
h
c
ec
f
d
h
F1
F2
The circuit consisting of levels 2 3 and 4 has OR gate outputs Convert this circuit to NAND gates in the usual way leaving the AND gates at level 1 unchanged The result is
739 (b) One solution would be to replace the two AND gates in (a) with NAND gates and then add inverters at the output However the following solution avoids adding inverters at the outputs
F1 = [(a + b) c + d] (e + f)= ace + bce + de + acf + bcf + df= ce (a + b) + d (e + f) + cf (a + b)
F2 = [(a + b) c + g] (e + f) h= h (ace + bce + acf + bcf) + gh (e + f)= h [ce (a + b) + cf (a + b)] + gh (e + f)
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
63 64
Unit 8 Problem Solutions
81
82 (a)(contd)
Static 1-hazards are 1101harr1111 and 0100harr0101
82 (a)
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
WF
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
1
1
F = ACD + A C + B CDF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
0
F = (A + C) (A+ C + D ) (B + C + D)
Static 0-hazards are 0001harr0011 and 1000harr1001
82 (b)A B
C D 00 01 11 1000
01
11
10
1 1
1
1
1
1
1
1
Ft = ACD + A C + B CD + ABC + ABD82 (c) A B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
0
0
Ft = (A + C) (A+ C + D ) (B + C + D)(A + B + C)(A + B + D)
Ft = (A + C) (A + C + D) (B + C + D) (A + B + C) (A + B + D)
83 (a)
3
F
G1 2 4 5 6 7 t (ns)
E
C
Glitch(static 1 hazard)
A BC D 00 01 11 10
00
01
11
10
1 1
1
1
1
1
G = ACD + B C + ABD
Modified circuit (to avoid hazards)83 (b)
A = 1 B = Z C = 1 Z = X D = 1 + Z = 1 E = X = X F = 1 = 0 G = X 0 = 0 H = X + 0 = X
See FLD Table 8-1 P 214
84
A = B = 0 C = D = 1So F = ABD + BCD + BCD = 0
But in the figure gate 4 outputs F = 1 indicating something is wrong For the last NAND gate F = 0 only when all its inputs are 1 But the output of gate 3 is 0 Therefore gate 4 is working properly but gate 3 is connected incorrectly or is malfunctioning
85
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
63 64
86
15
V
Z0 5 10 20 25 30 35 40 t (ns)
Y
X
W87 A B
C D 00 01 11 1000
01
11
10 1
1 1
1
1
1
Z = AC D + A CD + BC D
Static 1-hazards lie between 1000harr1010 and 0010harr0011Without hazards Z
t = ACD + ACD + BCD + ABC + ABD
A = Z B = 0 C = Z = X D = Z 0 = 0 E = Z F = 0 + 0 + X = X G = (0 Z) = 0 = 1 H = (X + 1) = 1 = 0
88
A = B = C = 1 so F = (A + B + C) (A + B + C) (A + B + C) = 1But in the figure gate 4 outputs F = 0 indicating something is wrong For the last NOR gate F = 1 only when all its inputs are 0 But the output of gate 1 is 1 Therefore gate 4 is working properly but gate 1 is connected incorrectly or is malfunctioning
89
810 (a)
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + AC D + BCD
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AB C
FA B
C D 00 01 11 1000
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C + ABD + AC D
F (A B C D) = sum m(0 2 5 6 7 8 9 12 13 15)There are 3 different minimum AND-OR solutions to this problem The problem asks for any two of these
Solution 1 1-hazards are between 0000harr0010 and 0111harr0110
Solution 2 1-hazards are between 0010harr0110 and 0000harr1000
Solution 3 1-hazards are between 0111harr0110 and 0000harr1000Without hazards F
t = BD + AC + BCD + ACD + ABD + ABCF
A BC D 00 01 11 10
00
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (A+ B + C)
FA B
C D 00 01 11 1000
01
11
10
0
0
0
0
0
0
F = (A + B + D) (A + B+ C + D ) (A+ C+ D ) (B + C+ D)
F = (A + B + D) (A + B + C + D) (A + C + D) (A + B + C)
0-hazard is between 1011harr0011
Either way without hazard Ft = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D) (A + B + C)
810 (b)
F = (A + B + D) (A + B + C + D) (A + C + D) (B + C + D)
0-hazard is between 1011harr1010
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
65
Unit 9 Problem Solutions
91 See FLD p 636 for solution 92 See FLD p 636 for solution
93 See FLD p 637 for solution 94 See FLD p 637 and Figure 4-4 on FLD p99
95 y0 y1 y2 y3 a b c 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 1 0 0 0 1 1 X X 1 0 1 0 1 X X X 1 1 1 1
ay y
y y 00 01 11 1000
01
11
10
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0 12 3
a = y + y23 3
b
00 01 11 1000
01
11
10
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
b = y + y y
y yy y
0 12 3
12 3 0
c
00 01 11 1000
01
11
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c = y + y + y + y2 1
y yy y
0 12 3
96 See FLD p 638 for solution 97 See FLD p 638 for solution
98 See FLD p 638-639 for solution 99 The equations derived from Table 4-6 on FLD p 101 are D = xybin + xybin + xybin + xybinbout = xbin + xy + ybinSee FLD p 639 for PAL diagram
910 Note A6 = A4 and A5 = A4 Equations for A4 through A0 can be found using Karnaugh maps See FLD p 640-641 for answers
911 (a) F = CD + BC + AC rarr Use 3 AND gatesF = [CD + BC + AC] = [C (B +D) + CA]
= [(C + B + D) (A + C)] = BCD + AC rarr Use 2 AND gates
911 (b) F = AB + CD rarr Use 2 AND gatesF = (AB + CD)
= [(A +C) (A + D) (B + C) (B + D)] = AC + AD +BC +BD rarr Use 4 AND gates
912 (a) See FLD p 641 use the answer for 912 (b) but leave off all connections to 1 and 1
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
66 67
BinBin
X Y
Diff0
Bin
Bin
1
X Y
Bout
916 (b) 916 (c) XXXX
Y
DiffX
0
1
X
Y
Bout
Bin Bin
917 For a positive number A |A| = A and for a negative number A |A| = minusA Therefore if the number is negative that is A[3] is 1 then the output should be the 2s complement (that is invert and add 1) of the input A
A3A30
A2A20
A1A10
A0A0
0
A3
A3
A3
A3
1
output
FA
FA
FA
FA
918I0
I1
I2
I3
m0m1m2m3
ZA
B2-to-4decoder
I0I1I2I3
A B
Z
919 I0I1I2I3
B C AI4I5I6I7
B C
Z
920 (a)
3-to-8Decoder
D
Bout
x
y
Bin
D = sum m(1 2 4 7) Bout = sum m(1 2 3 7)
920 (b)
D = prod M(0 3 5 6) Bout = prod M(0 4 5 6)
3-to-8Decoder
D
Bout
x
y
Bin
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
68 69
921
4-to-2priorityencoder
y0y1y2y3
4-to-2priorityencoder
y4y5y6y7
a
b
c
d
a1b1c1
a2
c2
b2
922
3
0
abcd
efgh
1
2
SS
SS
C
2 x 5
out
N1
N2
ROM
8
a b c d e f g h S3 S2 S1 S0 Cout Meaning 0 0 0 0 0 0 0 0 X X X X X (0000 is a not valid input) 0 0 1 1 0 0 1 1 0 0 1 1 0 (0 + 0 = 0) 0 1 0 1 0 1 1 0 1 0 0 0 0 (2 + 3 = 5) 1 0 1 0 0 1 1 1 0 1 0 0 1 (7 + 4 = 11)
923 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 1 0 0 00 1 1 1 1 0 0 11 0 0 0 1 0 1 01 0 0 1 1 1 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
R
S
T
U
V
W
Z
Y
2 x 4
ROM
4
923 (b) VR S
T U 00 01 11 1000
01
11
10 1
1
1
1
X
X
X
X
X
X
V = S T + RW
R ST U 00 01 11 10
00
01
11
10
0
0
0
1
1
1
0
0
0
1
X
X
X
X
X
X
W = ST U + S T U + R U + S T U
If any of the inputs y0 through y7 is 1 then d of the 8-to-3 decoder should be 1 But in that case c1 or c2 of one of the 4-to-2 decoders will be 1 So d = c1 + c2
If one of the inputs y4 y5 y6 and y7 is 1 then a should be 1 and b and c should correspond to a2 and b2 respectively Otherwise a should be 0 and b and c should corresond to a1 and b1 respectively So a = c2 b = c2a2 + c2a1 and c = c2b2 + c2b1
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
924 (a) R S T U V W Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 1 0 00 0 1 1 0 0 1 00 1 0 0 X X X X0 1 0 1 X X X X0 1 1 0 0 1 0 10 1 1 1 X X X X1 0 0 0 1 1 0 01 0 0 1 1 0 1 01 0 1 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 0 1 1 01 1 1 1 X X X X
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
74 75
Note Unused inputs outputs and wires have been omitted from this diagram
y2
y7
y6
y5
y4
y3
xx x
x
x
xx
xx
xx
x
x
x
x
y1
y0
a
xx
b
c
x x xx x x x
x
x x x x xx x x xx x x
x
d
929 (contd)
930 F = CDE + CDE + ADE + ABDE + BCD
F = AB(CDE + CDE + DE + DE) + AB (CDE + CDE + DE + CD) + AB (CDE + CDE) + AB (CDE + CDE + CD)
F = BC (ADE + ADE) + BC (DE +DE + ADE + ADE) + BC (ADE) + BC (DE + DE + ADE + D)
F = AC (DE + BDE) + AC (DE + DE + DE + BDE + BD) + AC(0) + AC(DE + DE + BD)
Use the expansion about A and CF = AC(F0 ) + AC(F1 ) + AC(F3 )where F0 F1 F3 are implemented in lookup tables
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
74 75
931 F = BDE + ABC + CDE + ABCD
F = AB (DE + CDE) + AB (CDE + CD) + AB (DE + C + CD) + AB (CDE)
F = BC (DE + DE) + BC (DE + A) + BC (DE + AD) + BC (0)
F = AC (BDE + DE + BD) + AC (BDE) + AC (BDE + DE) + AC (BDE + B)
In this case use the expansion about B and C to implement the function in 3 LUTsF = BC(F0 ) + BC(F1 ) + BC(F2 ) + BC(0)Here we use the LUTs to implement F0 F1 F2 which are functions of A D E
= A (BI0 + BI1 ) + A(BI2 + BI3 ) = AG + AF where G = BI0 + BI1 F = BI2 + BI3
Set programmable MUX so that Y is the output of MUX H
Unit 10 Problem Solutions
101 See FLD p 642 for solution 102 See FLD p 642 for solution
103 See FLD p 643 for solution 104 See FLD p 643 for solution
105 See FLD p 643 for solution Notes The function vec2int is found in bit_pack which is in the library bitlib so the following declarations are needed to use vec2int
library bitlibuse bitlibbit_packall
If std_logic is used instead of bits then the index can be computed as
index lt= conv_integer(AampBampCin) where A B and Cin are std_logic
conv_integer is found in the std_logic_arith package
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
76 77
106 See FLD p 643 for solution 107 See FLD p 644 for solutionNotes In line 8 00ampa converts a to a 18-bit std_logic_vector The overloaded ldquo+rdquo operators automatically extend b c and d to 18 bits so that the sum is 18 bits In line 9 sum(17 downto 2) drops the lower 2 bits of sum which effectively divides by 4 to give the average Adding sum(1) rounds up the value of f if sum(1) = 1
108 See FLD p 644 for solution
Add the following to the answer given on FLD p 644Addout lt= 0 amp E + BusSum lt= Addout(3 downto 0)Cout lt= Addout(4)
109 See FLD p 644 for solution
1010 The network represented by the given code is
PQ R
LN
M
(1) Statement (a) will execute as soon as either P or Q change Hence it will execute at 4 ns
(2) Since the NAND gate has a delay of 10 ns L will be updated at 14 ns
(3) Statement (c) will execute when the value M changes It will execute at 19 ns
(4) R will be updated at 19 + Δ ns since Δ is the default delay time when no delay is explicitly specified
H lt= not A nand B nor not D nand E
(Note not happens first then it proceeds from left to right)
1011 (a) 1011(b) AN lt= not A after 5 nsC lt= AN nand B after 10nsF lt= not D after 5nsG lt= C nor F after 15nsH lt= G nand E after 10ns
1012
1014 (a) The expression can be rewritten asF lt= (((not E) amp 011) or 000100) and (not D)
Evaluating in this order we getF = 000110
FP
U
T
V
RS
Q
P
S
QR
L = X (Since 1 and 0 in the resolution function yields X)
M = 0N = 1 (1 overrides Z in the resolution function)
1013
LHS not(101 amp 011) = 010100RHS (100 amp 101 and 010 amp 101) = 000101Since LHS gt RHS the expression evaluates to FALSE
1014 (b)
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
end eqn
76 77
library bitlibuse bitlibbit_packall
entity myrom isport (A B C D in bit W X Y out bit)
end myrom
architecture table of myrom istype ROM16_3 is array(0 to 15)of bit_vector(0 to 2)constant ROM1 ROM16_3 = (010 111 100 110 011 110
001 000 000 111 100 010 001 100 101 000)signal index integer range 0 to 15signal temp bit_vector(0 to 2)begin
1016 (a) 1016 (b) The value will be determined by the std_logic resolution function For example if membus = 01010101 and probus = 00001111 then databus = 0X0XX1X1
1017 (a) with CampD selectF lt= not A after 15ns when 00B after 15ns when 01not B after 15ns when 100 after 15ns when 11
1017 (b)F lt= not A after 15ns when CampD = 00else B after 15ns when CampD = 01else not B after 15ns when CampD = 10else 0 after 15ns
entity mynand isport(X Y in bit Z out bit)
end mynand
architecture eqn of mynand isbegin
Z lt= X nand Y after 4 nsend eqn
1018 (a) 1018 (b) entity main isport(A B C D in bit F out bit)
end main
architecture eqn of main iscomponent mynand is
port(X Y in bit Z out bit)end component
signal E G bitbegin
n1 mynand port map(A B E)n2 mynand port map(C D G)n3 mynand port map(E G F)
