Kaustav Banerjee, Member, IEEE, and Robert W. Dutton, Fellow, IEEE
Abstract—Electrostatic discharge (ESD) failure threshold ofNMOS transistors is known to degrade with the use of silicideddiffusions owing to insufficient ballast resistance, making themsusceptible to current localization, which leads to early ESDfailure. In general, the gate-to-contact spacing of salicided devicesis known to have little impact on their ESD strength. However,experimental results presented in this paper show that the ESDstrength depends on the gate-to-contact spacing independent ofthe silicided process. Subsequently, a detailed investigation of theinfluence of gate-to-source and gate-to-drain contact spacings iscarried out for a salicided 0.13- m technology which providesnew insight into the behavior of deep submicron ESD protectiondevices. It is shown that the reduction in current localizationand increase in the power dissipating volume with increasein the gate-to-contact spacings are the primary causes of thisimprovement, which implies that even for silicided processes, thegate-to-contact spacing should be carefully engineered for efficientand robust ESD protection designs.
NMOS transistors are widely used as protection devicesagainst electrostatic discharge (ESD), which is a major re-
liability concern for all categories of integrated circuits [1]. Itis well known that for nonsilicided or silicide-blocked NMOSprotection transistors, the second breakdown triggering current( ), which is widely used to monitor the ESD strength, canbe increased with larger drain contact spacing because of moreuniform triggering of the lateral n-p-n structure obtained withballast resistance1 effects [1]. In addition, it is also well es-tablished that effectiveness against ESD is reduced in the case
Manuscript received February 25, 2002; revised July 8, 2002. This work wassupported by Texas Instruments, Inc., Dallas, TX. The review of this paper wasarranged by Editor C.-Y. Lu.
K.-H. Oh and R. W. Dutton are with the Center for Integrated Systems,Stanford University, Stanford, CA 94305 USA (e-mail: [email protected]; [email protected]).
C. Duvvury is with Silicon Technology Development, Texas Instruments,Dallas, TX 75243 USA (e-mail: [email protected]).
K. Banerjee is with the Department of Electrical and Computer Engi-neering, University of California, Santa Barbara, CA 93106 USA (e-mail:[email protected]).
Digital Object Identifier 10.1109/TED.2002.803627
1Ballast resistance effect makes the ESD currents flow more uniformly in thedrain diffusion region.
of devices with silicided diffusions [1], since the ballast resis-tance is negligible. In silicided CMOS processes, the primarycause of the degradation of ESD failure threshold is known to benonuniform lateral bipolar conduction, which is attributed to in-sufficient ballasting resistance in the fully silicided source/drainstructures [2]. This decrease in ESD strength imposes severerestrictions on the efficient design of ESD protection. There-fore, to avoid localized current conduction and improve,device structures with sufficient ballasting resistance are real-ized by introducing the silicide blocking option, or by imple-menting well resistors on the drain side, or by inserting localinterconnect layers [3]–[5]. However, these options either re-quire an extra mask or more process complexity and result inincreased process cost and chip area. Hence, use of salicided2
devices is often preferred for cost effectiveness in providing ad-vanced ESD protections. The of the silicided devices is gen-erally believed to be independent of the gate-to-contact spacingparameter. Hence, the impact of the gate-to-contact spacing of asalicided NMOS transistor on the ESD failure strength has notbeen fully explored.
However, contrary to conventional understanding, for ad-vanced deep submicron salicided technologies with shallowtrench isolation (STI) structures, we have recently reportedthat the gate-to-drain contact spacing has an impact on[6]. Moreover, the gate-to-source contact spacing has alsobeen observed to affect [6]. This work investigates theabove new phenomenon in advanced salicided transistors anddescribes the different mechanisms that are observed at thesource and drain sides, respectively. The physical mechanismcausing unexpected improvement in silicided devices withincreased gate-to-contact spacing is identified. Furthermore,it is shown that the ESD strength of the protection devicebecomes independent of the gate-to-contact spacing whenadequate substrate bias is applied. These observations havesignificant implications for ESD performance improvementsimply through optimization of the device layout, even withoutintroducing expensive process options.
II. EXPERIMENTS
A. Dependence on Contact Spacing
In this work, the dependence of second breakdown trig-gering current [mA/ m] is investigated as a function ofthe gate-to-source/drain salicided (CoSi) contact spacing
2184 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
Fig. 1. Schematic of a silicided NMOS transistor indicating the gateto source/drain contact spacing (GSCS/GDCS) and the noverlap ofthe source/drain contact (S_ =D_ ). For the 1.5-V NMOS, S/Dcontact opening (S=D) = 0:15�m and S_ = D_ = 0:1�m.For the 3.3-V NMOS, the S/D contact opening (S=D) = 0:15�m andS_ = D_ = 0:125�m. In the test structures, the S/D contact openingand n overlap of S/D contact (S_ =D_ ) remain unchanged despite thevariations of GSCS/GDCS.
(GSCS/GDCS) for various test structures with grounded gates.Test structures were fabricated using a 0.13-m mixed-voltageCMOS technology. Two types of transistors are investigatedin this study: low (1.5 V) and high (3.3 V) voltage NMOStransistors with different gate oxide thickness and drawnchannel lengths. The 1.5-V NMOS transistor has a 27-Å-thickgate oxide and 0.175-m-long gate poly, while the 3.3-VNMOS transistor has a 70-Å-gate oxide and 0.5-m-long gatepoly. However, the finger width for both transistors is 20m.Fig. 1 shows the schematic cross section of the ESD NMOStransistor used in this study. The contact spacing is measuredfrom the gate poly edge to the near edge of contact openingand the contact opening width is fixed at 0.15m for all thetest structures. Since the test structure uses a shallow trenchisolation (STI) with constant n overlap with the source anddrain contact ( _ _ ) for a given device rating, the totalsize of the source and drain structures are changed proportionalto the variation of the GSCS and GDCS. The second breakdowntriggering current ( ) was measured using the transmissionline pulsing (TLP) method for a voltage pulse width of 200ns. As expected, since the resistance of silicided region isrelatively small compared to other parasitic resistances in thesource/drain structure, a change in resistance proportional tothe GDCS/GSCS is not apparent from the dc current–voltage( – ) measurements. The drive current ( ) of the 1.5-VNMOS transistor was tested with GDCS/GSCS variations. Asshown in Fig. 2, the measured drive currents show that thedifference in the resistance due to increased gate-to-contactspacing with the salicided diffusion is hardly apparent. Inaddition, the inset in Fig. 2 shows a sample of TLP curves forthe 1.5-V transistor with two different GDCS and GSCS. Itcan be clearly seen that the value is about doubled with anincrease in GDCS/GSCS from 0.1m to 0.5 m. However, theslope of the high current regions is almost identical for the two
Fig. 2. Measured drive currents (I ) for the 1.5-V NMOS transistors withdifferent gate-to-contact spacings show no apparent differences, whereV =
V = 1:5 V. The inset shows high-current TLP curves for the 1.5-V NMOStransistor, which clearly show the impact of the gate-to-contact spacings onItdespite the silicided diffusion.
Fig. 3. Second breakdown triggering current (It ) with thegate-to-source/drain contact spacing for two different silicided NMOStransistors. The two dotted circles indicateIt for each device withminimum contact spacing: 0.1�m and 0.225�m for the 1.5-V NMOS(W=L = 20=0:175�m) and 3.3-V NMOS (W=L = 20=0:5�m),respectively.
different test structures, which implies that the on-resistanceof the test structures is nearly the same despite the differentgate-to-contact spacings.
For the TLP measurements of the 1.5-V and 3.3-V transistorsas shown in Fig. 3, of both the devices surprisingly improveswith the GSCS/GDCS. Compared with values of the tran-sistor with the minimum gate-to-contact spacing (0.1m for1.5-V NMOS and 0.225 m for 3.3-V NMOS), the improve-ment of is approximately 100% and 40% for the low-voltageand high-voltage transistors, respectively. This implies that the
OH et al.: IMPACT OF GATE-TO-CONTACT SPACING ON ESD PERFORMANCE 2185
Fig. 4. It values for the 1.5-V NMOS transistors with various GDCS andGSCS.It depends on both GDCS and GSCS within the scatter of data.W =
20�m.
gate-to-contact spacing is an important design parameter deter-mining ESD strength for the gate grounded ESD protection de-vices. It also suggests the possibility of achieving increased ESDrobustness through optimizing the layout of the silicided pro-tection devices without any extra processing steps or structureoptions. However, the primary cause of this improvement ofhas not been explored and needs comprehensive modeling andanalysis in order to improve understanding of the device physicsinvolved in this effect. This will also enable the establishmentof robust ESD protection design approaches through proper de-sign of the devices.
As shown in Fig. 3, for the 1.5-V NMOS transistors, thedependence on the gate-to-contact spacing is more apparent
than that for the 3.3-V devices. In general, for advanced de-vices with salicided diffusion, the improvement of is noteasily achieved due to early failure caused by current localiza-tion. In this regard, any amount of improvement in for sali-cided technology with no process changes has significant im-plications. As can be seen in Fig. 4, values are influencedby both GDCS and GSCS within the scatter of data. Despitethe salicided process, the increasing trend ofis obvious asGDCS and GSCS increase. For the minimum gate-to-contactspacing of 0.1 m, ranges from 1 to 1.5 mA/m. However,with the increased GDCS m and GSCS m,values are clustered around 3.5 mA/m. The data clearly showthat for a given spacing (GDCS), increase in GSCS strongly af-fects the ESD hardness. This experimental result implies that theimpact of gate-to-source contact spacing is as significant as thatof the gate-to-drain contact spacing for a salicided technology.
B. Effect of Substrate Bias
For silicided devices, it has been reported that improveswith a forward substrate bias by enlarging the turn-on fingerwidth of the devices [2]. With sufficient external substrate bias( V), the dependence on the gate-to-contactspacing disappears as the emitter–base junction of the lateralbipolar transistor fully turns on (Fig. 5). As shown in [2], thephenomenon of improvement is associated with the extent
(a)
(b)
(c)
Fig. 5. (a)It of the 1.5-V NMOS transistors is dependent on GSCS andGDCS with an external substrate bias of 0.7 V, and is nearly independent ofGSCS and GDCS with sufficient external substrate bias of (b) 1 V and (c) 1.25V.
of uniformity of the lateral current distribution, since the ESDcurrent becomes more uniform along the channel width withincreased external substrate bias. In addition, it should be notedthat the dependence on the gate-to-contact spacing for the1.5-V transistor is stronger, since the extent of uniformity ofthe lateral current distribution of the two devices varies (Fig. 6).It is believed that the devices with shorter channel length andshallower junction depth experience nonuniform bipolar con-duction more strongly since the relative sensitivity to the sta-tistical random variation is higher for given process conditions.In order to identify the underlying physical mechanisms for the
2186 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
(a)
(b)
Fig. 6. Total failure threshold current (IT ) with the finger width for (a)1.5-V NMOS transistors and (b) 3.3-V NMOS transistors where GDCS/GSCS= 0:1�m. The total failure current can be scaled with finger width withinonly a limited finger width (W � 20�m) and the inset shows that the 3.3-Vdevice (W = 20�m and GSCS= 0:225�m) with nearly uniform currentconduction shows negligible dependence ofIt on GDCS.
drain side and source side contact spacing effects respectively,the following effects were investigated: 1) the influence of theballasting ESD current distribution; 2) the improvement of thecurrent driving capability of the lateral n-p-n transistor; and 3)the increase in thermal capacity due to the enlargement of powerdissipating volume along with the increase in GSCS/GDCS.Each of these effects has been investigated in detail in the nextsection.
III. A NALYSIS AND DISCUSSION
A. Ballasting Current Distribution
As shown in Fig. 2, from the dc and TLP measurements for1.5-V NMOS transistors, the drive current and the on-resistanceshow no differences between the structures with the minimumgate-to-contact spacing and the ones with increased gate-to-con-tact spacing as expected. First, to analyze the impact of theGDCS, for a fixed GSCS of 0.1m, was measured for thestructures with GDCS of 0.1 and 1m, respectively. As can beobserved from Fig. 7, consistent with Fig. 2 (inset), even with
Fig. 7. High currentI–V curves for the 1.5-V NMOS transistor with twodifferent GDCS of 0.1�m and 1�m where GSCS is 0.1�m. The slope ofhigh-current regions is almost identical, butIt is nearly doubled with theincreased GDCS.
further increase in GDCS, the on-resistance remains unaffected.However, is nearly doubled with GDCS m.
It is instructive to note that, contrary to the experimental re-sults presented in this work, it has been reported in the past thatthe on-resistance is changed depending on the silicide thicknessand junction depth [4]. Since it is well known that the silicidecontact resistance is a strong function of interfacial doping con-centration (Silicide/Si), the silicide contact resistance is influ-enced by the variation of the silicide thickness [7]. Moreover,the junction depth can also affect the drain diffusion resistance.Therefore, it is likely that the impact of these factors was ob-served as slight changes in the on-resistance in [4], even withsilicided structures.
Nevertheless, based on the empirical results presented in thiswork, it can be conjectured that the increase of GDCS allevi-ates the current localization problem by further expanding theturned on portion of the finger width, which appears only fordevices with strongly nonuniform current distributions underESD stress. For devices with various finger widths, total failurethreshold currents, [mA], were measured for the low andhigh voltage transistors. As can be seen in Fig. 6, the total failurethreshold current does not scale with the drawn finger width forthe 1.5-V transistor. For the 3.3-V transistor, scales onlyfor a limited range of widths. This implies that the ESD cur-rent distribution for 1.5-V NMOS devices is highly nonuniformwhile it is nearly uniform for the narrow 3.3-V NMOS tran-sistors ( m). The data shown in Fig. 6(b) sup-port the observation that only devices with uniform ESD cur-rent distribution do not show dependence on GDCS. Thus, itcan be concluded that the increase in GDCS helps spread outthe ESD current more uniformly along the finger width, whichleads to improvement in the effective value of , though theincrease in the ballasting resistance with the GDCS is hardly no-ticeable. This is apparent from Fig. 3 and from the total failurethreshold current ( ) data in Fig. 6(a) for the 1.5-V NMOSdevices where the ESD current distribution is strongly nonuni-form. In addition, for low voltage transistors, with adequate ex-ternal substrate bias, the dependence ofon GDCS disap-pears as shown in Fig. 5. This result also supports the argu-
OH et al.: IMPACT OF GATE-TO-CONTACT SPACING ON ESD PERFORMANCE 2187
Fig. 8. Equivalent circuit of the NMOS including the parasitic lateral n-p-nbipolar transistor when the lateral n-p-n is on.I is the channel current,Iis the avalanche-generated current, andI is the substrate current.
ment that the increase in GDCS alleviates current localizationfor low voltage transistors. In other words, it seems that for thesalicided devices, the shorter the gate-to-drain contact spacingis, the stronger the current localization. Therefore for the de-vices requiring higher ESD strength, minimum gate-to-contactspacing should be avoided unless substrate bias can be used inthe protection circuit design [8].
B. Characteristics of the Lateral n-p-n
In general, the ESD hardness of NMOS devices can bedescribed in terms of the primary device parameters of theparasitic lateral n-p-n transistors, such as the current gain (),avalanche multiplication factor ( ), and effective substrateresistance ( ) [9]–[11]. When the lateral n-p-n turns on(Fig. 8), the , , and are given by [10]
(1)
(2)
(3)
Despite variation of the GSCS/GDCS, can be assumedto remain constant since the substrate doping concentration re-mains unchanged. In addition, the substrate contact is designed20 m away from the STI boundary at the source side and themaximum variation in the distance of substrate contact from thegate poly edge can be 0.65m due to increase in GSCS. This0.65- m variation in the distance of substrate contact will havea negligible impact on the effective substrate resistance value.Therefore, the current gain and avalanche multiplication are ofprimary interest for studying the impact of variations of gate-to-contact spacing on . The lateral n-p-n operation depends ona combination of , , and for a given power dissipa-tion. For a given ESD current, less avalanche multiplication andhigher current gain is preferable for higher ESD strength, sincestrong avalanche multiplication results from high fields whichin turn, leads to locally higher temperatures. The variation of theavalanche multiplication for the test structures can be observedby employing two-dimensional (2-D) device (MEDICI) simu-lation. It should be noted that in the test structures used in this
(a)
(b)
Fig. 9. Avalanche-generation current (I ) and multiplication factor (M ) forthe variation of (a) the GDCS and (b) GSCS.
study, as the contact spacing is increased, the source or drainarea did not remain constant since the distance from the edge ofthe gate poly to the STI boundary on the source and drain sidealso simultaneously increased (Fig. 1). In addition, in the sim-ulations, the silicide layers are treated as virtual electrodes andthe effective substrate resistance of 5 k/ m is attached to thebottom substrate contact. For the thermal boundary conditions,a thermal electrode is defined at the bottom of the substrate andthe temperature of this thermal electrode is assumed to be thesame as the ambient temperature. It is important to note that weassume the simple thermal boundary conditions for the simula-tions since the results of the thermal simulations are intended toprovide only a relative comparison between different structuresfor a given thermal boundary condition. Furthermore, from thethermal point of view, the size of the simulation structure shouldbe fixed, otherwise the thermal boundary conditions change.Using the dc current sweep simulation mode, high-current char-acteristics were reproduced for the structures with minimumgate-to-contact spacings (GSCS/GDCS m) and also forlonger GDCS ( m) or GSCS ( m). As shown inFig. 9, the avalanche-generated current () and multiplica-tion factor ( ) are compared for the three cases. As the drain
2188 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
(a)
(b)
Fig. 10. To track the current gain of a lateral n-p-n transistor, the triggeringvoltage (V ) and holding voltage (V ) are measured for the 1.5-V and 3.3-VNMOS transistors. The data clearly show that the current gain is reduced by (a)increase in GSCS while it (b) remains nearly constant with GDCS.
current increases the generation current increases while the mul-tiplication factor decreases rapidly, regardless of the gate-to-contact spacing. Based on the simulation results, variations ofthe gate-to-contact spacing appear to have no impact on theavalanche process.
The increase in the current gain of the lateral n-p-n transistorcan result in an improvement of by conducting more currentfor a given ESD stress. In order to track the current gain of alateral n-p-n transistor with the variation of GSCS and GDCS,the ratio of the triggering voltage ( ) and holding voltage ( )is monitored for various test structures as shown in Fig. 10, sincethe current gain of a lateral n-p-n transistor (for a gate groundedNMOS) in a self-biasing mode is proportional to theratio [12]
(4)
where is the common-base breakdown voltage (withemitter open-circuited), is the breakdown voltage forthe common-emitter configuration (with base open-circuited),and is a constant. For a constant GDCS of both the low- andhigh-voltage devices, the ratio of and decreases with in-crease in GSCS. However, compared with the values
(a)
(b)
Fig. 11. Base current (hole current) density vector atI = 1 mA/�m forthe device with (a) minimum gate to contact spacing, GSCS/GDCS= 0:1�mand (b) increased gate to source contact spacing, GSCS= 0:5�m. As GSCSincreases, wider emitter and base junction is utilized for the current conductionand this results in a drop in the current gain due to increase in base current for agiven collector current.
for GSCS variations, the values are nearly independentof the GDCS variations. As described earlier, for the test struc-tures, size of the source/drain is increased as the GSCS/GDCSincreases. Therefore, the effective area of the emitter (source)of the lateral n-p-n is enlarged with increase in the GSCS, andin turn, the effective current path is also increased. As shownin Figs. 11 and 12, for a given collector current, with the in-creased effective size of the emitter, more base current (holecurrent component) flows into the emitter for a given genera-tion current (Fig. 11), which results in a slight decrease in thecurrent gain (Fig. 12).
However, despite the decreased current gain with GSCS, im-provement in is observed with GSCS. Consequently, theincrease of with the GSCS is not attributed to the lateraln-p-n current gain. These results suggest that the mechanismfor improvement of with the gate-to-source contact spacingvariations is not dependent on the efficiency of lateral parasiticn-p-n transistor. In fact, the efficiency of the lateral n-p-n forconducting ESD current seems to be degraded or unchangedwith increases in gate-to-source contact spacing. Therefore themain cause of the improvement in due to increase in GSCSis still unclear. Hence, to gain better insight into the physicalbehavior, we next explored possible thermal effects involved inthe gate-to-source contact spacing by performing electrothermalsimulations.
OH et al.: IMPACT OF GATE-TO-CONTACT SPACING ON ESD PERFORMANCE 2189
(a)
(b)
Fig. 12. (a) Current gain (�) versus the drain current (I ) and (b) the basecurrent (I ) versus the generation current (I ) for the device with differentgate-to-contact spacings.
C. Thermal Effects
Before investigating any thermal effects involved in themechanism of improvement with gate-to-source contactspacings, it is important to discern any possible role of theuniformity of current distribution (arising solely due to increasein GSCS or the effective emitter area of the lateral n-p-ntransistor) as the primary physical mechanism responsiblefor the improvement. As shown in Fig. 6(b), the currentdistribution is nearly uniform for the 20m wide high-voltagetransistors and increase in GDCS has no impact onsincethe current is already uniformly distributed. Using the sameargument, increase in GSCS should also have little impact onthe uniformity and on . Nevertheless, the data for highvoltage devices in Fig. 3 clearly show the impact of GSCS eventhough the current is already uniform (since m).Hence, it can be concluded that the observed improvement of
with GSCS is not primarily due to any improved uniformityof current distribution. The above arguments are particularlyvalid for the high-voltage (3.3 V) transistors.
In order to investigate any increase in thermal capacity dueto enlargement of power dissipating volume along with theincrease in GSCS/GDCS, the temperature distributions in thedevice have been compared using electrothermal simulations.Current flowlines and temperature distribution contours for
(a)
(b)
(c)
Fig. 13. Current flowlines and temperature distribution contours at the draincurrent of 1 mA/�m for the three different structures are shown. (a) GSCS=
0:1�m and GDCS= 0:1�m, (b) GSCS= 0:1�m and GDCS= 0:5�m, and(c) GSCS= 0:5�m and GDCS= 0:1�m.
a drain current ( ) of 1 mA/ m in the three different structuresare shown in Fig. 13. According to the simulation results, thelocation of the maximum temperature in the device remains thesame, despite differences in the maximum temperature valueitself. Due to the higher thermal resistance of STI structures andreduced thermal conductivity of upper passivation layers, theheat generated in the device under the ESD stress is confinedand mostly dissipated through the substrate. Therefore, changesin the STI boundary associated with variations of GSCS/GDCSinfluence the overall temperature distribution and the peaktemperature in the device as well. In Fig. 14, we show the effectof the gate-to-contact spacings on the temperature distribution.The temperature for the device with longer GSCS ( m)is significantly lower than that of the two other structures withGDCS of 0.1 and 0.5 m. The augmented power dissipatingvolume for the larger GSCS results in a lower peak tempera-ture for a given drain current. Thus for the device with largerGSCS, a higher ESD failure threshold can be obtained due toa reduction in the peak temperature. Therefore, under ESDconditions, the maximum temperature of the device for a given
2190 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
(a)
(b)
Fig. 14. Temperature distribution along thex andy direction [as indicated inFig. 13(a)] at the drain current of 1 mA/�m for the three different structures:(a) vertical temperature distribution and (b) lateral temperature distribution.
Fig. 15. Simulated maximum temperature for the two different test structureswith injected drain current. The maximum temperature increases more rapidlyas the power dissipating volume decreases for the shorter gate-to-source contactspacing. GDCS= 0:1�m.
drain current is higher due to reduction in the effective sourcesize resulting from smaller GSCS. The simulated maximumtemperature with the drain current is also plotted in Fig. 15.
Fig. 16. Total failure threshold current (IT ) for the two different teststructures having different noverlap lengths of S/D contact of 0.1�m and 0.4�m (D_ andS_ ). The inset shows the schematic of the test structure.GDCS/GSCS= 0:1�m.
The maximum temperature increases more rapidly with thedrain current as the power dissipating volume decreases for theshorter gate-to-source contact spacing. Note that a significantdifference in the maximum temperature can be expected athigher drain currents. To provide further support for the thermaleffect involved in the gate-to-contact spacing, the total failurethreshold currents ( ) of the 1.5-V test devices having twodifferent power dissipating volumes (arising due to increasedn overlap length of S/D contacts) are shown in Fig. 16. Itclearly indicates the dependence of on the size of thepower dissipating volume. For the device with_ _of 0.1 m, the total failure current is less than 25 mA.However, with increase in the power dissipating volume dueto the extension of _ _ , significant improvement inthe failure current can be obtained. It should be noted that thisimprovement of for low-voltage transistors is not attributedto any improved uniformity of current distribution since thegate-to-source/drain contact spacing is unchanged for both thetest structures in Fig. 16. The experimental result in Fig. 16agrees with the predictions based on electrothermal simulations(Figs. 13–15). Both sets of data suggest that thermal effectis the root cause of improvement with increase in GSCS.Therefore, it can be concluded that the observed improvementof with GSCS for the low voltage transistors is alsoprimarily due to thermal effects.
Also, it should be noted from Fig. 5(b) and (c) that both GSCSand GDCS have little impact on under substrate bias con-dition, which makes the current distribution more uniform forthe low voltage transistors. As shown in [2], the current flow-lines, with substrate bias, spread out more uniformly and deeperinto the substrate compared with the flowlines without substratebias. Hence, Fig. 5 implies that the volume associated with cur-rent (or temperature) distribution is significantly increased bysubstrate bias and that this volume is substantially larger thanthe one arising due to increase in GSCS. This is reflected in the
OH et al.: IMPACT OF GATE-TO-CONTACT SPACING ON ESD PERFORMANCE 2191
dramatic improvement of in Fig. 5(b) and (c), while showingalmost no sensitivity to GSCS and GDCS.
Finally, the overall physical mechanisms involved in thegate-to-contact spacing can be summarized. Although thechanges in ballast resistance cannot be observed directly,increases in the gate-to-drain contact spacing are effective inmitigating severe nonuniform ESD current conduction. The in-crease in the GDCS improves for devices with nonuniformESD current distributions, primarily the low-voltage (1.5 V)transistors used in this work. Despite reduction in current gainof the lateral n-p-n transistor, increases in GSCS lead to higher
primarily due to thermal effects arising from increase in thepower dissipation volume. This implies that for salicideddeep submicron devices with STI is sensitive to the thermalcapacity of the structures; and that the lateral n-p-n modelis not sufficient for describing the device behavior of thesedevices under ESD conditions. Therefore, analysis of ESDbehavior of advanced devices should consider both thermaleffects and the nonuniform bipolar conduction. Based on thisstudy, it is recommended that the minimum gate-to-contactspacing should be avoided for the design of protection devices.However, the minimum contact spacing can be used if suffi-cient substrate bias can be supplied to the NMOS device underESD conditions, because the substrate-triggered lateral n-p-ntransistor is independent of the gate-to-contact spacings asconfirmed experimentally in this work. Furthermore, on-goingexperimental work also show that the results obtained from thesingle finger structure correlate very well with the results frommultifinger structures provided the multifingers are uniformlytriggered.
IV. CONCLUSION
Improvement of ESD failure threshold with the gate-to-con-tact spacing for fully silicided NMOS transistors have been in-vestigated. The results provide new insight into ESD designrules for deep submicron technology based on detailed experi-mental and simulation results. It has been shown that the reduc-tion in current localization and increase in the power dissipationvolume with increases in the gate-to-contact spacing are the pri-mary factors influencing improvement of ESD performance. Ithas also been established that substrate biasing can help elim-inate the impact of the gate-to-contact spacing on the ESD ro-bustness. Results from this work suggest that even for silicidedprocesses, the gate-to-contact spacing should be carefully engi-neered to achieve efficient and robust ESD protection designs.
ACKNOWLEDGMENT
The authors wish to thank V. Gupta and Dr. A. Amerasekeraof Texas Instruments, Inc., Dallas, TX, for their insight in thedesign of test structures.
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[6] K.-H. Oh, C. Duvvury, K. Banerjee, and R. W. Dutton, “Investigation ofgate to contact spacing effect on ESD robustness of salicided deep sub-micron single finger NMOS transistors,” inProc. IEEE Int. ReliabilityPhysics Symp., 2002, pp. 148–155.
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[8] C. Duvvury, S. Ramaswamy, A. Amerasekera, R. Cline, B. Anderesen,and V. Gupta, “Substrate pump NMOS for ESD protection application,”in Proc. EOS/ESD Symp., 2000, pp. 7–17.
[9] A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, “Mod-eling MOS snapback and parasitic bipolar action for circuit-level ESDand high current simulations,” inProc. IEEE Int. Reliability PhysicsSymp., 1996, pp. 318–326.
[10] A. Amerasekera, V. Gupta, K. Vasanth, and S. Ramaswamy, “Analysisof snapback behavior on the ESD capability of sub-0.20�m NMOS,” inProc. IEEE Int. Reliability Physics Symp., 1999, pp. 159–166.
[11] A. Amerasekera, V. McNeil, and M. Rodder, “Correlating drain junctionscaling, silicide thickness, and lateral NPN behavior, with the ESD/EOSperformance of a 0.25�m CMOS process,” inIEDM Tech. Dig., 1996,pp. 893–896.
[12] S. M. Sze,Physics of Semiconductor Devices. New York: Wiley, 1981.
Kwang-Hoon Oh (S’92) received the B.S. and M.S.degrees in electrical engineering from Seoul NationalUniversity, Seoul, Korea, in 1990 and 1992, respec-tively. He is currently pursuing the Ph.D. degree atStanford University, Stanford, CA.
From 1992 to 1997, he was with SamsungElectronics, Puchon, Korea, where he was engagedin the design and development of power MOSFETsand IGBTs. During 2000–2001, he held summerresearch positions at Texas Instruments, Inc., Dallas,TX, where he focused on the modeling of ESD
reliability for advanced CMOS technologies. His research interests are in thearea of device simulation, characterization, and electrothermal and reliabilitymodeling for advanced deep submicron CMOS technologies with applicationsto IC circuits.
Mr. Oh is a member of the IEEE Electron Devices Society.
2192 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002
Charvaka Duvvury (SM’01) received the Ph.D. de-gree in engineering science from the University ofToledo, Toledo, OH.
After working as a Postdoctoral Fellow in physicsat the University of Alberta, Alberta, ON, Canada,he joined Texas Instruments, Dallas, TX, in 1977. Heinitially worked in the Houston DRAM Group as aDesign/Product Engineer for 4K/16K DRAMS. Hethen was part of the first 256K CMOS DRAM designand the Advanced Development Group that workedon the 1 Meg DRAM with specific contributions in
DRAM circuit design, transistor modeling, and reliability studies. He joined theSemiconductor Process and Device Center, Dallas, in 1988, where his work wason the transistor modeling of CMOS/BiCMOS technologies and development ofESD protection for high voltage designs and submicron CMOS technologies. Hewas elected Senior Member of Technical Staff in 1990, Distinguished Memberof Technical Staff in 1997, and Texas Instruments Fellow, also in 1997. Hiscurrent work is on ESD development for deep submicron CMOS technologies.He has published over 65 papers in technical journals and conferences and holds25 patents with several pending. He has coauthored books on hot carriers (NewYork: Van Nostrand Reinhold, 1992), modeling of electrical overstress (Boston,MA: Kluwer, 1994), and ESD reliability phenomena and protection design (NewYork: Wiley, 1995).
Dr. Duvvury is a recipient of the Outstanding Contributions Award fromthe EOS/ESD Symposium (1990), Outstanding Mentor Award from theSRC (1994), several Best Paper Awards from the EOS/ESD Symposium,and Outstanding Paper Award from the International Reliability PhysicsSymposium. He has been very active in the EOS/ESD Symposium, where hewas the Technical Program Chairman of the 1992 Symposium and was theGeneral Chairman of the 1994 ESD Symposium. He is currently a member ofthe ESD Association Board of Directors, promoting university education andresearch in ESD. He is also a member of Eta Kappa Nu and Sigma Xi.
Kaustav Banerjee(M’99) received the Ph.D. degreein electrical engineering and computer sciences fromthe University of California, Berkeley, in 1999.
He was with Stanford University, Stanford,CA, from 1999 to 2002 as a Research Associateat the Center for Integrated Systems. In July2002, he joined the Faculty of the Department ofElectrical and Computer Engineering, Universityof California, Santa Barbara, as an AssistantProfessor. His research interests include nanometerscale circuit effects and their implications for
high-performance/low-power VLSI and mixed-signal designs and their designautomation methods. He is also interested in some exploratory interconnectand circuit architectures such as 3-D ICs, integrated optoelectronics, andnanotechnologies such as single electron transistors. He co-advises severaldoctoral students at Stanford University, University of Southern California,Los Angeles, and the Swiss Federal Institute of Technology (EPFL), Lausanne,Switzerland. From February 2002 to August 2002, he was a Visiting Professorat the Circuit Research Labs of Intel, Hillsboro, OR. In the past, he has alsoheld summer/visiting positions at Texas Instruments, Inc., Dallas, TX, andEPFL-Switzerland, and has consulted for several EDA companies in the SiliconValley. He has authored or coauthored over 70 technical papers in archivaljournals and refereed international conferences and has presented numerousinvited talks and tutorials.
Dr. Banerjee served as Technical Program Chair of the 2002 IEEE Inter-national Symposium on Quality Electronic Design (ISQED ’02), and is theConference Vice-Chair of ISQED ’03. He has also served on the technical pro-gram committees of the ACM International Symposium on Physical Design, theEOS/ESD Symposium, and the IEEE International Reliability Physics Sympo-sium. He is the recipient of a Best Paper Award at the 2001 Design AutomationConference.
Robert W. Dutton (F’84) received the B.S., M.S.,and Ph.D. degrees from the University of California,Berkeley, in 1966, 1967, and 1970, respectively.
He is currently Professor of electrical engineering,Stanford University, Stanford, CA, and Director ofResearch at the Center for Integrated Systems. Hehas held summer staff positions at Fairchild, BellTelephone Laboratories, Hewlett-Packard, IBMResearch, and Matsushita during 1967, 1973, 1975,1977, and 1988, respectively. His research interestsfocus on integrated circuit processes, device and
circuit technologies (especially the use of computer-aided design (CAD) indevice scaling and for RF applications). He has published more than 200journal articles and graduated more than four dozen doctoral students.
Dr. Dutton was Editor of IEEE TRANSACTIONS ON COMPUTER-AIDED
DESIGN from 1984 to 1986, the winner of the 1987 IEEE J. J. Ebers and 1996Jack Morton Awards, the 1988 Guggenheim Fellowship to study in Japan, waselected to the National Academy of Engineering in 1991, and was also beenhonored with the Jack A. Morton Award in 1996 and the C&C Prize (Japan)in 2000.
