Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing
Colin Rawlings1,4, Yu Kyoung Ryu1, Matthieu Rüegg1,3, Nolan Lassaline1, Christian Schwemmer1, Urs Duerig1,4, Armin W. Knoll1*, Zahid Durrani2, Chen Wang2, Dixi Liu2, and Mervyn E. Jones2
1 IBM Research – Zurich, Saeumerstrasse 4, 8803 Rueschlikon, Switzerland
2 Department of Electronic and Electrical Engineering, Imperial College London, London SW7 2AZ, UK
3 Microsystems Laboratory, Institute of Microengineering, Ecole Polytechnique Fédérale de Lausanne, 1015 Lausanne, Switzerland
4 now at SwissLitho AG, Technoparkstrasse 1, 8005 Zuerich, Switzerland
E-mail: [email protected]
Abstract
The fabrication of high-performance solid-state silicon quantum-devices requires high resolution patterning with minimal substrate damage. We have fabricated room temperature single-electron transistors (SETs) based on point-contact tunnel junctions using a hybrid lithography tool capable of both high resolution thermal scanning probe lithography and high throughput direct laser writing. The best focal z-position and the offset of the tip- and the laser-writing positions were determined in-situ with the scanning probe. We demonstrate < 100 nm precision in the registration between the high resolution and high throughput lithographies. The SET devices were fabricated on degenerately doped n-type > 1020/cm3 silicon on insulator (SOI) chips using a CMOS compatible geometric oxidation process. The characteristics of the three devices investigated were dominated by the presence of Si nanocrystals or phosphorous atoms embedded within the SiO2, forming quantum dots (QDs). The small size and strong localisation of electrons on the QDs facilitated SET operation even at room temperature. Temperature measurements showed that in the range 300 K > T > ~100 K, the current flow was thermally activated but at < 100 K, it was dominated by tunnelling.
Keywords: nanofabrication, thermal scanning probe lithography, laser writing, single electron transistor, mix and match processing
Accepted version of paper published in Nanotechnology (2018)
Nanotechnology. 2018 Sep 24. doi: 10.1088/1361-6528/aae3df. [Epub ahead of print]
Published in Nanotechnology (2018)
Nanotechnology. 2018 Sep 24. doi: 10.1088/1361-6528/aae3df
1. Introduction
For over 40 years, CMOS-based devices have met the evolving requirements of integrated circuits through continuous improvements in speed, complexity and packing density. This has been achieved mainly through reduced device dimensions, with an accompanied evolution of device structure. With decreasing dimensions, challenging barriers are encountered in device physics, and at dimensions < 10 nm, quantum effects increasingly and adversely influence device characteristics. For example, the operation of a nominally “classical” Fin-FET, with a fin only ~ 4 nm wide, has been shown to be fundamentally limited by quantum confinement []. While there is an on-going exploration of new materials such as III-V and III-V on silicon [], graphene [], MoS2, [] etc., there will be significant manufacturing problems with the inclusion of such technologies into any existing product line. Fortunately, it is also possible to achieve ‘beyond CMOS’devices in silicon through the development of single electron transistors (SETs), which are particularly attractive because, unlike in ‘classical’ transistors, a reduction in size inherently improves their performance. In SETs, an “island” or quantum dot (QD) is located between source and drain electrodes and is separated from them by tunnel barriers. An electric field established between source and drain facilitates the tunnelling of electrons onto and off unoccupied energy levels on the island. The proximity of a gate electrode(s) adds an additional degree of control, thus replicating conventional transistor actions.
Room temperature (RT) QDs and SETs [,] are promising devices for ‘beyond CMOS’ nanoelectronics at the sub-10 nm scale. RT operation of these devices requires a highly nanoscale (~5 nm) semiconductor ‘island’ or QD, with single-electron charging energy Ec >> kBT = 26 meV at 300 K []. Device fabrication in Si retains compatibility with present CMOS nanofabrication methods. Nanofabrication of these devices is typically performed using high-resolution lithography, either alone or in combination with oxidation [,,,] or with material morphology [,,,]. Si QDs may be defined using lithography and oxidation [], Si layer roughness [], Si nanocrystals [,], Si nanowires with cross-section variation along the length [,], or by using impurity atoms or nanocrystals embedded within SiO2 [].
These state of the art devices were fabricated using mask-less lithographies, which allow researchers to investigate ultra-small device geometries before implementation and mass production. For mask-less methods, currently high resolution is accompanied by a severe decrease in throughput []. Fortunately, typical devices have their high resolution features localised in small areas of the design, with the remainder being composed of coarse features. These coarse features can be defined with a high throughput lithography technique, in so-called mix-and-match lithography. Optical lithography has been successfully combined with nano-imprint lithography for the fabrication of nano-biosensors [] and quantum point contacts []. However, the use of two distinct lithographic techniques doubles the work load for registration, imaging and pattern transfer. This additional effort has motivated the development of a hybrid approach [] [] where the same resist layer is exposed separately using optical and electron beam lithography. This hybrid approach provides better throughput than can be achieved using variable or shaped electron beams []. Alignment remains a critical issue for such techniques as the alignment metrology must be consistent between pairs of tools. This challenge has previously been addressed by mix and match of electron beam lithography (EBL) with electric field scanning probe lithography (SPL) []. Precise alignment of a high-resolution SPL pattern was achieved by imaging the EBL pattern utilizing the exemplary imaging capabilities of scanning probes. To our knowledge there is only one example of combining SPL, in this case scanning tunneling hydrogen depassivation lithography, with optical lithography []. The latter was used for the definition of implanted wires in Si to provide electrical contacts to the scanning probe written devices and required a separate process for the optical lithography.
Thermal scanning probe lithography (t-SPL) has recently demonstrated its suitability for meeting the need for a high-resolution lithography process which causes minimal substrate modification. The fabrication process is based on a polymeric transfer stack that provides a high thermal resistance and therefore decouples the lithography process from the substrate type []. 11 nm half pitch dense line patterns have been fabricated in the substrate with sub-10 nm feature size []. This high resolution is paired with the capability to address existing features on a substrate with sub-5 nm accuracy [].
In this work we have paired t-SPL with integrated direct laser writing in an hybrid mix and match approach. Like the heated cantilever, the focused laser beam is able to trigger the thermal decomposition of the resist layer. The laser beam was focused on the thermally insulated resist by means of a lens mounted on the cantilever holder (see Fig. 1), thus providing simple integration in a single tool. Moreover, the same positioning system was used for t-SPL and laser writing, reducing the alignment challenge to simply determining the geometrical offset between the tip writing and laser writing positions. Furthermore, neither lithography step involved charged particles, mitigating concerns over unwanted substrate modification. Thus we arrived at a simple integration of high throughput laser writing with 10 nm resolution t-SPL lithography [] in a single patterning tool.
We studied the fabrication, electrical behaviour and interaction between QDs within ~ 10 nm scale point-contact Si/SiO2/Si tunnel junctions operating as RT SETs. Samples, having prepatterned features with 30 × 30 μm2 areas designated for the integration of the point-contact transistor devices, were first fabricated using optical lithography. The process flow of the mix and match lithography, including the calibration of the laser writing offset relative to the tip writing position and the registration with the pre-patterned sample is described first. The lithography for each pair of devices took 5 minutes and these were transferred into the silicon layer by reactive ion etching (RIE). The overall chip design incorporated several structures, enabling different functions, e.g. memory, to be investigated, but the focus of this paper is specifically on the electrical performance of the QD transistors. A pre-oxidation feature size of the central point contact of 25 nm was achieved with side gates approaching the channel to a distance of ~ 50 nm.
Figure 2. Process flow used in fabricating the single electron transistors. (a) Device geometry. The pre-pattern present on the wafer before SET fabrication is shown in pink. The central 30 µm x 30 µm square was structured using a combination of laser writing (blue area) and thermal scanning probe lithography (dark green area). The regions of the sample effected by the steps shown in panels c (light green), d (dark green) and e (blue) are shown. (b) Imaging of laser written lines by the scanning probe in order to determine the offset between the laser focus and the probe's tip. (c) Locating the existing surface features (the light green areas in panel a) using the probe's tip in order to align the device geometry with the sample's position in the tool. (d) Patterning of the high-resolution regions of the device geometry using t-SPL (dark green area in panel a). (e) Patterning of the low-resolution parts of the device geometry (blue area in panel a) using the laser. (f) Result of transferring the patterns into silicon using RIE. (g) Result of performing the thermal oxidation to form the point contact channel in the device channel.
Materials and methods
The SET devices were fabricated on 15 mm x 15 mm chips cut from an 300 mm ultrathin silicon on insulator (SunEdison Semiconductor, US) wafer. The wafer had a 12 ± 1 nm thick silicon layer with a (100) orientation which was isolated from the silicon substrate by a 25 nm thick buried oxide. The top silicon layer was highly doped (5 x 1020 cm-3) using phosphorus implantation (IMEC, Belgium).
The lithography transfer stack was deposited on the substrate by spin coating as described previously [,]. The top layer consisted of an 8.5 nm thick top layer of Polypthalaldehyde (PPA). PPA is a self-amplified depolymerization polymer [] with an unzip temperature of approximately 120 – 150°C. The PPA decomposes upon contact with the hot tip. During patterning a cantilever heater temperature of 950ºC was used and a tip-sample force of 15 nN was applied electrostatically to the cantilever. The electrostatic force was applied for 5 μs to bring the tip into contact with the sample. Patterning was stable at a pattering depth of 4-6 nm, sufficient for a reliable pattern transfer []. A loss of resolution due to tip erosion could not be observed.
The PPA layer was spin coated from an anisole solution. Underneath the PPA was a 2 nm PMMA (roughness ~ 0.3 nm RMS, 950 kg/mol, Allresist AR-P 672.02, diluted 1:19 in anisole) tip-protection layer, which was spin coated on top of a 2.5 nm SiO2 hard mask layer (roughness 0.23 nm RMS). The SiO2 was deposited using evaporation. The final, bottom layer of the transfer stack was an 18 nm thick layer of HM8006 (JSR Corporation), which was deposited using spin coating.
Figure 1. Experimental setup. a) Tip and lens holder. The lens is glued into a barrel for height adjustment. The cantilever is mounted into an aluminium holder attached to a PCB. Contact springs provide electrical signals to the cantilever. b) The tip holder is mounted to the z-piezo and coarse positioning stage. The collimated laser beam is deflected by a dichroic beam splitter onto the focussing lens. For imaging a lens collects the reflected light from the laser and from a white LED onto the camera. The laser uses the same xy positioning system for writing, which provides a fixed offset between tip and laser position.
In addition, the thermal decomposition of the PPA could be triggered using a 100 mW laser with an emission wavelength of 375 nm integrated into the t-SPL setup, see Fig. 1. A aspherical lens (Thorlabs 352610-A, f = 4 mm, Ø = 6.33 mm) mounted on the tip holder focussed the laser onto the sample. During patterning the output power was set to 30 mW. A linear scan speed of 100 µm/s was used since the model based positioning control of the piezo positioner [] required for high speed scanning has not yet been extended to vector scanning. The laser writing process took less than 30 s.
Reactive ion etching was performed in the manner described in [] and []. The duration of the first, critical O2/N2 etch used to open the SiO2 hardmask was 6 s.
Electrical characterisation of the point-contact (PC) transistors (SETs) was performed at room temperature (RT = 300 K) using probed measurements, and from 300 – 10 K using a CTI-Cryogenics closed cycle Helium cryostat with electrically bonded samples. Drain-source current (Ids) vs. drain (Vds) and gate voltage (Vgs) were measured using Keithley 236 source measurement or Agilent 4155B parameter analyser units, with Ids curves measured as Vds was swept at constant Vgs, and Vgs stepped from one curve to the next. Drain-source differential conductance (gds) vs. Vds and Vgs characteristics were extracted from the Ids – Vds, Vgs data.
Figure 3. Results of the alignment process for the mix and match lithography scheme. (a) The topography measured by the t-SPL system after writing series of features with the laser in the resist layer. Between each feature the tip height above the surface was increased by 4 µm to identify the z position of the best focus. (b) Cross section shown in blue in (a). The width (full width at half maximum) of the written line is 1.2 µm. The line’s sidewall slope controls the uncertainty of the width of laser written features after pattern transfer. The black lines show the effect of an uncertainty in the etch depth of ±1 nm on the position of the edge of the laser written line. (c) Topography image of one of the features used for alignment. (d) The result of aligning the lithographic design file (see Fig. 2a) to the measured sample topography (light green boxes).
Results
Hybrid Lithography
The process flow for the hybrid lithography scheme is shown in Fig. 2. First, the offset between the laser focus and the cantilever's tip was measured by writing lines with the laser at different z heights in an unused portion of the sample. The topography resulting from the exposure of the resist by the laser was then measured using the scanning probe. Finally the offset between the laser focus and tip was determined using cross-correlation (Fig. 2b). Next, the scanning probe was used to locate a pair of features in the vicinity of the area to be patterned (Fig. 2c). The detected location of these features was used to align the device geometry with the sample's position in the tool. The high resolution parts of the device design were written first using t-SPL (Fig. 2d). The remaining low resolution features were then written using the tool's integrated laser writer (Fig. 2e). The resulting resist pattern was transferred into the top silicon layer of the SOI using reactive ion etching (Fig. 2f). This left a channel, nominally 20 nm wide, in the SET structure. To form the QD from the lithographically defined channel, the substrate was subjected to a geometric thermal oxidation process in a tube furnace at 1000 oC for 5 mins. This had the effect of converting the silicon surfaces to oxide, thereby constricting the channel width to the required sub-10 nm feature size and thus facilitating the formation of the point contact [], [] (see Fig. 2g). Following oxidation, contact windows were opened and Cr/Al contact metallisation deposited to facilitate probing and bonding for electrical characterisation.
Alignment process
Figure 4. Topography results from the fabrication of a single electron transistor using the hybrid lithography process. (a) AFM topography image after performing the hybrid t-SPL and laser lithography process on the PPA resist layer. (b) Optical image of the final device after pattern transfer using RIE. (c) AFM topography image of the resist layer after t-SPL patterning but before laser writing. (d) Close-up of the blue dashed box shown in (c) which contains the channel and side gates. (e) AFM image of the region shown in (c) after RIE. (f) Close-up of the region marked by the red dashed box in (e). (g) Cross sections of the transistor channel. The cross sections are marked by the dashed lines in (d) (blue line, resist after t-SPL) and (f) (red line, silicon after reactive ion etching). Before accounting for the effects of tip convolution and defining the widths at half the maximum of the depth the gate spacing is 46 nm and the channel width is 36 nm. (h) The estimated AFM tip shape reconstructed using a blind tip estimation algorithm []. The tip profile is shown in the inset along with the position of the cross section. The estimated tip width at the depth of 8.5 nm [black horizontal, dashed lines in panels (g) and (h)] considered in panel (g) is 11 nm suggesting a channel width of 25 nm.
Fig. 3a shows a set of written structures that were used to measure the offset between the probe's tip and the laser focus (see Fig. 2b). As each cantilever chip adopts a slightly different position within the holder, this offset changes each time the cantilever is replaced in the tool. The repeatability of the cantilever loading is roughly ± 50 µm in x and y and ±10 µm in z. Each of the test structures shown in Fig. 3a was written at a different z height. The height was varied in 4 µm increments from which the operator selected the height yielding the best focus. The width (1.2 µm, full width half maximum) of the written profile (see Fig. 3b) was measured in preparation for the path calculation for the laser writing process. This beam width results in a writing primitive for the laser writing process which is 4 orders of magnitude larger than the 10 nm x 10 nm writing primitive offered by t-SPL.
For the alignment of the prepatterned silicon wafer we scanned two features close to the central device area (see Fig. 2c). Fig. 3c shows the topography image recorded for one of the reference features. This topography image was used in combination with the topography image for the second feature to position the device's design file in the tool's coordinate system (see Fig. 3c). The transformation used to align the images was the sum of an isotropic scaling, a rotation and a translation.
Alignment accuracy
Our laser writing implementation uses the same piezo scanner used for t-SPL patterning. Therefore we exploit the precision of t-SPL imaging to detect existing features on the surface. On the other hand, larger areas need to be stitched, however, the resolution of the piezo-motor driven coarse stage of 5 nm provides sufficient accuracy, comparable with the size of the laser features and hence passive positioning is sufficient. The uncertainty of the overlay between the t-SPL written patterns and existing surface features has been treated in detail in [] where the detection of features with a lateral extent of several microns buried beneath a spin coated resist was considered. It was found that sub-10 nm detection errors could occur even for surface topographies following a spin coating of just 4 nm thickness. The relative lateral offset between the laser and tip written features may be established with similar accuracy by imaging laser written features (see fig. 3a), since the feature dimensions are comparable (10 nm thick and 1 μm wide). Moreover, for the alignment relative to the optical prepatterns we consider the size of the topographical feature (Fig. 4c) of 5 µm × 5 µm × 40 nm and calculate a cross-correlation error of less than 2 nm [], [].
The alignment errors in our hybrid lithography process are instead dominated by two effects. The first is thermal drift. In our laboratory environment the sample drifts relative to the tip holder at a typical rate of 10 nm / minute. Since the entire t-SPL and laser writing process takes 5 minutes we expect an offset of 50 nm between the tip written features (or the prepattern) and the laser written features to develop due to this thermal drift. In the case of t-SPL patterning the topography measured during writing can be used [] to apply an on-the-fly drift correction during patterning. However, this is not possible during laser writing as the topography is not recorded during the write process.
The second error source arises from the rather shallow side wall slope of the laser written structure. This shallow slope originates from the finite size of the focal spot. The expected error may be quantified by considering the etch process which will effectively "cut" (see fig. 2f) the continuous topography, , at a certain depth, , converting it into a binary mask:
Typically this etch process can be controlled to within 1 nm []. Analysis of the cross section in Fig. 3b (black line) yields an expected uncertainty in the width for laser written features of 50 nm.
Thus the thermal drift contributes a 50 nm uncertainty in the centre position of the laser written line, while the sidewall slope results in a similar uncertainty in the width of the written line. This uncertainty of the edge position of around 100 nm defines the design rules for fracturing the device design file into the t-SPL and laser written parts.
Device fabrication
Two SETs were fabricated in each of the 30 μm x 30 μm areas. Fig. 4a shows the measured surface topography of the resist for one such area after both parts of the hybrid lithography process had been completed. The t-SPL written part is marked by the green dashed lines. The remaining parts were written by the laser in less than 30 s. Each t-SPL field took 1.9 min to complete, resulting in a total patterning time of a mere 4.5 min for the entire area. Figs. 4d and 4f show the critical parts of the device, the channel and side gates before and after etching. Fig. 4g shows the measured cross sections perpendicular to the channel at these two points in the fabrication process. The depth of the feature transferred into the silicon top layer was 17 nm. This is 5 nm greater than the nominal thickness of the silicon layer, to ensure that no short circuits existed between the parts of the device.
A linear scan speed of 100 µm/s and a line width/spacing of 1 µm yields an areal throughput of 4×105 µm2/h. This is 10x greater than the fastest speeds demonstrated by t-SPL []. We estimate that better control algorithms, a more powerful laser, and a more robust mechanical setup could provide stable laser writing speeds of 1 mm/s, enhancing the throuput by a further factor of 10, providing an area of 4 mm2 to be written in an hour. We note that the contact pads of the design (12 times 200x200 µm2) and the leads (1/8th of the pad area) could then be written in 8 minutes (or 1.5 h with the current system).
Assessing the fabricated width of the channel is challenging. Due to concerns over sample modification SEM inspection was not possible and so AFM was used. At these small dimensions tip convolution contributes significantly to the apparent widths to protruding features. We applied the blind tip estimation algorithm of [] implemented in the Gwyddion AFM software to the topography of Fig. 4f. The reconstructed tip profile was consistent with a dilation of the channel width of 11 nm, yielding an estimated channel width of ~25 nm and a side gate spacing of 55 nm. This agrees well with the device's designed width of 20 nm and gate spacing of 50 nm.
Electrical characterisation
Fig. 5(a) shows the RT Ids – Vds, Vgs characteristics for a point contact SET (Device A) with lithographically defined (pre-oxidation) width ~25 nm. The Ids – Vds curves are non-linear, with a low current ‘Coulomb blockade’ region within | Vds | < ~0.1 V (dashed line 1-2, Fig. 5(a)). Assuming a QD origin and similar tunnel barriers, the Coulomb blockade edge Vc = 0.1 eV corresponds to a total island capacitance [], [] C = e/Vc = 1.6 aF, and a Coulomb charging energy Ec = e2/2C = 50 meV > kBT = 26 meV. Here, Ec is defined as the energy necessary to charge the QD with an electron from the source, and is half the Coulomb gap within the QD, e2/C. The comparatively small charging energy implies weaker single-electron effects in comparison with previous ultra-small QDs in PC SETs [], and suggests that an unoxidised Si nanocrystal or a group of impurity atoms, rather than a single impurity atom forms the QD. Outside this region, Ids is lower in magnitude for negative applied bias, implying that an asymmetric, diode-like potential exists along the conduction path. The asymmetry of the potential is likely to be associated with the potential profile of the oxidised point-contact neck. Ids oscillates strongly with Vgs, with two large peaks (labelled A and B) in the range -0.4 V < Vgs < 0.5V, and three smaller current peaks (for Vgs > 0.5 V). These may be associated with RT single-electron current oscillations in the device []. The extracted gds – Vds, Vgs curves (Fig. 5(b)) show further features in the characteristics. A fine structure consisting of two smaller peaks exists in gds (labelled F1 and F2, arrowed, Fig. 5(b)), forming lines, which shift across the plot. There is also a shift in position in Vgs of the main oscillation peaks ‘A’ and ‘B’ as Vds increases, e.g. the gds minimum at Vgs = -0.4 V, Vds = 0 V (Fig. 5(b)) shifts to Vgs = 0 V and Vds = 0.18 V.
Figure 5. Electrical characterisation of PC SET (Device A) having a pre-oxidation width of ~30 nm. (a) RT Ids – Vds, Vgs characteristics showing non-linear behaviour, with a low current ‘Coulomb blockade’ region within | Vds | < ~0.1 V (dashed line 1-2), which reflects a total island capacitance of 1.6 aF and a Coulomb charging energy of 50 meV. (b) The extracted gds – Vds, Vgs curves showing two smaller peaks existing in gds (labelled F1 and F2, arrowed), forming lines, which shift across the plot with increases in Vds. These are shown in line plots of the gds – Vgs data (c-d), at positive bias (Fig. 5(c), Vds = 0 – 0.15 V) and at low bias values (Fig. 5(d), Vds = 0 – 0.1 V). These illustrate the main oscillations in gds, the behaviour of the finer peaks in the data (arrowed in Fig. 5(b)), and additional current switches, labelled ‘a’ and ‘b’. (e) A schematic drawing of the nanometre scale SiO2 neck of device, implying that only a few randomly distributed nanocrystals or P atoms can exist within this region, which are encapsulated by SiO2, to form tunnel barriers, (f) schematic showing two Coulomb diamonds (solid lines) and band diagrams indicating the position of the Coulomb gap Ec with respect to the source (EFS) and drain (EFD) Fermi energies at various points along the diamonds. Peaks in gds (shown schematically by lines in red) occur along the edges of diamonds, e.g. for the N electron number diamond, along the top right edge and at the central point between the diamonds, the upper edge of the Coulomb gap is resonant with EFS.
Fig. 5(c-d) shows line plots of the gds – Vgs data, at positive Vds = 0 – 0.15 V, Fig. 5(c), and low bias values Vds = 0 – 0.1 V, Fig. 5(d), to better illustrate the main oscillations in gds, the behaviour of the finer peaks in the data (arrowed in Fig. 5(b)), and additional current switches, labelled ‘a’ and ‘b’. Fig. 5(c) illustrates that as Vds increases towards 0.15 V, the large gds peak labelled ‘C’ at Vds = 0 V, Vgs = -0.05 V is supressed with a simultaneous evolution of the main oscillation peaks ‘A’ and ‘B’, at higher and lower Vgs value. The width of the peak ‘C’ is ∆VgsC = 0.5 V. Assuming a QD origin, this corresponds to a gate capacitance [], [] Cg = e/∆VgsA = 0.32 aF. Changes in the zero Vds bias oscillation period, in Fig. 5 (c-d) at Vgs > 0.2V, imply corresponding changes in Cg. For Vgs > ~ 0.2 V, in addition to a smooth oscillation in gds, two ‘telegraph signal’ like switches occur, marked ‘a’ and ‘b’. Switch ‘a’ becomes more prominent as Vds increases. These switches are likely to be associated with the charging/discharging of a defect state close to the conduction path through the PC neck. We note that unlike the main oscillation peaks, e.g. ‘A’ and ‘B’, or the fine structure peaks F1 and F2, the gds switches ‘a’ and ‘b’ occur abruptly with Vgs, implying a defect state rather than a QD origin.
The fine features F1 and F2, marked by arrows in Fig. 5(c), occur near Vgs ~ 0 V across the Vds range. There are however small shifts in position of these peaks. At low bias (Vds < 0.1 V), the peak positions are marked by dashed lines, Fig. 5(d), and evolve out of a splitting of the main peak centred at Vgs = -0.05 V. As Vds increases past 0.1 V, the peaks are seen to cross, F2 shifting to a lower Vgs value and a jump in the position of F1 to higher a Vgs value, near Vds ~ 0.1 V, Fig. 5(c).
The characteristics of two additional devices are now considered. Fig. 6 (a & b) shows the RT Ids – Vds, Vgs characteristics for a second, similar PC SET (Device B). Qualitatively similar behaviour is observed compared to Device A, with a central, low current region with Vds (here between -2 V < Vds < 1 V) and a prominent oscillation in Ids with Vgs. Four large current peaks can be seen, with finer features also visible. The average peak width in this device is ∆Vgs ~1 V. The average current magnitude in this device is lower than in device A, implying a higher resistance of the tunnel barriers isolating the quantum dot, and/or a stronger secondary potential along the current path. The increased width of the central, low current region in comparison to Device ‘A’ suggests the contribution of a secondary potential in addition to Coulomb blockade of the QD.
Figure 6. The electrical characteristics of two additional devices. (a) The RT Ids – Vds, Vgs characteristics for Device B, showing behaviour qualitatively similar to Device A. Key features are a central, low current region (between -2 V < Vds < +1 V) and a prominent oscillation in Ids with Vgs showing four large current peaks and also finer features. (b) line-scan plots of the Ids – Vgs data at Vds values -5.0 to +2.25 V showing the oscillations with greater clarity. (c) Temperature dependence, ~200 K to RT, of the Ids – Vds characteristics of a third device, Device C. The characteristics are symmetrical about zero bias, with current magnitudes comparable to Device A. (d) Further temperature dependence, 10 K to 300 K in 20 K steps to 270 K with a final step of 30 K, of the Ids – Vds characteristics of Device C. Below 200 K, the characteristics show asymmetry and below ~100K, for the range -0.2 V < Vds < 0.15 V, the current magnitude reduces sharply. (e) An Arrhenius plot of ln(Ids) vs. 1/T, extracted from the data for Device C for Vds values 0.01 – 0.2 V. It is seen that the current is thermally activated in the range 300 K > T > ~100 K, but below 100 K, shows only a weak temperature dependence and is dominated by tunnelling. (f) Activation energies Ea for the thermally activated portion of the data, extracted using the maximum slope of the ln|Ids|/T = Ea/kB. This plateaus rapidly with increasing Vds.
The temperature dependence of the Ids – Vds characteristics of a third device, Device C, is shown in Fig. 6 (c & d). The characteristics are symmetrical about zero bias, from RT to ~200 K, Fig. 5(a), with current magnitude comparable to Device A. Below 200 K, the characteristics become asymmetric, and below ~100K, for the range -0.2 V < Vds < 0.15 V, the current magnitude reduces sharply (Fig. 5(b)). Furthermore, small current steps occur outside this region.
An Arrhenius plot of ln(Ids) vs. 1/T, extracted from the data is shown in Fig. 6(e). It is seen that the current is thermally activated in the range 300 K > T > ~100 K. However, below 100 K, the current shows only a weak temperature dependence and is dominated by tunnelling. The maximum slope in each curve for the thermally activated portion of the data, ln|Ids|/T = Ea/kB allows extraction of the activation energies Ea for each curve. These may be associated with the height of the maximum potential energy along the conduction path, and are plotted in Fig. 6(f). In a manner similar to our previous work on RT PC QD transistors fabricated by electron beam lithography (EBL) [], Ea increases and then saturates at ~28 meV as Vds increases. At higher Vds, any additional potential barriers along the conduction path are pulled down by Vds, Ea then corresponding to the Coulomb charging energy of the dominant QD. In Device C, this is Ec ~ Ea ~ 28 meV. This value is not sufficiently high compared to kBT at RT for strong single-electron effects at RT, and at best, a non-linearity in the Ids – Vds characteristic is observed (Fig. 5(a)).
Discussion
The characteristics of Fig. 5, Device A, are now considered in detail. In the PC SETs, the unoxidised Si source-drain regions on either side of the PC SiO2 ‘neck’ remain conductive at RT, as these are degenerately doped, P donors at concentration ND > 1020 /cm3, giving an average donor separation ~2 nm. Even in the case of regions nearest the SiO2 neck, where disorder in the doping concentration can be the most significant, at RT these are likely to remain conductive. The SiO2 neck therefore dominates device characteristics. The nanometre scale of this region implies that only a few nanocrystals or P atoms can exist within this region, distributed randomly (Fig. 5(e)). These are encapsulated by SiO2, which forms tunnel barriers with a potential energy well above kBT = 26 meV at RT, and making QDs at the nanocrystals or P atoms. Current transport occurs through the QDs, the current path following QDs with the smallest physical separation, and/or energy difference between energy states. Randomness in the specific position and number of QDs leads to variation in the exact electrical characteristics of different devices (e.g. Devices A - C), although these remain qualitatively similar. At given values of Vgs, energy states in the QDs can lie near the Fermi energy in the source, EFS. Current through the PC neck is then enhanced for gate voltage ranges where this occurs, similar to the range -0.4 V < Vgs < 0.5V in Fig. 5. Furthermore, Coulomb charging of the QD can occur, producing full or partial Coulomb diamonds [], [] in the Ids or gds – Vds, Vgs characteristics. For devices with ~10 nm PC necks, single RT QD characteristics can be observed [].
The shift in Vds, Vgs value of the large gds peaks ‘A’ and ‘B’ define the edges of partial Coulomb diamonds in Device A (dashed lines, inset to Fig. 5(a)). As an asymmetry exists in the Ids – Vds characteristics (Fig. 5(a)), we show only the Vds > 0 V part of the diamonds for clarity. Fig. 5(f) shows schematically two Coulomb diamonds (solid lines) and band diagrams indicating the position of the Coulomb gap Ec with respect to the source (EFS) and drain (EFD) Fermi energies at various points along the diamonds. Peaks in gds (shown schematically by lines in red in Fig. 5(f)) occur along the edges of diamonds, e.g. for the N electron number diamond, along the top right edge and at the central point between the diamonds, the upper edge of the Coulomb gap is resonant with EFS.
We now consider the origin of the fine peaks F1 and F2, Figs. 5(c and d). These features evolve from the gds peak ‘C’ at Vds = 0 V, and follow the valley between peaks ‘A’ and ‘B’, i.e. along the vertical dashed line between the Coulomb diamonds, Fig. 5(f). As these features do not lie parallel to the diamond edges, they cannot be associated with resonant tunnelling through excited states []. Along the vertical dashed line in Fig. 5(f), the upper edge of the Coulomb gap lies midway in the energy window EFS – EFD. This state is therefore likely to be occupied by an electron. We now propose that the double peaks F1 and F2 occur due to interaction of this state with a nearby, secondary QD. Electrostatic interaction between this and the primary QD causes peak splitting, in a manner similar to coupled double QDs at cryogenic temperatures []. It is interesting to note that the peak shift region around Vds ~ 0.1 V, Fig. 5(c), resembles anti-crossing behaviour seen in double QD systems, although in our case, this is at RT. Finally, additional peaks can occur in devices where multiple QDs exist along the conduction path, with different charging energies, i.e. a multiple tunnel junction []. However, the specific alignment of F1 and F2 along the vertical dashed line in-between the Coulomb diamonds, Fig. 5(f), and their evolution from a conductance peak of the primary QD (peak ‘C’), supports the argument that these features are associated with interactions with the primary QD.
Figure 7. Comparison of the room temperature electrical characteristics of SET devices made by t-SPL, reported in this paper, and by EBL, using data reported in ref. []. (a) Ids vs. Vds characteristics at three Vgs values for a t-SPL defined SET, with the experimentally measure values (open circles) fitted with a 9th order polynomial (solid lines). (b) Histogram showing the fit error ΔIds, normalised to the maximum current Ids-max in each Ids vs. Vds curve. (c) Ids vs. Vds characteristics at three Vgs values for an EBL defined SET. (d) Histogram showing the normalised error for the curves in (c). The EBL device shows a greater spread of error than the t-SPL device.
Finally, the characteristics of the t-SPL fabricated PC SETs may be compared to previous work on EBL fabricated devices []. The results of Figs. 5 & 6 show that SPL can be used to fabricate similar individual devices to those using state-of-the-art EBL. However, some differences exist in the characteristics. Telegraph signal like switches in the characteristics (‘a’ and ‘b’ in Fig. 5(d)) appear to be fewer than in EBL devices. Here, the use of thermal SPL may be significant, as there is less likelihood of implantation of electrons or the creation of defect sites in the buried oxide layer, in comparison with the high-energy electron beam in EBL. However, the primary purpose of the nanolithography in the PC SETs is not to define the QDs themselves, but to define small regions of SiO2, in order to limit the number of QDs influencing the characteristics and facilitating measurement of individual QDs.
The electrical characteristics of these devices are comparable to our previous EBL devices [], although the current in the t-SPL defined device is higher than in the EBL device, and it could be argued that it shows fewer fine features and switches in the current. This can be seen by reference to Figure 7, where a comparison has been undertaken of the room temperature electrical characteristics of a SET device defined by t-SPL and reported earlier in this paper (Fig. 5), and those made by EBL, reported as QD2 in ref. []. Figure 7(a) shows the Ids vs. Vds characteristics, at three Vgs values, for the t-SPL defined SET. Curves are chosen for the lowest and highest gate voltages in the measurement, and for zero gate voltage. These have been fitted using a 9th order polynomial, with the fit errors Ids, normalised to the maximum current Ids-max in the respective Ids vs. Vds curves, shown in (b). In a similar way, the Ids vs. Vds characteristics at three Vgs values for an EBL defined SET are shown in (c), and the accompanying histogram in (d).
Some observations may be made from these results. The error histogram, which may be used as an estimate of the influence of variations from a smooth polynomial trend in a given Ids vs. Vds characteristic, is much tighter for the SPL device than for the EBL device (~2% max. error vs. ~8% max. error). However, the error is created by any variation from the fit, including both actual noise, i.e. random variation in measured current, and any quantum effect peaks or steps. The polynomial fit also has an inherent fitting error, and this contributes to the overall error in the histograms. However, from the I-V data/fits this is relatively small, and all the fit R values are better than 0.9998. Given the higher current in the t-SPL device, it is possible that the device channel and QD core is simply larger, and hence less affected by any nearby states creating ‘noise’. With this argument, the lower error histogram width in the SPL device is simply because it is a larger, and not because of the fabrication method. However, the higher energy electron beam in EBL might also create more defect states in the vicinity of the device core (i.e. the substrate BOX), and these can easily interact with the core or form QDs in their own right. SPL would be less likely to do this. The richer structure in the EBL defined device might then arise from the creation of defect sites during EBL exposure interacting with the core QD behaviour. Defect formation at the Si/SiO2 interface during EBL has long been a subject of interest and discussion for the fabrication of MOS transistors and quantum devices. Many parameters are involved and, while it is speculative to generalise, it is encouraging to note recent work [], based on low temperature transport measurements and electron spin resonance, reporting the removal of shallow interface traps by annealing in forming gas and leading to nearly identical results between irradiated and unexposed MOS devices.
Conclusion
In conclusion, we demonstrate the fabrication and electrical characterisation of room temperature single electron transistors based on point-contact Si/SiO2/Si tunnel junctions. The fabrication was performed using a hybrid lithography technique combining laser writing and thermal scanning probe lithography to expose the same resist layer. A lens integrated into the tip holder allowed for an in-situ calibration of the best focal position, and ensured a constant offset between the t-SPL and the laser writing position. Scanning probe imaging was used to calibrate this remaining alignment challenge in-situ. Only a single patterning and pattern transfer step was required to define the high resolution devices and their leads to the predefined contact pads on the chip. An alignment accuracy of < 100 nm to existing features on the substrate and between the two lithographies was achieved, less than 10% of the size of the laser writing primitive. This simple and precise approach to mix and match lithography resulted in a total patterning time of less than 5 minutes to define the nanoscale dimensioned devices and the large area contact leads. Moreover, it is conceivable that 10 times faster laser patterning speeds are accessible as discussed above, providing patterning of the entire (currently prepatterned) contact pad design in approximately 8 minutes. Thus, the approach offers a simple and elegant solution for a rapid production of nanoscale prototype devices for researchers.
Here, point contact devices were fabricated in degenerately doped n-type SOI material, with oxidised ‘necks’ of ~10 nm dimension and a side gate spacing of 50 nm. The device characteristics were dominated by the presence of Si nanocrystals or phosphorous atoms embedded within the SiO2, forming QDs. The small size, and strong localisation of electrons on the QDs allows SET operation even at RT. While the electrical characteristics of these devices are comparable to similar EBL devices, the thermal SPL devices appear to suffer less from defect induced switches in the current. The electrical characteristics show RT single-electron current oscillations and additional, finer current peaks. Splitting of the latter occurs with gate bias, in a manner similar to peak splitting in larger, double coupled QD systems at cryogenic temperatures. It may be possible to attribute these features to RT electrostatic interactions between different QDs embedded within the SiO2 point-contact.
Acknowledgements
The authors would like to acknowledge valuable discussions with I. Rangelow, at the University of Ilmenau, Germany. The authors also acknowledge J.-F. de Marneffe at IMEC, Belgium for ion implantation of the 12 nm thick SOI wafers. Moreover, we thank R. Allenspach and W. Riess at IBM for valuable discussions and support, and U. Drechsler at IBM for the fabrication of cantilevers and assistance in clean-room processes.
The research leading to these results received funding from the European Union’s Seventh Framework Programme FP7/2007-2013, under grant agreement no. 318804 (SNM).
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