7/28/2019 Gate Insulator Pentoxide

1/4

CMOS Metal Replacement Gate Transistors usingTantalum Pentoxide Gate Insulator

A. Chatterjee, R.A . Chapman, K . Joyner, M . Otobe", S. Hattangady, M. Bevan, G.A.Brown, H. Y ang,Q. He, D. Rogers, S.J . Fang, R. K raft, A.L .P. Rotondaro, M. Terry, K. Brennan, S.-W.Aur, J .C. Hu,H-L Tsai, P. J ones, G. Wilk, M. Aoki*, M. Rodder, and I.-C. ChenSil icon T echnology Development, M S 3702 Texas Instruments, P.O.Box 6503 1 1, Dallas TX 75265.*Tsukuba Research and Development Center,Texas Instruments, Japan

AbstractThis paper reports a full CM OS process using acombination of a Ti" M etal Replacement Gate Transistordesign with a high dielectric constant gate insulator oftantalum pentoxide over thin remote plasma nitrided gateoxide. MOS devices with high gate capacitances equivalentto that for

7/28/2019 Gate Insulator Pentoxide

2/4

Fig. 9 illustrates that the use of Ta205 esults in lower J, fora given target value of Cgateat the probable value of supplyvoltage of 1SV .Figure I O shows a plot of EOlC,.,,,, versus t~,205 forNM OS capacitors. is the vacuum permittivity, C is themeasured capacitance per unit area of the gate insulator stackwith the device biased in accumulation, and t~,zo5 is thethickness of Ta2O5 measured by TEM . The symbols show theexperimental data, the solid curve shows the extrapolation totT(,zo5=0, and the dashed lines indicate the upper and lowerconfidence limit of this extrapolation based on estimates oferrors in the measured values of C and tTu205. The intercepton the vertical axis represents the ratio of thickness/dielectric-constant for the interfacial layer. The TEM of Figure 3 showsthat the thickness of the interfacial layer is 2 nm. This impliesthat the dielectric constant of the interfacial layer is 6.1. Suchan increase dielectric constant of the interfacial layer iscritical for achieving high gate capacitance and is consistentwith earlier observations [4] of increased effective dielectricconstant of thin oxides after remote plasma nitridation. Notethat if the dielectric constant of the interfacial l ayer were 3.9(pure SO2) , the fi lm thickness would have to be 1.3 nm, incontradiction with the TEM .Fig. 11 shows Jgate s. 1/T for Ta2OSand SO 2. The highactivation energies for Ta2O.j conduction are consistent withthe results of Matsuhasi [7]. T he gate current appears to be amixed conduction mechanism involving Poole-Frenkelemission in the Ta205.The thin oxide between the Ta2OS and the Si channelshould limit interface and trap density. The fast interfacedensity estimated from the charge pumping current (Fig 12) ishigh (2.8E1 /cm2) relative to pure SiOz (2E10/cm2) butsimilar to previous studies for Ta205 2]. Electron and holemobilities are shown in Fig. 13; pp is similar and pN s lowcompared to standard design W/TiN/SiO2 gate [8].Both NM OS and PM OS designs use Ti" gates,shallow drain extenders and angled pocket implants. The mid-gap workfunction of T IN raises V TN and VTpby -10.5Vlrelative to nC/p+poly gates. Thus, compensating As and BF2implants areused to lower V T ~nd VTp. Figures 14and 15show VT and subthreshold slopes versus Lgate. TheNM OSFET's show good characteristics down to Lgate=0.06pm, but the PM OS VT's are too low for Lgate0.1 pm.Figures 18 and 19 show the NM OS and PM OS IoFFversus ION characteristics. NM OSFET's have a reasonablyhigh I ON of 940uN pm at Iom=l nAJ pm for VDD =2.0 V , but

for vDD=1.5V IONs low (520pA/pm) because of high VTNvalues at short Lgate'sesulting from the large tilt-angle pocketimplant. The corresponding PM OS IoN7s re reasonable forCM OS inverter chains with fan-out=l show low standbycurrent, I(standby), combined with high effective capacitanceeven at V,, =2.0V. If S i02 were used then the gate dielectricfilm for such high capacitance would be so thin that the gatecurrent would cause a significant increase in I(standby). Fig.20 shows a plot of I(standby) and active current, I (active), at1 M Hz clock frequency versus delay time per inverter stagewith L,,, as the fundamental variable. The TazO5 thickness is6.5 nm for this data. This type of plot can be used todetermine a "maximum figure of merit" defined from theinverter delay of a chain with a gate length for which I(active)

= I(standby), (FOM [max]=l/delay at intersection) [9]. Theincrease in I (standby) at short delays (and gate lengths) i s dueto the rapid fall-off of V Tp with decreasing gate length. Theestimated gate length for equal standby and active currents is0.13 pm (limited by PM OS VT roll-off). T he delay times atthis intersection are shown in F ig, 21 as a function of Vcc.The results are similar for 5.3 nm and 6.5 nm Ta2O5.However, the 6.5nm thickness results in lower I(standby).

both v~,=1.5v (330 ufdum) and VDD=~.OV540pfdpm).

4. ConclusionsThe metal Replacement Gate transistor design permitsleaving the high-k gate insulator in its optimum state. Veryhigh gate capacitance can be obtained with low gate currentusing TazO5 even at 2.0V. Inverter chains with 2500 stageshave been demonstrated operating at 2.0V with acceptablestandby current. The Ta205 gate insulator process can beimproved to even lower gate currents [lo].[I ] J -L Autran, et af "Fabncation and Charactenzation of Si-MOSFETswith PECV D Amorphous T a20~ ate Insulator," IEEE Electron Dev Lett[2] I C K myalli, et al , "Stacked Gate Dielectncs with TaO for FutureCM OS Technologies." Symp VLSI T ech,pp 216-217, 1998[3] Y Momiyama, ef al . "Ultra-Thin Ta2Os Gate Insulator with TIN GateTechnology for 0 lum MOSFETs," pp 135-136, Symp VLSITech,1997[4] A Chatterjee,et a , "Sub- I00 nm Gate Length Metal Gate TransistorsFabncated by a Replacement Gate Process," IEDM Technical Digest ,pp821-824, 1997[5] H Y ang, et a l , " A Compansonof TIN Processes for CV D W/TiN GateElectrode on 3 nm Gate Oxide," IEDM Technical Digest, pp 459-462,1997(61 W W Lee, et a l , "Fabncation of 006 um Poly-Si Gate Using DUVLithography with a Designed Si,O,N, Film as an ARC and Hardmask, ",Symp VLSI Tech,pp. 13 1 132, 1997.[7 ] H M atsuhashi, et a l , "Optimum Electrode Materials for T al05Capacitors for High- and Low-TemperatureProcesses," J pn J Appf Phys,[8] J C Hu, ef a1 , Feasibil ity of W/TiN Metal-Gate for Conventional 013um CMOS T echnology and Beyond," IEDM Techni cal Digest, pp. 825-828,1997[9] R A Chapman, et a ,"A Standby Current Limited Performance Figureof M ent for Deep-Submicron CMOS," IEEE Transacfrons on ElectronDevi ces, vol. ED-44, pp. 1888-1895, 1997[ IO] S Kamiyama,et a , "Highly Reliable 2 5nm Ta205 Capacitor ProcessTechnology for 256 Mbit DRA MS," IEDM Technical Digest, pp 827-830,1991

ReferencesVOI 18, pp 447-449, 1997

VOI 33, pp 1293-1297, 1994

29.1.2778-IEDM 98

7/28/2019 Gate Insulator Pentoxide

3/4

Poly gate

Figure 1. Steps in the fabrication of a metal replacement gate transistor. a) after C M P planarization of polysili con disposable gate transistor with nitride sidewalls,b) after wet etch removal of polysil icon gate and gate oxide, c) after 1.5nm RPN-RTO then conformal deposition of Ta205 followed by an 800C RTA in N2, d)after deposition of T IN and 80nm W metal layers and pattendetch to form t-gate, e) after completion of the transistor with W-plug contacts to the sourcddrains.

Figure 2. TEM cross section of O.lpm long WlT iNReplacement T-gate with 5nm T a205 gate insulator.Nitride sidewalls before and after shallow drainextender shown. TiN layer is a compositeof CVD(conformal) and PVD (non-conformal) depositions.The larger thickness of PVD TiN at the top of theslot narrows the slot and contributes to the formationofavoid inside the tungsten gate.

Figure 3. H igh resolution TEM of gate insulator atthe bottom of a O.lpm gate. The Ta205 thickness isapproximately the same in large area capacitors, butthe TiN thickness is much larger in wide areacapacitors than seen in this TEM .

0.300.25

0.050.W

1816

E 14$ 1 2

10

1 48 2

-3 -2 -1 0 1 2 3Gale Voltage (V)0.15 0.20 0.25 0.30

Reticle Design Length (um)Figure 4. Polysilicon disposable gate l inewidth vs.length for the metal replacement gate after correctingfor the decrease in the slot width due to the 5.3nm n-type siliconand havethick conformal T a205 film. L inewidth controlalong a 0.05pm line is +/-0.015pm (3*0).

Figure, PMOS Gate Capacitancevs, Gate Voltagethicknesses. Both cases are with TiN M gates over

design length. shown is the gate with T a205 gate insulator of 5.3nm and 6.5nmcompensating

i

-3 -2 -1 0 1 2 3Figure 5. NM OS Gate Capacitance vs. Gate Voltagewith Ta205 gate insulator of 5.3nm, and 6.5nmthicknesses with pure Si 02 and nitrided-RTO(RPNO) NMOS from Ref. 4. All cases are withT i N M gates over p-type silicon. Note that c,ase with6.5 nm Ta205 has C,,,, similar to case with 2.5nm

Gate Voltage (V)

1E4 1?1E&4 E-01-1EM

-.$E

1EOIE 1E-051E-X5 1E-07

-3 -2 -1 0 1 2Voltage[VlFigure 8. PM OS Gate current vs. Gate Voltage withn-well for Ta205 cases of 5.3nm and 6.5nmthickness. Note that the gate currents are similar forNM OS and PM OS for Ta205. For 6.5nm Ta205,both NM OS and PM OS have lower gate currents fornegative vol tages than for positive voltages.RPNO. Dashed lines atupper left show extrapolationof capacitance values to -3V.

1 +w-1E+01p 1E+OO0 1E-01$1 E-02 1E-03

1E-030 1E-04E 1E-05

1E-060 1E-07

1E-091E-10

* +z 1E-OB

10 11 12 13 14 15 16 17 18GateCqMcRmcen Accumulation at -1.WfFlum2)

GateVolt;ige wth Figure9 The use of Ta205 gate insulator results inp"yP substrate for Ta205 cases Of 5.3nm and higher values of capacitance for the same value of6.5nm thicknesses. Note 6.5nm Ta205 case has gate leakage in accumulation compared to eitherusing 2.5nm nitrided-RTQ (samecapacitance).

-3 -2 -1 0 1 2 3Voltage [VI6. Gatecurrent

lower gate current than Ref. case pure Si02 ornitrided sil icon dioxide gate insulators

29.1.3IEDM 98-779

7/28/2019 Gate Insulator Pentoxide

4/4

0 1 2 3 4 5 6 7Thicknessof la 205 Layer (nm)Figure 10.E O / C ~ ~s thickness of TazOS whereC , dccis gate capacitance of the NMOS in accumulationDashed lines show confidence l imts in extrapolationfrom TazOSdata. The dielectnc constant of TazOSobtained from the slope is 29. The intercept on thevertical axis is r/k where f is the interfacial layerthickness, k is its dielectnc constant Using r=2nmfrom TEM (Fig.3), k=6 1

w-E Dependence 1 Gate Current on Temperature.

L - A - L '

- - - - - ~ ~0800 01 0 2 0 3 0 4 0 5

Replacement Gate Length (um]Figure 14. NM OS and PMOS VT's vs. replacementgate length. NM OS works well to 0.06um1. Shortergate lengths fail because poly-Si linewidth varies(30=0.015um)along the width of the transistor.

0.0000 0.1000 0.20M 0.3000 0.40CiI 0.5000ReplacementGate Length (urn)

Figure 15. Subthreshold slope vs. replacernent gatelength for NM OS &PMOS.\1E-03 -.$ wrriNlsi02aIna iE-07 T ,1 0 1 5 20 2 5 3 0 3 5 4 0IOOOTT [K']Figure 1 1. Gate leakage asa function of temperaturecompanng NM OS and PMOS in accumulation forTa205 to Si 02 gate insulator. The large activationenergies for Ta205 suggest a mxed conductionmechanism including Poole-Frenkel emssion.1 E M13

0 1E03sm-U

1EWm1

1E 052 5 2 -15 -1 0 5 0 0 5

BaseLavel VGL (V) 1E03Figure 12 Fast interface state densityforTa205 and s i ~ 0 4pure Si02 compared to prior work Ref.-2. Z I E 0 5

E 1E066 1E074 1E08g 1E09

L

350-T 3w0-g200 1E 10

2 1w0 ag 150 81E-11

1E 12d m

000 0 2 0 4 0 6 0 8 10 12 1 4

EthctlvoVartisal Field(MVlcm)Figure 13. Hole mobility is sirmlar to that reportedin Ref.-8, but electron mobility is smaller.

14001200

5'e 400a200

0

lE+OO-E1E-0221E-04

rI11E-06 21E-08 Ea1E-10

21E-12 2a1E-14 In

-0.0 0.5 1.0 1.5 2.0 2.5Drain Voltage (Volts)

Figure 16. NMOS drive characteristics and substratecurrent for typical strong transistor.

0 0.5 1 1.5Gate Voltage (Volts)Figure 17. Typical NM OS strong transistorsubthreshold current and gate current. Thecharacteristics for PM OS transistors are similarlygood, but at longer gate lengths.

1E.06E 1E.07$1 E.08E 1E.0951 E 10g i E . i lOiE.12

1E.131E.14

I

0 200 4W 600 800 1000 1200Drive Current (uAlum)Figure 18. NMOS off-current vs. Drive Current for1.5V and 2.0V.

0 000

- 0 , ,1 E 1 4 1 ~ I 1 I I ! I0 200 400 600 800Drive Current (uAlum)

Figure 19. PM OS off-current vs. drive current forVD=.SV and 2.0V.

20 25 30 35 40 45 50 55 60Delay per Stage (ps)

Figure 20. Inverter chain standby and active currentsvs. delay time. Intersection at 27 ps isa "maximumFOMI" quality factor [Ref. 91 when standby=activecurrent. At long gate lengths (long delays), thestandlby current is limited by gate current.E070- i0:;0

0

prz92

1E-11 #1E-124

1o 1.5 2.0 2.5Supply Vol tage (Vol ts)Figure 21. Inverter chain FOM (max) and standbycurrent vs. supply voltage. Use of 6.5nm Ta205results in lower standby currentforsame speed.

29.1.4780-IEDM 98