Gate Insulator Effects on the ElectricalPerformance of ZnO Thin Film Transistor on a
Polyethersulphone Substrate
Jae-Kyu Lee and Duck-Kyun Choi∗
Department of Materials Science and Engineering, Hanyang University, Seoul 133-791, Korea
Low temperature processing for fabrication of transistor backplane is a cost effective solution whilefabrication on a flexible substrate offers a new opportunity in display business. Combination ofboth merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexiblePolyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selectionand design of compatible gate insulator is another important issue to improve the electrical proper-ties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx . TheSiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effectiveto enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employ-ing SiNx /SiO2 stacked gate exhibited the best performance. The device parameters of interest areextracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swingare 107, 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.
Keywords: ZnO, AOS TFT, Flexible, Transparent, PES.
1. INTRODUCTION
Hydrogenated amorphous silicon has been extensivelyinvestigated as an active layer for TFT for flexible elec-tronics such as flexible solar cell and flexible TFTs.1–5
However, their performance is limited by the low mobil-ity and degradation on exposing to air and light. In addi-tion, the Si based devices are of less interest due to theiropaque nature for the transparent electronics application.For such purpose, ZnO is attractive and promising due toits transparent nature in the visible range of light spec-trum. It exhibits band gap about 3.37 eV.6�7 Besides, oneof the important factors that make ZnO a competitive can-didate for transparent optoelectronic device is the easinessin growing polycrystalline film at room temperature.As far as ZnO based devices are concerned, most of
the works has been focused on improving the qualityof channel material. The use of single crystalline ZnOhas been reported by few authors.8�9 While high perfor-mance ZnO or doped ZnO TFTs with high field effectmobility ranging 1∼80 cm2/Vs and high on/off ratio rang-ing 105∼107 have been reported by many authors.10�11
There have been few studies on low threshold voltage and
∗Author to whom correspondence should be addressed.
low operating voltage employing high-k dielectrics as agate insulator.12�13 On the basis of existing literature andconsidering the transparency and low temperature growthcapability, ZnO is still an outstanding candidate for flexi-ble and transparent electronics.Recently, it has been demonstrated that zinc tin oxide
(ZTO) TFT exhibits mobility of 14 cm2/Vs and on/offcurrent ratio of 106 on a flexible polyimide substrate.14�15
On the other hand, the mobility of 7 cm2/Vs and on/offcurrent ratio of 103 with indium gallium zinc oxide (IGZO)active layer and Y2O3 gate oxide on the polyethyleneterephthalate substrate has been reported.16 Thus, it isemphasized that the fabrication of flexible TFT is rathera compromise between processing and device parameters.The additional factor that enters into this picture is the coef-ficient of thermal expansion. The difference between thecoefficient of thermal expansion between oxide and organicsubstrate leads to damage and degradation of devices.Therefore, the establishment of fabrication process for theflexible electronics with better device parameters is a chal-lenging task. In this investigation, attempts have been madeto demonstrate the ZnO based TFT on a flexible PES sub-strate. Furthermore, process optimization of ZnO channellayer and gate insulator design have been carried out tosecure reliable performance on the flexible substrate.
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Gate Insulator Effects on the Electrical Performance of ZnO Thin Film Transistor on a PES Substrate Lee and Choi
Fig. 1. Schematic cross section of a ZnO TFT.
2. EXPERIMENTAL DETAILS
Polyethersulfone film was preheated at 120 �C for an hourin air ambient to minimize the shrinkage that might occurduring subsequent processing. 50 nm thick SiO2 barrierlayer was deposited by PECVD at 140 �C on top andbottom surfaces of substrate, which was followed by adeposition of 100 nm thick Al bottom gate electrode usingevaporator at room temperature. The SiO2 gate insulatorlayer was deposited at 140 �C using PECVD and an activelayer of 100 nm thick ZnO was grown at room tempera-ture using RF magnetron sputter at powers from 20 W to70 W and a working pressure about 20 mTorr. The drainand source contacts were obtained by depositing 100 nmthick Al using shadow mask. The channel length and widthfor the stated process were 50 and 2000 �m, respectively.The schematic of cross sectional view of a TFT device isprovided in Figure 1.The surface morphology of ZnO film was analyzed
using AFM while the crystallinity of ZnO was character-ized using XRD. The electrical performance of gate oxideand the device characteristics were evaluated using semi-conductor analyzer, HP5279B.
3. RESULTS AND DISCUSSION
The XRD patterns for ZnO thin films deposited on a PESsubstrate with various RF powers are provided in Figure 2.
Fig. 2. XRD patterns for ZnO films deposited at various RF powers of(a) 20 W, (b) 30 W, (c) 40 W, (d) 50 W, (e) 60 W and (f) 70 W.
Fig. 3. Microstructure for the ZnO film on PES deposited at 20 Win Ar.
All films exhibit (002) peak near 34�. There is a tendencyin increase of crystallinity with RF power. However, it isalso observed that the film deposited at the power of 40 Wor beyond resulted in micro-cracks. The difference in ther-mal expansion between ZnO and PES originated from thetemperature rise of substrate during deposition is likelyto cause such cracks. In order to preserve crack free filmwhen preparing ZnO thin film, judicious control in depo-sition power is suggested.It has been noticed that the crystallinity and the grain
size are affected by the gas ratio in deposition. The mor-phology of ZnO surface on PES deposited in Ar at RFpower of 20 W was examined with FE-SEM and is shownin Figure 3.As explained earlier, the design of a gate insulator (GI)
compatible with ZnO active layer is another concern tosecure good transistor performance. In this study, SiO2,SiNx, and SiNx/SiO2 gate insulator structures have beeninvestigated. The thickness of all the insulators was sameand fixed to 200 nm. The MIM structure of Pt/GI/Pt wasemployed to evaluate the leakage current behavior for threedifferent gate insulators. It turned out that the minimumleakage current density was observed for SiNx/SiO2. Theperformance of three gate insulators is shown in Figure 4.
Fig. 4. Leakage current density for three different MIM capacitors.
5860 J. Nanosci. Nanotechnol. 12, 5859–5863, 2012
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Lee and Choi Gate Insulator Effects on the Electrical Performance of ZnO Thin Film Transistor on a PES Substrate
In order to understand the leakage current mechanism,the leakage currents for different specimen were drawnagain in various ways and are given in Figures 5(a)–(c).The leakage current density for investigated structure iscomprised of space charge contribution, Frankel–Pooleand Fowler–Nordheim tunneling through GI. At the lowfield in the SiNx and SiNx/SiO2 gate insulators, spacecharge contribution predominates. On the other hand,at higher field, tunneling mechanism predominates. Fromthe figure, the current density for MIM containing SiNx
gate insulator sharply increases and can be characterized
(a)
(b)
(c)
Fig. 5. Various plots of leakage current for MIM structures withthree different gate insulators of SiO2, SiNx and SiO2/SiNx showing(a) J (Leakage current density) −V 2, (b) Fowler–Nordheim tunnelingmechanism and (c) Frankel–Poole mechanism.
by J∝ V 2. The decay in the leakage current density withfield can also be attributed to the formation of spacecharges. Same behavior is also visible for SiNx/SiO2 stackwhile the MIM with SiO2 exhibits classical tunnelingbehavior. The SiNx insulator has sources of creating trapat the interface and in the bulk as well. The equilibriumdefects in the bulk are mainly responsible for the formationof space charges. Moreover, the existence of defects leadsto Frankel–Poole mechanism contribution to the leakagecurrent density. Finally, at high field, tunneling mechanismgoverns the leakage current.During the device fabrication process, any crack leads
to a serious degradation and poor device performance. Thechoice of higher RF power during deposition leads to thecrack formation and it apparently propagates into channellayer. In this investigation, in order to avoid the crack for-mation and to retain the mechanical stability of substrate,50 nm thick SiO2 buffer layer has been deposited usingPECVD. The degree of deformation after the completionof device fabrication with buffer layer and without bufferlayer is compared in Figure 6. It can be seen that the depo-sition of buffer layer enhances the mechanical stability ofthe substrate. The polymer-ceramic interface formation at
Fig. 6. Degree of deformation with and without buffer layer.
J. Nanosci. Nanotechnol. 12, 5859–5863, 2012 5861
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Gate Insulator Effects on the Electrical Performance of ZnO Thin Film Transistor on a PES Substrate Lee and Choi
Fig. 7. Transfer curves for ZnO-TFTs with three different gateinsulators.
elevated temperature seems to improve the thermal andmechanical stability of substrate.Thus, the substrate using buffer layer of 50 nm SiO2 has
been used for the processing of devices. The optimal RFpower, buffer layer deposited substrate and three differentgate insulators have been chosen to investigate the reliabil-ity of flexible backplane for the display and to determinethe performance of ZnO-TFTs. The transfer curves for theZnO-TFTs with SiO2, SiNx and SiNx/SiO2 are presentedin Figure 7. The device parameters of interest for ZnO-TFT are channel mobility, threshold voltage, subthresholdswing and on/off current ratio and those for ZnO-TFTswith three different gate insulators are listed in Table I.It appears that the channel mobility of the ZnO TFT
with SiO2 gate insulator is the highest one. However, thatnumber is overestimated and not meaningful because ofthe relatively high leakage current. In fact, the SiNx/SiO2
stacked gate shows the highest and meaningful value. Thethreshold voltage for ZnO-TFT exhibits a significant vari-ation as the gate insulator changes from SiO2 to SiNx orstacked SiNx/SiO2. Since the gate electrode for all threedevices is same, the source for changing threshold voltageappears to be associated with the interfacial traps. Substan-tial amount of traps are existing at the interface createdby equilibrium defect in gate insulator employing SiNx.The subthreshold swing for the three devices also agreeswith the conclusion. It shows decreasing trend as the gateinsulator changes from SiO2 to SiNx/SiO2 stack. Among
Table I. Device parameters for the ZnO-TFT with three different gateinsulators.
Gate insulator On/off ratio SS (V/dec.) Vth (V) �FE (cm2/Vs)
the devices fabricated, one with SiNx/SiO2 stacked gateexhibits the best performance.
4. CONCLUSIONS
ZnO as an attractive alternative for transparent flexibleelectronic has been investigated. The process optimizationof ZnO deposition on the flexible substrate has been estab-lished. The lower RF power, in this case 20 W has beenobserved to be the best choice for the ZnO deposition.Furthermore, the deposition of 50 nm thick SiO2 bufferlayer on both sides of the flexible substrate turned outto improve the mechanical and thermal stability. The gateleakage current has been observed to be lowest for thecase of SiNx/SiO2 stack structure which concludes a stackconfiguration can be a solution for gate insulator. Usingthe optimal parameter, the ZnO-TFT on the polymer (PES)substrate has been successfully fabricated and the deviceparameters have been evaluated. The highest field effectmobility of 22 cm2/Vs has been observed for the devicewith SiNx/SiO2 stack gate. A reliable process for the fab-rication of TFT on flexible substrate and improved deviceparameter, low temperature fabrication of ZnO-TFT hasbeen established.
Acknowledgments: This work was supported by aKorea Science and Engineering Foundation grant fundedby the Ministry of Education, Science, and Technol-ogy (No. R11-2005-048-00000-0, SRC/ERC Program,CMPS) and the National Research Foundation of Korea(NRF) grant funded by the Korea government (MEST)(No. 2010-0014618).
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Received: 30 July 2011. Accepted: 16 February 2012.
