Influence of BJT Transit Frequency MOSFET Parameters on … · 2019. 8. 1. · BiCMOS is the...

VLSI DESIGN1999, Vol. 9, No. 2, pp. 203-211Reprints available directly from the publisherPhotocopying permitted by license only

(C) 1999 OPA (Overseas Publishers Association) N.V.Published by license under

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Printed in Malaysia.

Influence of BJT Transit Frequency Limit Relationto MOSFET Parameters on the Switching Speed

of BiCMOS Digital Circuits

A. SRIVASTAVA*

Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803-5901

(Received 25 March 1997; In finalform 4 December 1997)

The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFETparameters (L, Vth) to design BiCMOS digital circuits. The fTi relation is used inconjunction with the established BiCMOS gate delay models. It is shown that theminimum delay BiCMOS circuits driving the large capacitive load, can be designed atthe transit frequency limit with the reduced BJT AREA factor. The time delaycalculations are presented for a typical BiCMOS circuit and comparison is made withthe results simulated using SPICE.

Keywords: BiCMOS, digital circuit design, VLSI design, gate delays, analysis, simulation

INTRODUCTION

BiCMOS is the technology combining the lowpower of CMOS with the high-speed and drivecapability of bipolar for realizing high perfor-mance digital circuits [1-3]. Over the yearsBiCMOS integrated circuits have been well char-acterized for high-speed digital logic applications[4-16]. The circuit delay time model of theBiCMOS has been extensively studied and as aperformance measure of the BiCMOS technology[12]. Many closed-form analytical expressions for

the gate delay have been derived through thephysical and electrical modeling and are availablein the literature [5, 9, 10-13].

Greeneich and McLaughlin [5] have obtainedclosed-form analytical expressions for the gatedelay and have shown its dependence on deviceand circuit parameters. The analysis does notinclude high-level injection effects in the bipolartransistor model. For the devices used, high-levelinjection effects are not a major consideration intransient response studies. Rosseel and Dutton [6]have studied the influence of device parameters on

* Tel.: (225) 388-5622; Fax: (225) 388-5200; e-mail: [email protected]

203

204 A. SRIVASTAVA

the switching speed of a BiCMOS buffer circuit.The analysis examines the high-level injectioneffects through the parameters Ikv, the upper kneecurrent in bipolar transistor, and shows to stronglyinfluence the performance. The analysis alsoexamines the influence of different emitter sizeson the delay time and it is shown that for a givenarea, the delay is minimum for one optimal sizeratio for the MOS and bipolar transistors. Rofailand Elmasry [11] have derived analytical andnumerical BiCMOS gate delay models to char-acterize BiCMOS structures using long and shortchannel devices. Their numerical model includehigh-current effects and other second order effects.Raje et al. [12] have provided a piecewise delayexpression of the BiCMOS gate delay model whichtakes into account high-current effects in bipolartransistor, short-channel effects in MOSFET andparasitic capacitances at the base and output.Fang et al. [10] have proposed a BiCMOS overalldelay-optimization scheme. Under this scheme, thedelay is minimized when the maximum collectorcurrent is equal to the onset current of high currenteffects of bipolar transistors. This indicates thatthe bipolar transistor in BiCMOS circuits operatesat a collector current density below the high-current region for speed-optimized BiCMOScircuits. It is also shown that BiCMOS circuitscan keep the speed advantage over CMOS circuitsdown to submicron dimensions under constantload conditions.A comparison of these papers shows that

different analytical solutions have been obtainedthrough the use of different assumptions. None ofthese work seems to include and provide a propercorrelation between the MOS and bipolar transis-tors dimensions in gate delay modeling and delayminimization in BiCMOS circuits. Rothermel andHosticka [7] have shown that there is a transitfrequency below which the bipolar transistor doesnot contribute to the speed improvement, andhence the digital BiCMOS design techniques donot offer any speed advantage over CMOS. In thiswork, we have further explored the usefulness ofthe relationship between the transit frequency limit

of the bipolar transistor and MOSFET parameterson BiCMOS gate delay models.

THEORY

In the following, we will describe the relationbetween BJT transit frequency limit and MOSFETparameters, and BiCMOS gate delay models.

BJT Transit Frequency Relation to MOSFETParameters

In order to develop a realistic BiCMOS speedimprovement model, consider a simple BiCMOSbuffer circuit which includes an internal logic asshown in Figure 1. The buffer circuit in the Figure

drives a capacitive load, CL. Figure providesthe necessary parasitics which are to be included indeveloping a relation between the bipolar andMOS transistors parameters. Figure 2 shows theequivalent circuit for the buffer part of the Figurewhere the transistor acts as a digital switching

device. In Figure 2, the MOS transistor providesthe input current source and bipolar transistorsimulates the output stage of the buffer. We nowassume that bipolar or MOS transistor charge anddischarge the load capacitance, CL, by the sameoutput current (louT). The input current is alsoassumed to be constant during switching. Thus,the time needed to build an active charge in base orchannel region of bipolar and MOS transistors canbe calculated from the input charge. Now for thesame charging and discharging current, bothtransistors will have the same speed under identicalinput conditions, and BiCMOS drivers con-structed with them will have the same delay times.

In BiCMOS circuits, if the bipolar transistor hasto switch faster than the MOS transistor, chargebuild-up in the base of bipolar transistor shouldexceed the charge build-up in the channel region ofthe MOS transistor. This sets a lower limit on thebipolar transistor to perform better than the MOStransistor. The limit is described by the transitfrequency limit, fTL relation and is of the following

BiCMOS SWITCHING SPEED 205

INTERNALLOGIC CIRCUIT

BiCMOS BUFFER CIRCUIT

VDDO

M1

M3

FIGURE BiCMOS buffer with internal circuit.

VDD

lOUT

) Charging

lOUT

IOSFET Discharging

BJT

IIN

GND

CL

FIGURE 2 Transistor as a digital switch.

O

CL

o Votrr

form [7]

fTL--#oN(VDD- Vth)

323 71"LEFF(LEFF -[- 6Lov) ( VDD+ LEFFEcm(1)

where #ON is the mobility in low electrical field,Lov the overlap length, Vth the threshold voltage,Ecm the critical electric field, and VDD the powersupply voltage. The transit frequency limit, fTL isrelated to MOS transistor parameters (LEvy, Lovand Vth) and supply voltage VDD. For a BiCMOS

206 A. SRIVASTAVA

circuit to perform better over the CMOS circuit,the transit frequencyfT of the BJT should be equalto or greater than the transit frequency limit, fTi.Equation (1) forfTL can be used to design BJT andMOSFET more realistically in a BiCMOS circuitfor the optimum delay.

BiCMOS Delay Models

In Figure 1, transistors M1 and M3 provide basecurrent to transistors Q1 and Q2, respectively.Transistors M2 and M4 remove the base chargefrom the bipolar transistor during dischargeprocess in switching transient. The buffer designprovides identical pull-up and pull-down response.The delay time model can be developed byapplying a step voltage at the input of the buffercircuit. It can be followed from Figure that largerthe transistor M1, the higher is the base andemitter currents of transistor Q1 which results inshorter gate delay. This condition may lead to BJTentering into the high-current region where Kirkeffect [17, 18] takes place. In practical situation,the buffer circuit is driven by an internal CMOSlogic circuit as shown in the Figure 1. Now, if thetransistor M1 is made larger in size by increasingits width, the gate capacitance of M1 will increase.The gate capacitance of M1 acts as a load to theinternal logic circuit (inverter in the present design)and will reduce its speed. Thus, in order to achievethe shortest delay of the BiGMOS circuit of Figure1, it may not be necessary to drive BJT(Q) in thehigh-current region during the pull-up transient.BiCMOS gate delay is composed of pull-up

delay due to charging of load capacitance CLthrough the combination of M1-Q1 transistors,and pull-down delay due to discharging of Cthrough the combination of M3-Q2 transistors. Ithas been shown in Ref. [10] that pull-up and pull-down transient response of the BiCMOS buffercircuit can be made equal by making BJTs Q1 andQ2 identical and keeping widths of M1 and M3same. Thus, one can describe the switchingbehavior of a BiCMOS circuit either throughpull-up or pull-down delay models. In the present

work, we will study the switching responsethrough the pull-up delay models.

It was stated earlier that BiCMOS buffer circuitoperates below the current level (maximum outputcurrent) at which high-current effects set-in whenintegrated with the internal CMOS logic. Themaximum output current can be approximated tobe equal to upper knee current IkF of the BJT asdone by earlier workers [10] for an optimum delaycalculation. It was also stated in this work that theBiCMOS circuit can be made to perform betterover the CMOS circuit if transistors are designedto operate at the transit frequency limit fVLdescribed by the Eq. (1). The transit frequencylimit fw can also be assumed to be the frequencyat which high-current effects set-in. Thus, opti-mum gate delay for the BiCMOS circuit can beobtained at the fT at which it can be approxi-mated that the maximum output current is equalto the knee current/kW. Earlier delay models [5, 10]can be suitably modified to include the transitfrequency relation of Eq. (1) and its dependence onMOSFET parameters. The operation of theBiCMOS circuit can be divided into three timeintervals as shown in the Figure 3.

FIGURE 3 Three time delay intervals in a BiCMOS circuitshown on output voltage waveforms. Note: Output currentwaveform is also included to show the maximum collectorcurrent.


(i) The time interval tl is defined as the initialdelay time. The MOSFET (M1) turns-on andBJT (Q) begins to conduct until its base-emitter voltage VBE reaches aboutVBE(on)_0.7V. At the end of the timeinterval tl, the MOSFET (Ma) still remainsin saturation and the BJT (Q) turns-on. Theinitial time delay can be obtained from ananalysis of the equivalent circuit during thetime interval t and is given by [5]

V. (on)Reh(CE / Cc) VDD --I Vth,p[ CE + Cc(2)

where

(ii)

2LRch (3)WI#pCox(VDD- Vth,PI)

Rch is the equivalent dc channel resistance ofthe MOSFET (M1). Cz, Co RB and Rc are theemitter and collector capacitances, RB and Rcare the base and collector resistances, respec-tively of BJT (Q). Cz, Cc, RB and Rc areassumed to be constant. Ccs is the collector-substrate capacitance of Qz and is assumed tobe constant. W1 and L are the channelwidth and length of the transistor M1. #p andVth,P are the hole carrier mobility and thresh-old voltage. In a typical BiCMOS circuit,Rc < Rch which makes the second term inEq. (2) negligible.The delay time t2 is the time interval duringwhich BJT (Q) is on and the MOSFET (M)is still in saturation. It is to be mentioned thatM remains in saturation provided its thresh-old voltage [Vth,P > VBE(On) 0.7 V of Q1.The time delay can be obtained from ananalysis of the equivalent circuit during thetime interval t2 and is given by [5]

t2--[2RchC7-yr{]VIh’pI--VBE(n)}] 1/2VDD- Vth,PI (4)where C[ is the equivalent load capacitance,7- is the equivalent forward transit time of the

BiCMOS circuit. C[ and r are given byCL / CCSCL

(iii)

"r. "rT + RcCc (6)where 7"T (1/(27rfT)). fT is the cut-off fre-quency or transit frequency of the transistor.Cz is neglected since Vz(on) nearly remainsconstant and equals to 0.7 V, (Vnz - 0.7 V).The delay time t3 begins when VOUT--Vth,PI--V E(on) and M enters the linearregion, and ends at the point where theoutput reaches the switching threshold

Vs 2.5V. M1 can be substituted by anequivalent channel resistance Rch in theequivalent circuit during the time interval t3which is of the form [5]

VDD- VB(on) }t3 - Tcos- 2(VDD gth,P[) (7)where

and

r (8)1- ro2

r5 v/(Rch / RB)C7"r (9)Cc (0)

/: 3F C L

It should be noted that for a typical device andcircuit parameters To

208 A. SRIVASTAVA

collector current at the boundary between t2 andt3. This is due to a constant term (C) which is setto 0 for mathematical simplicity in the derivationof Eq. (7) [5]. However, it was suggested in Ref.[10] that for high-speed BiCMOS circuits, Vth,plcan be approximated to be equal to VBE(On)-0.7 V. Thus, it can be assumed that the MOSFET(M) operates in the linear region during the timeinterval t2 without causing a significant error. Itimplies that t2 0 and the time interval t3 can thenbe described in the following form [10]

t3- Ttan_ (2/3-)T (12)Equation (12) can be further simplified to the form

t3 TM " T-- 2 (13)for 2/7- >> T for typical devices.The delay time to is now the sum of time

intervals t and t3 since t 0, described by Eqs.(1) and (13), respectively. The maximum outputcurrent It(max) of Q at the end of the timeinterval t3 can then be described by the equation ofthe form [10]

{goD--gag(on)}Ic(max) --CL Tsin .exp

4/3-for PFT-T >> T

(14)

The maximum output current described by the Eq.(14) can be assumed to be approximately equal tothe knee current Ikv at which high-current effectsstart. Equation (14) for It(max) in combinationwith the Eq. (1) for fTL can be used to designoptimum delay BiCMOS circuits. It should benoted that fTL influences time delays through thetime delay interval equations for t2 and t3.

RESULTS AND DISCUSSION

Figure 4(a) shows the dependence of BJT transittime on the MOSFET channel length, obtainedfrom Eq. (1) for a BiCMOS circuit shown inFigure 1. The typical MOSFET parameters used inthe calculation are #ON 5 X 102/V-sec, Vth,N0.8V, LOV-----0.13LEFF, Ecm 7x 104V/cm andVDD 5V. The corresponding transit frequencylimit dependence on the channel length is shown inthe Figure 4(b). Figure 4 can be used to obtaindimensions of BJTs and MOSFETs in a BiCMOScircuit designed to operate at the minimum delay.Figure 5 shows the simulated output voltage

10

"I0

10-1O.OOe+O

(a)1.00e-4 2.00e-4 3.00e-4

Channel Length,

8.00e+9

6.00e+9

4.00e+9

2.00e+9

O.OOe+O0.00o+0 1.00e-4 2. OOe-4 3.00e-4

(b) Channel Length,

FIGURE 4 (a): BJT transit time dependence on MOSFETchannel length; (b): BJT transit frequency limit dependence onchannel length.


5.0

4.0

3.0

2.0

1.0

0.00.00

FIGURE 5

1-V(4), Ref.101-V(2), Ref.10

& 3-V(4)

-’-"- 3-V(2)2-V(2)2-V(4)

0.50 1.00 1.50 2.00

Time (t), ns

Voltage response at nodes 4 and 2, respectively obtained from SPICE3.

response of the BiCMOS buffer with the internalcircuit. The step function input voltage whichswitches from 0 to 5 V is applied at a node 6. Thecircuit is simulated using SPICE3 (LEVEL 2)MOSFET model parameters. BJT and MOSFETmodel parameters are taken from the Ref. [10].The load capacitance, CL is 5 pf. In Figure 5, V(4)and V(2) are the voltage responses at nodes (4) and(2), respectively. In a group of V(4) plots l-V(4),Ref. [10] plot shows the output voltage responsecorresponding to device dimensions of Ref. [10] forthe gate delay. The corresponding input voltageresponse at a node 2 is shown by 1-V(2), Ref. [10]plot. The MOSFET channel length is 2t.tm andBJT transit time is 20 ps for this set of curves. Theplots 2-V(4) and 3-V(4) show the output voltageresponse for L- 1.0 and 0.51am, respectively.Transit time (-v) parameters are obtained fromthe Figure 4(a). The corresponding input voltageresponse at a node 2 is shown by 2-V(2) and 3-V(2)

curves. The plots l-V(4), Ref. [10], 2-V(4) and 3-V(4) are obtained using the AREA factor-14, 14and 8 and -T 20, 55 and 20 ps, respectively forthe BJT design. Figure 5 shows that the BiCMOSgate delay is further reduced from the value that isobtained for the optimized design described inRef. [10].

Figure 6 compares the output current responsecorresponding to L 2 and 0.5 l.tm, respectively.The current response corresponding to L lam isnot included in this figure. The plot 1-I, Ref. [10]shows the output (collector) current variation forthe BiCMOS circuit design parameters of the Ref.[10]. The output current peaks at approximately30mA and the AREA factor is 14. This plot iscompared with the plot for 2-I for L 0.5 lm,and -T 20 ps obtained from the Figure 4(a). TheAREA factor is 8 for this curve which providesnearly the same peak current as in the 1-I, Ref.[10] curve. Figure 6 also shows that the output

210 A. SRIVASTAVA

0.03

0.02

0.01

O

O 0.00

-0.010.00e+0

1-1C, Ref. 10

2-1C

1.00e-9 2.00e-9

Time (t), s

FIGURE 6 Output current (collector current) response.

TABLE BiCMOS delay time

L Ic(max) t t2 t3 tdlam (mA) (ns) (ns) (ns) (ns)

td(t2 o)(ns) (ns)

BJT CLAREA factor (pF)

0.5 28 0.052 0.085 0.519 0.656 0.6742.0 30 0.092 0.090 0.504 0.686 0.742

0.60 8 50.70 14 5

current peaks approximately at a half the timeneeded to reach the switching threshold Vs 2.5 Vin plot 1-Ic Ref. [10]. Thus, we can conclude fromFigures 5 and 6 that the Eq. (1) gives a lower gatedelay with the reduced BJT AREA factor underthe same load condition. This is further shown inthe Table I where the time intervals tl, t2, t3 andthe total delay time td for the BiCMOS buffer stageare summarized. In Table I, delay time results areincluded for L 0.5 lam without using the Eq. (1)[10]. SPICE3 (LEVEL 2) simulation results arealso shown for comparison. In the Table I, resultsobtained from the use of the transit frequencyrelation (Eq. 1) for L 0.51am suggest that aminimum delay BiCMOS circuit can be designed

even with the reduced BJT AREA factor. Thepresented design approach provides nearly thesame maximum output current (Fig. 6, plot 2-Ic) todrive the same load (CL 5 pF) as in L 21mbased design.

CONCLUSION

The BJT transit frequency limit dependence onMOSFET parameters and its direct relationship toBiCMOS delay time intervals give a minimumdelay. The minimum delay is obtained withreduced BJT AREA factor and large maximumoutput current which is approximately to be the


upper knee current. The high-current effects whichstart at the knee current, occur at the end of timeinterval t3 or the delay time td. Since the BiCMOScircuit operates below the knee current, highcurrent effects such as degradation in current gainand base transit time are not included in the timedelay analysis. This approach holds good foroutput voltage to rise to its switching thresholdwhich is normally the case. The results andanalysis of the present work suggest that theminimum delay BiCMOS digital circuits could bedesigned using BJT transit frequency limit criteriain relation to MOSFET parameters.

Acknowledgement

Author is grateful to the reviewers for theirvaluable comments and suggestions.

References

[10] Fang, W., Brunnschweiler, A. and Ashburn, P. (1992)."An accurate analytical BiCMOS delay expression and itsapplication to optimizing high-speed BiCMOS circuits,"IEEE J. Solid-State Circuits, 27(2), 191-202.

[11] Rofail, S. S. and Elmasry, M. I. (1992). "Analytical andnumerical analysis of the delay time of BiCMOSstructures," IEEE J. Solid-State Circuits, 27(5), 834-839.

[12] Raje, P. A., Saraswat, K. C. and Cham, K. M. (1992)."Accurate delay models for digital BiCMOS," IEEETrans. Electron Devices, 39(6), 1456-1464.

[13] Lai, P. T. and Cheng, Y. C. (1994). "A closed-form delayexpression for digital BiCMOS circuits with high-injectioneffects," IEEE J. Solid-State Circuits, 29(5), 640-643.

[14] Rafail, S. S. (1994). "Low-voltage, low-power BiCMOSdigital circuits," IEEE J. Solid-State Circuits, 29(5), 572-579.

[15] Kuroda, T. and Matsuo, K. (1994). "Analysis andoptimization of BiCMOS gate circuits," IEEE J. Solid-State Circuits, 29(5), 564-571.

[16] Chiang, C. H. and Kuo, J. B. (1995). "An analyticaltransient model for a 1.5 V BiCMOS dynamic logic circuitfor low-voltage deep submicrometer BiCMOS VLSI,"IEEE Trans. Electron Devices, 42(3), 549-554.

[17] Kirk, C. T. (1962). "A theory of transistor cutofffrequency 0ca:) falloff at high current densities," IRETrans. Electron Devices, ED-9, 164-174.

[18] Feng, W. (1990). "Accurate analytical delay expressionsfor ECL and CML circuits and their applications tooptimizing high-speed bipolar circuits," IEEE J. Solid-State Circuits, 25(2), 572-583.

[1] Alvarez, A. R. (Ed.) (1989). BiCMOS Technology andApplications, Kluwer Academic Publications, Boston,MA.

[2] Buchanan, J. E. (1991). BiCMOS/CMOS Systems Design,McGraw-Hill, NY.

[3] Kang, S. M. and Leblebici, Y. (1996). CMOS DigitalIntegrated Circuits." Analysis and Design, McGraw-Hill,NY.

[4] De Los Santos, H. J. and Hoefltinger, B. (1986)."Optimization and scaling of CMOS-bipolar drivers forVLSI interconnects," IEEE Trans. Electron Devices, ED-33(11), 1722-1730.

[5] Greeneich, E. W. and McLaughlin, K. L. (1988)."Analysis and characterization of BiCMOS for high-speeddigital logic," IEEE J. Solid-State Circuits, 23(2), 558-565.

[6] Rosseel, G. P. and Dutton, R. W. (1989). "Influence ofdevice parameters on the switching speed of BiCMOSbuffers," IEEE J. Solid-State Circuits, 24(1), 90-99.

[7] Rothermel, A. and Hosticka, B. (1989). "Speed compar-ison of digital BiCMOS and CMOS circuits," lEE Proc.,Pt. G, 136(2), 49-56.

[8] Srivastava, A. (1991). "Switching properties of polysiliconemitter transistor operating in saturation," lEE Proc.-G,138(3), 358- 362.

[9] Diaz, C. H. and Leblebici, Y. (1991). "An accurateanalytical delay model for BiCMOS driver circuits," IEEETrans. Computer-Aided Design, 10, 577-588.

Authors’ Biography

A. Srivastava is currently an Associate Professor ofElectrical and Computer Engineering at theLouisiana State University in Baton Rouge. Hewas previously on the faculty in Department ofElectrical and Computer Engineering of the StateUniversity of New York, New Paltz; NorthCarolina State University, Raleigh, University ofCincinnati; and Birla Institute of Technology andScience, Pilani (India). During 1979-80, he wasalso a UNESCO FELLOW at the University ofCincinnati and University of Arizona, Tucson. Inthe past, he has also served as a Scientist at theCentral Electronics Engineering Research Insti-tute, Pilani (India). His research interests includeDigital and Analog/Mixed-Mode VLSI Design,Modeling; Smart Sensors and CMOS-MEMSIntegration; Rad-Hard GaAs and CMOS ICs; andCryogenics. He is a Senior Member of IEEE.

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