112 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 5, MAY 1994

InGaAs Microwave Switch Transistors for Phase Shifter Circuits

Mohsen Shokrani and Vik J. Kapoor, Senior Member, IEEE

Abstruct- A new InGaAs insulated-Gate FET (IGFET) with 1 pm gate length and three different gate widths have been designed, fabricated and characterized as switch devices for microwave control applications in phase shifter circuits. The devices employed a plasma deposited silicon dioxide gate insu- lator and had multiple air bridged source regions. The details of the DC current-voltage (I-V) characteristics and small signal S- parameter measurements up to 20 GHz are presented. The switch IGFET's had a drain saturation current density of 300 mNmm gate width with breakdown voltages of higher than 35 V. An insertion loss of 1.0, 0.6, and 0.4 dB at 10 GHz and 1.4, 0.8, and 0.4 dB at 20 GHz have been measured for the 300,600, and 1200 pm gate width IGFET's, respectively. Equivalent circuit models fitted to the measured S-parameters for IGFET's yielded on-state resistances from 10.7 to 3.3 R, off-state resistances from 734.4 to 186.8 0 and off-state capacitances from 0.084 to 0.3 pF as the gate width is increased from 300 to 1200 pm. The simulation results using IGFET models for the phase shifter circuits indicated a maximum phase error of 0.11", 0.26", and 0.47" with 0.74, 0.96, and 1.49 dB maximum insertion loss and greater than 33, 26, and 19 dB return loss for the 11.25", 22.5", and 45" phase bits, respectively, over the 9.5-10.5 GHz frequency hand.

I. INTRODUCTION

NDIUM gallium arsenide (InGaAs) is a promising semicon- I ductor for high frequency microwave and millimeter wave device applications due to its superior electronic properties. InGaAs lattice matched to indium phosphide (InP) has higher low field mobility (12000 c m 2 N s), and peak electron velocity (3 x lo7 c d s ) . Further InGaAs layers grown on InP are more suitable for high power applications due to the enhanced thermal conductivity of InP over GaAs. Excellent small signal and large signal microwave performance of InGaAs insulated- gate field-effect-transistors (IGFET) have been reported. A maximum frequency of operation (Fmax) of 45 GHz were obtained for a 1 Irm gate length and 0.56 mm gate width self aligned gate InGaAs IGFET [I]. Recently, IGFET's with 1 pm gate lengths have demonstrated an output power density of 1.07 W/mm of gate width with a corresponding power gain of 4.3 dB at 9.7 GHz [2]. Moreover, submicron depletion mode InGaAs power IGFET's have produced record output powers at K-band [3]. IGFET's with 0.7 pm gate lengths produced an output power density of 1.04 W/mm with an associated power gain and power added efficiency of 3.7 dB and 40%, respectively. Although excellent and impressive results have been demonstrated for InGaAs amplifier IGFET's, no research

Manuscript received March 25, 1993; revised July 27, 1993. The authors are with the Microwave Electronics Laboratory, Department

of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, Ohio 45221-0030.

IEEE Log Number 9216816.

has been reported for InGaAs based IGFET as a switch device. Development of a switch InGaAs IGFET could make significant contributions in the area of control applications as described below.

The switch FET is a three terminal device with the gate terminal as the control port and the source and drain terminals as the input and output port for the RF signal [4]. When a zero gate voltage is applied to the gate, the switch is in the low impedance state (or the on-state). When the FET is driven into pinch off by reverse biasing the gate with respect to the source, the switch is said to be in the high impedance state (or the off-state).

The on-state resistance of the switch FET (Ron) determines the insertion loss of the microwave signal through the device. Due to the insulating gate, much larger positive gate biases can be applied in an InGaAs switch IGFET than a GaAs switch metal-semiconductor FET (MESFET). This along with the enhanced mobility of InGaAs could reduce Ron and in turn the insertion loss of the switch FET without increasing the doping density of the channel region. The operation of the switch FET in the off-state is mostly dominated by the equivalent source to drain capacitance ( C o ~ ) . Since the source to drain resistance in the off-state is very high, C o ~ can simply be approximated as Cds + C, where C, is the series equivalent capacitance of gate-source capacitance ( Cgs) and gate-drain capacitance ( C g d ) and c d s is the source-drain fringing and depletion layer capacitance. The impedance of the switch FET in the off-state is decreased due to Co, which in turn degrades the isolation of the switch FET at higher frequencies of operation [4].

This paper describes the design, fabrication, characteriza- tion, and equivalent circuit modeling of 1 pm gate length InGaAs switch IGFET's. Three different gate widths of 300 pm, 600 pm, and 1200 pm were investigated to examine the trade off between low on-state resistance and high off- state capacitance. The DC current-voltage (I-V) characteristics as well as small signal scattering parameter (S-parameter) measurement results from 2-20 GHz are presented. The equiv- alent circuit models of the InGaAs switch FET fitted to the experimentally measured S-parameters is also given. Finally, the design and simulation results of monolithic loaded line phase shifter circuits using the InGaAs switch IGFET models are presented.

11. EXPERIMENTAL

Fig. 1 shows the schematic cross section of the I pm gate length InGaAs switch IGFET. The devices were fabricated on InGaAs layers grown lattice matched on semi-insulating (SI)

0018-9480/94$04.00 0 1994 IEEE

SHOKRANI AND KAPOOR: InCaAs MICROWAVE SWITCH TRANSISTORS FOR PHASE SHIITER CIRCUITS 113

GATE WIDTH - 300 ,600 ,1200 f l

- 4.5 pm -

, , GATE INSULATOR 1 GATE 1 OHMIC CONTACT

\

N-PIPE InGaAs (1017)

UNWPEDInP BUFFER LAYER 0.1 f l i

SEMI-INSULATING InP SUBSTRATE

Fig. 1. Schematic representation of the cross-section of an InGaAs switch IGFET with 1 pm gate length and three different gate widths of 300, 600, and 1200 pm.

InP substrates with resistivity greater than lo7 R. cm. The thickness of InGaAs and InP layers were 0.5 and 0.1 pm, respectively. The source-drain ohmic metal spacing was 4.5 pm. The length of the gate recess was 2.5 pm. The ohmic contact consisted of a 0.3 pm thick layer of Au:Ge which was Au plated to a thickness of 2 pm during the airbridge fabrication process. The gate metal was Ti/Au of 0.45 pm thickness.

The InGaAs switch IGFET's had two to eight parallel gate fingers with individual gate widths of 150 pm. This resulted in three total gate widths of 300, 600, and 1200 pm. This allowed the trade off between low on-state resistance and high off-state capacitance to be investigated. The individual source and drain regions were 30 pm wide while the outer source pads had widths of 60 pm. The source regions were connected to the source pad via Au airbridges crossing over the gate feed line. The signal leakage through the gate connection was suppressed by connecting a 5 KR on-chip mesa resistor to the gate of the IGFET. Finally 100 pm2 source, drain and gate pads were provided to accommodate wire bonds for device packaging and FG testing. The total area of each device was 0.3x0.56 mm2 for 300, 600, and 1200 pm gate width devices, respectively.

The InGaAs and InP layers used in this research were grown lattice matched on SI InP substrates using metal organic chem- ical vapor deposition technique. The details of the MOCVD growth has been reported [2]. The InGaAs layer was n-type doped to 1017 cm-3 and had a hall electron mobility of 6500 cm2N. s.

The cross section of the fabrication sequence of the InGaAs switch IGFET is shown in Fig. 2. The substrates were initially degreased in boiling acetone and methanol for 5 and 1 min each followed by a DI water rinse. Device active areas and gate bias resistors were defined by performing a mesa lithography followed by a mesa isolation etch. The mesa etch

PLATED Au

MESA ETCH

OHMIC CONTACT

RECESS ETCH

GATE OXIDE

GATE METAL

OXIDE ETCH

RESISTOR ETCH

AIR BRIDGE

IGFET RESISTOR

Fig. 2. Fabrication process cross-section for InGaAs switch IGFET with silicon dioxide gate insulator and source air bridges as described in the text.

was performed using a H2S04:H202:H20 (1:1:38) solution to etch the InGaAs layer active layer and a HCl:H20 (7:lO) to etch the undoped InP buffer layer (Fig. 2(a)). The samples were etched for 3.5 min to remove the InGaAs layer and 4 min to remove the InP buffer layer. Source-drain contacts were formed by evaporating 1500 8, Au:Ge 12% eutectic followed by 2000 A Au and lift off (Fig. 2(b)). The ohmic contacts to the gate bias resistor were also formed in this step. The samples were alloyed in a resistively heated furnace at 405" C for 1.5 min a forming gas ambient flow of 1 it/min. The channel region of switch FET's were then chemically recessed as shown in Fig. 2(c) using a H2S04:H20:H20 (1 : 1: 100) for about 4 min or until the desired source-drain current was achieved.

After stripping the recess photoresist, the silicon dioxide (Si02) gate insulator was direct plasma enhanced chemical vapor deposited (PECVD) to a thickness of 650 8, (Fig. 2(d)). Details of the Si02 deposition process have previously been reported [5] . The Si02 films were deposited using SiH4 and nitrous oxide (N20) as the reactant gases in a Technics Planar Etch IIA (PEIIA) system equipped with a 13.56 MHz RF power generator. Immediately prior to the insulator deposition, samples were cleaned in a dilute HF solution to minimize native oxide at the semiconductor-insulator interface. The Si02 deposition parameters were an RF power density of 85 mW/cm2, SiH4 flow rate of 21 sccm, N2O flow rate of 55 sccm, deposition pressure of 370 mTorr and a deposition temperature of 250" C. The samples were annealed in pure hydrogen for 0.5 hr to improve the bulk and the interfacial quality of the gate insulators. The 1 pm length gates were

114

Fig. 3.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 5, MAY 1994

DRAIN GATE

MESA RESISTOR

GATE FEED LINE

AIR BRIDGES

SOURCE

1 320

DRAIN VOLTAGE (V) Fig. 4. I-V characteristics of InGaAs switch IGFET. Drain current has been

Photograph of a fabricated InGaAs switch IGFET with 600 p m total gate width, 1 Jim gate length, 5 KQ mesa resistor and with a total die area of 0.35x0.56 mm2.

normalized to 1 mm gate width. The gate voltage is swept from $9 V to -15 V in steps of -3 V.

defined by optical lithography and 200 8, Ti and 4500 8, Au were lifted off (Fig. 2(e)).

In an amplifier IGFET, the gate metal is completely isolated from the rest of the FET by the highly resistive gate insulator. In the present InGaAs switch IGFET, because of the gate bias mesa resistor, there exists a conductive path between the resistor and the source-drain regions through the SI InP substrate as seen in Fig. 1. This causes a slight increase in the gate to source leakage circuit. It was also determined that after the gate insulator deposition, a layer of charge was accumulated at the surface of the InP substrate due to the gate insulator. This surface charge layer increased the conductivity of the SI substrates, resulting in an unacceptably high gate- source leakage currents which severely degraded the DC and the RF performance of the switch IGFET. Therefore the gate insulator was selectively etched from the regions where it would contribute to the gate-source leakage current as shown in Fig. 2(f). This reduced the gate-source leakage current to acceptable levels for proper switch IGFET operation. The gate bias mesa resistors were then trimmed to the desired resistance value. The resistor's active area was etched through a photoresist opening using a H2S04:H20:H20 (1:l: 100) solution (Fig. 2(g)). Resistors were etched for about 3 min which yielded a typical resistance of 5 kR.

Air bridges connecting individual source regions to the source pad were then formed. The source, drain and the gate pads were also Au plated in this step. The samples were coated with a 3.5 pm thick layer of Shipley 1400-37 photoresist and the bridge supports were defined using the support mask. This photoresist thickness would eventually be the bridge height and had to be thick for minimum cross over capacitance. This photoresist layer formed a platform for electroplating the bridge. A 100:1000 8, of Ti:Au seed layer was evaporated on the entire sample. The electrical contact to the bridges during gold electroplating was made through the thin Au interlayer. The seed layer was then thickened up to a thickness of about 3 pm by gold electroplating. The gold plating was performed using a commercially available

gold potassium cyanide solution from Engelhard corporation. The gold plating solution was heated to 60" C and stirred to improve uniformity. A plating current density of 2.5 mA/cm2 was used to obtain high quality and reproducible plated Au. The bridge pattem was then defined on top of the plated gold using the bridge mask and standard photolithography. The excess gold was etched away in a mixture of potassium iodine, iodide and DI water [KI:I2:HzO (8 gr:2 gr:80 ml)] for approximately 3 min followed by a 10 sec. etch in [HF:DI (1:lO)l to remove the Ti layer. The air bridge process was completed by lifting off the top and bottom layer resist in acetone using ultrasonic agitation followed by oxygen ashing as shown in Fig. 2(h). The substrates were then lapped to a thickness of 5 mils.

InGaAs switch IGFET's were packed in an HP 83040 Modular Microcircuit Package for RF testing. The package consisted of 2 end block launchers which contained 3.5 mm connectors and coaxial to microstrip launchers. The launch pins were ribbon bonded to 10 mm long 50 R Au microstrips on 10 mil alumina substrates. A thm-reflect- line (TRL) calibration was implemented to perform the S- parameter measurements. No DC voltage was applied to the source and drain. The small signal S-parameters were mea- sured from 2-20 GHz using an HP 8720 automatic network analyzer.

111. RESULTS A photograph of a fabricated 600 pm gate width InGaAs

switch IGFET is shown in Fig. 3. The ohmic contact resistance and the specific ohmic contact resistance were measured using a transmission line test structure. A contact resistance of 0.1Lo.5 R-mm and a specific contact resistance of 1-5 x R-cm were obtained. The sheet resistance of the InGaAsflnP layers were also measured using a Vander Paw structure. The sheet resistance was determined to be 140-150 R/O. Fig. 4 shows a typical I-V characteristics for an InGaAs switch IGFET. The drain current has been normalized to 1 mm gate

SHOKRANI AND KAPOOR: InGaAs MICROWAVE SWITCH TRANSISTORS FOR PHASE SHIFTER CIRCUITS 715

12Wq 6 W q 300q 0 1 I

a a. I

OFF STATE 3 bF -L, 8L 9

L 1

2.0 FREQUENCY (GHz) 20.0

%

ON STATE

e

W VJ

I a a.

8 9

2.0 FREQUENCY (GHz) 20.0 Fig. 6. Phase of S21 for the 300, 600, and 1200 pm InGaAs IGFET’s for the on-state and off-states. The measured data is indicated by triangles for the on-state and boxes for the off-state. The solid lines are the fit of the equivalent circuit model data to the measured 5’-parameters as described in the text.

Fig. 5. Insertion loss and isolation (magnitude of Sal in the on-state and off-state) for the 300, 600, and 1200 p m InGaAs switch IGFET. The on-state and off-state control voltages are +9 and - 15 V, respectively. The measured -- SOURCE data is indicated by triangles for the on-state and by boxes for the off-state. DRAIN- = D N

BOND WIRE TIME PAD BOND DELAY

The solid lines are the fit of the equivalent circuit model data to the measured S-parameters as described in the text.

TIME WIRE BOND DELAY BOND PAD

width. The gate voltage range is from -15 to 9 V in -3 V steps. At a drain-source bias of 2.5 V, the drain saturation current density was about 300 mNmm gate width. The pinch- off voltage of these devices were 12-15 V due to the voltage drop in the insulating gate. The gate-source and gate-drain reverse breakdown voltages were greater than 35 V for all three gate widths. The gate-source and gate-drain reverse saturation current were typically between 20 to 30 nA at 35 V and as low as 35 nA at 50 V. This high breakdown voltage could significantly increase the power handling capability of the switch FET for large signal applications. Due to the Si02 gate insulator, the drain saturation current and breakdown voltage values for the InGaAs switch IGFET’s are higher than typically obtained with recessed gate GaAs MESFET’ s. A breakdown voltage of 22 V and a drain saturation current density of 346 mNmm have been reported for a modified GaAs semi-insulated gate FET [6].

Fig. 5 shows the magnitude in dB of the forward trans- mission coefficient (S21) for the 300, 600, and the 1200 pm gate width InGaAs switch IGFET’s from 2 to 20 GHz. The on-state and off-state control voltages are +9 V and -15 V, respectively. The measured S 2 1 is indicated by triangles for the on-state switch FET and by boxes for the off-state switch FET. The measured results in Fig. 5 have been corrected for wire bond inductance. The solid lines through the measured data show the results of the equivalent circuit model used to fit the measured S-parameters and will be described in the next section. The insertion loss (magnitude of Sal in the on-state) of the 300 pm switch is 0.9 and 1.0 dB at 2 and 10 GHz

0-0

Ron c off

Fig. 7. InGaAs switch IGFET’s.

Schematic representation of an equivalent circuit model for the

and degrades to 1.4 dB at 20 GHz. The isolation (magnitude of ,921 in the off-state) of the 300 pm switch FET is 16.6 dB at 2 GHz and degrades to 7.5 dB at 10 GHz and reaches 2.2 dB at 20 GHz. The insertion loss of the 600 pm switch is 0.5, 0.6, and 0.8 dB at 2, 10, and 20 GHz, respectively. The isolation of the 600 pm switch FET is 12.1, 3.9, and 0.8 dB at 2, 10, and 20 GHz, respectively. Fig. 6 shows the corresponding phase of the measured 5’21 for all three gate widths in the on-state (triangles) and the off-state (boxes) and solid lines represent the results of the equivalent circuit model as described in the next section. The shift in phase of Szl in the off-state is due to the change in the equivalent source- drain capacitance as the gate width is increased from 300 pm to 1200 pm. The phase of ,921 in the on-state device stays fairly constant as a function of gate width at lower frequencies. The slight variations in the phase of S 2 1 as a function of gate width at higher frequencies in the on-state device could indicate the presence of parasitic reactive elements. All of the data presented above in Figs. 6 and 7 are for the IGFET when connected in the series configuration.

The measured reverse transmission coefficient (5’12) was similar to the 5’21 results for all three gate widths, indicating a bidirectional device. The observed behavior of Fig. 5 is similar to that of the GaAs switch MESFET’s [7]. As explained

776 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 5 , MAY 1994

previously, the capacitive coupling between the source and drain, degrades switch FET isolation in the off-state as the gate width and the frequency are increased as seen in Fig. 5 and its effect has to be taken into account when designing circuits. It is also observed that the device insertion loss is improved as the gate width is increased because the on-state resistance scales inversely with the gate width.

Iv. MODELING AND SIMULATION

A. IGFET Equivalent Circuit Modeling

Switch FET’s are widely used in microwave monolithic integrated circuit applications including loaded line [8], re- flection type 181, high pass-low pass 191, and switched line [lo] phase shifters and single-pole double-throw (SPDT) [ 111 switches. Therefore, for fast and simple computer aided design (CAD) of these circuits, an accurate switch FET circuit model is needed. These circuit models can also be used to relate the physical device parameters to final device performance or to monitor process effects on device performance. Fig. 7 shows the equivalent circuit model used to fit the measured small signal S-parameters of the InGaAs switch IGFET’s. The center box labeled ZDEVICE includes a resistor Ron for the on-state switch FET and a resistor R o ~ shunting a capacitor C,, for the off-state of the switch FET as shown in Fig. 7. The source and drain bond pads were modeled as microstrip transmission lines. The lengths and widths of the microstrips were set to 100 pm. The substrate thickness, relative dielectric constant (ET) and conductor thickness were set to 5 mils, 12.4, and 3 pm, respectively. The effects of wire bond inductance and lengths were accounted for using the wire bond over ground model. The outer boxes labeled by 7’s are time delays and were used to represent the switch FET electrical lengths 171. In this model it is assumed that gate circuit is effectively RF isolated from the switch FET by the gate bias resistor. The S-parameter measurements performed on a test mesa resistor identical to the one used in the switch FET, indicated better than 25 dB isolation over the 2-20 GHz frequency which proves the validity of the above assumption. All modeling and simulations in this work were performed using the HP Microwave Design System (MDS) version 4 software running on a Sun SPARCstation 2 computer workstation. The measured S-parameters were fitted to the equivalent circuits for both the on and the off-state simultaneously over the 2-20 GHz frequency range using the HP MDS gradient optimizer. The optimizer goal statements were set to minimize the vector percent difference between the measured data and the circuit models.

Table I represents the results of the modeled equivalent circuit parameters for the 300, 600, and 1200 pm InGaAs switch FET’s with 1 pm gate length. For the on-state FET, Ron values of 10.74, 6.54, and 3.38 R were obtained for 300, 600, and 1200 pm FET’s, respectively. The off-state FET’s were characterized by C0, of 0.084, 0.156, and 0.3 pF and Rotf of 734.4, 402.6, and 186.8 R for the 300, 600, and 1200 pm gate width FET’s respectively. The value of R 0 ~ are lower than GaAs MESFET’s and may be due to gate leakage.

TABLE I SWITCH IGFET EQUIVALENT CIRCUIT PARAMETERS

AS A FUNCTION OF DEVICE GATE WIDTHS

Parameters 300 pm 600 pm 1200 pm Ron (f2) 10.74 6.54 3.38 coff (PF) 0.084 0.156 0.300 Roff (n) 734.4 402.6 186.8 Tdelav (ps) 2.07 1.67 1.96

It is observed that Ron and C o ~ scale almost linearly with gate width with Ron ~ 3 . 7 R.mm gate width and Coff ~ 0 . 2 6 pF/mm. The results of the switch IGFET equivalent circuit model is shown by solid lines in Figs. 5 and 6, where the magnitude and phase of the measured Szl are also shown from 2 to 20 GHz. Strong agreement is observed between the model simulation and the measured data indicating an accurate equivalent circuit. The above values obtained for Ron and Coff of the 1 pm gate length InGaAs switch IGFET, nearly match that obtained for E-beam defined 0.35 pm gate length GaAs switch FET’s [ I 11.

B. MMIC Phase Shifter Design and Simulation

In order to evaluate the functionality and usefulness of the fabricated InGaAs switch IGFET’s, MMIC phase shifters were designed and simulated. A loaded line technique has been used to realize the phase shifters. The loaded line phase shifters are simple in structure and provide a constant phase shift and a low insertion loss over a wide frequency range and are particularly suitable for smaller phase bits 181, 1121. A schematic diagram of a loaded line phase shifter is shown in Fig. 8. The loaded line phase shifter consist of two equal two-state switchable admittances connected in shunt with a transmission line section of electrical length OL and characteristics impedance 2,. The admittances required for a given phase shift are provided by two loading stubs (impedance transformers) of electrical length Os and characteristic impedance Z S , each terminated by a switch FET. The two admittance states are produced by switching between the on-state and the off-state of the switch FET’s. The transmission between the two admittance states produces a change of A 0 in the phase of S21. Typical value of OL and ZL are about 90” and 50 0, respectively. Typically, microstrip transmission lines are used to realize the phase shifter in the monolithic form. The loaded line and the loading stubs are designated by microstrip widths and length of WL, l ~ , and WS, Is, respectively.

Three phase bits of 1 1.25, 22.5, and 45” were designed and simulated in the monolithic form using the HP MDS software. For each phase bit, OL, ZL, Os, and 2 s were calculated using the equations given in 1123, 1131. Values of WL, Z L , WS, and 1s were then obtained by optimizing the characteristics impedance and the lengths of microstrip transmission lines to ideal transmission lines. These values were then used as starting parameters in phase shifter optimization. The switch IGFET equivalent circuits discussed earlier, were used in all the calculations and optimizations. The substrate thickness, relative dielectric constant and conductor thickness values of 5 mils, 12.4, and 3 pm were used. Dielectric losses were also taken into account with dielectric loss tangent of 6 x

-_ . . -- ... .

SHOKRANI AND KAPOOR: InGaAs MICROWAVE SWITCH TRANSISTORS FOR PHASE SHIFTER CIRCUITS

I LOADED LINE

777

=S - ‘s I

The switch FET’s grounding was simulated using Au ribbon bonds of 1 mil thick and 4 mils wide. The phase shifters were designed for 50 R input and output interfacing. The design also included the effects of microstrip bends and discontinuities. The phase shifter circuits were optimized for minimum insertion loss, minimum retum loss and minimum phase error over 9.5-10.5 GHz frequency range.

To determine the optimum FET gate periphery, each phase bit was designed using 300, 600, and 1200 pm switch FET models. Table I1 presents the optimum gate width along with the optimized electrical and physical parameters for the loaded line and the stub lines. Optimum switch IGFET gate widths of 1200, 600, and 600 pm were determined for 11.25, 22.5, and 45” phase bits, respectively. The simulated electrical performance of the phase shifters are shown in Table 111. The effective dielectric constant (€,E) was calculated to be 8 for the 50 R loaded lines and 7-8 for the high impedance stub lines. The simulation results indicated a 0.11, 0.26, and 0.47” maximum phase error with 0.74, 0.96, and 1.49 dB maximum insertion loss and greater than 33, 26, and 19 dB retum loss for the 11.25, 22.5, and 45” phase bits, respectively over the 9.5-10.5 GHz frequency band. The maximum phase error is the maximum phase deviation from the design phase shift over the frequency band. The simulated performance of the phase shifters indicate an improvement over the simulated GaAs loaded line phase shifter implemented with GaAs switch FET’s in the C-band frequency [8] and clearly indicates the feasibility of InGaAs switch IGFET’s for microwave integrated circuit control applications. The improved simulated phase shifter performance may be due to a superior microwave response of the InGaAs insulated gate FET.

- IMPEDANCE TRANSFORMERS

V. CONCLUSION

InGaAs IGFET have been investigated for the first time as switch FET’s for microwave control circuit applications. Switch IGFET’s with 1 pm gate lengths and three gate widths of 300, 600, and 1200 pm have been designed, fabricated, and characterized up to 20 GHz. The devices were fabricated on MOCVD grown InGaAs layers and employed a plasma

TABLE I1 PHASE SHIFTER’S PHYSICAL AND ELECTRICAL PARAMETERS

Size Size (pm) (w) (wn) ( w ) (”) ( w )

Bit FET ZL (n)O,(”) I L WL Z , ( ~ ) O S ( ~ ) 2s 1V.s

11.25 1200 49.9 87.4 2580 96.0 108.8 100.3 3184 5.9 22.5 600 49.6 87.3 2575 97.5 100.3 110.9 3491 9.3 45 600 47.5 87.6 2573 107.3 67.7 112.6 3418 42.8

TABLE 111 PHASE SHIFTER’S SIMULATED ELECTRICAL PERFORMANCE

Bit Size (”) InGaAs Max Phase Max Insertion Retum Loss IGFET Size Error (”) Loss (dB) (dB)

11.25 1200 0.11 0.74 >33 22.5 600 0.26 0.96 > 26 45 600 0.47 1.49 >19

deposited silicon dioxide gate insulator. A 5 KR mesa resistor was used to RF isolate the gate bias circuit from the FET. The switch IGFET’s have a drain saturation current density of 300 mA/mm gate width. The source-gate and source-drain breakdown voltages of higher than 35 V were obtained. This high breakdown voltage could significantly improve the power handling capability of the switch FET’s. An insertion loss of 1.0, 0.6, and 0.4 dB at 10 GHz and 1.4, 0.8, and 0.4 dB at 20 GHz have been measured for the 300, 600, and 1200 pm gate width IGFET’s, respectively. Equivalent circuit models were fitted to the measured S-parameters. The switch IGFET’s had on-state resistances of 3-10 R and off-state capacitances of 0.08-0.3 pF. These values are comparable to 0.35 pm gate length GaAs switch MESFET’s. X-band loaded line MMIC phase shifter circuits have also been designed and simulated using the InGaAs switch IGFET’s circuit models. Optimum gate widths of 1200, 600, and 600 pm were determined for phase bits of 11.25, 22.5, and 45”, respectively. The simulation results indicated a 0.11”, 0.26O, and 0.47” maximum phase error with 0.74, 0.96, and 1.49 dB maximum insertion loss and greater than 33, 26, and 19 dB retum loss for the 11.25, 22.5, and 45” phase bits, respectively over the 9.5-10.5 GHz frequency band. Presently, the large signal characteristics of the InGaAs switch IGFET’s are being investigated as well as the fabrication of the phase shifter circuits.

REFERENCES

P. D. Gardner, D. Bechtle, S. Y. Narayan, S. D. Colvin, and J. P. Paczkowski, “High-efficiency GaInAs microwave MISFET’s,” IEEE Electron. Device Lett., vol. 8, pp. 443446, 1987. G. A. Johnson, V. J. Kapoor, M. Shokrani, L. J. Messick, R. Nguyen et al. “Indium gallium arsenide microwave power transistors,” IEEE Trans. Microwave Theory Tech., vol. 39, pp. 1069-1075, 1991. G. A. Johnson, V. J. Kapoor, D. Schmitz, and H. Jurgensen, “InGaAs field-effect transistors with submicron gates for K-band applications,” IEEE Trans. Microwave Theory Tech., vol. 40, pp. 429433, 1992. Y . Ayasli, “Microwave swirching with GaAs ET’S,” Microwave J., pp. 61-74, Nov. 1982. M. Shokrani and V. J. Kapoor, “Silicon dioxide with a silicon inter- facial layer as an insulating gate for highly stable InP MISFET’s,” J. Electrochem. Soc., vol. 138, pp. 1788-1794, 1991. Y. H. Yun and R. J. Gutmann, “GaAs semi-insulated gate FET (SIGFET) as high power MMIC control devices,” IEEE Inr. Microwave Symp. Dig., 1988, p. 999.

778 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 42, NO. 5 , MAY 1994

[7] A J Slobodnic, R. J Websters, G A Roberts, and G. J. Scalzie, Vik J. Kapoor (S’75-M’7&SM’83) received the “Millimeter wave GaAs FET switch modeling,” Microwave J , pp M.S. and Ph D. degrees in 1972 and 1976, respec- 93-104, Aug 1989. tively, from Lehigh University, Bethlehem, PA.

[SI C Andricos, I J Bahl, and E L. Gnffin, “C-band 6 bit GaAs monolithic He was a Senior Engineer and a member of phase shifters,” IEEE Trans Microwave Theory Tech., vol. 33, pp the technical staff at Fairchild Semiconductor, Palo 1591-1596, 1985 Alto, CA, from 1976 to 1978. In 1978, he joined

[9] Y Ayasli, S. W. Miller, R. L. Mozzi, and L K. Hanes, “Wide band S-C the faculty of the Case Westem Reserve Univer- monolithic phase shifter,” IEEE Trans. Electron. Devices, vol. ED-3 1, sity, where he was the Director of the Solid State p. 1943, 1984. Integrated Circuits Laboratory until 1983 He is

[lo] V Sokolov, J J Gedees, A. Contolatis, P E. Baulthan, and C Chao, presently a Professor and Department Head of the “A Ka band GaAs monolithic phase shifter,” IEEE Trans Electron. Electrical and Computer Engineering Department at Devices, p 1855, 1983 the University of Cincinnati. His research focuses on compound semiconduc-

Il l1 M. J Schlndkr and A Momis, “DC-40 GHz and 2 0 4 0 GHz MMIC tor process technology including heterostructures and quantum well devices SPDT Dev~ces, vO1. ED-34, PP. for the next generation of high-power, high-frequency devices for applications 2595-2601, 1987 In mcrowave and digital integrated circuits. He is also investigating high-

[I2] I Bahl and K. G’pta, “Design Of loaded line ‘IN diode phase temperature superconductors for passive and active microelectronic devices $hifter CircuitS,” IEEE Trans Mtcrowave Theory Tech., vol MTl-28, for rmcrowave app~lcatlons, pp. 219-224, 1980

[I31 C. Nguyen, “Design and performance of a W-band microstrip phase shifter,” Microwave J , pp 91-102, July 1989

IEEE Trans.

Dr Kapoor is a Fellow of the Electrochemical Society

Mohsen Shokrani received the B.S. degree in physics in 1986 from Thomas More College, Fort Mitchell, KY. He received the M.S. and Ph.D. degrees from the University of Cincinnati in electrical engineering in 1990 and 1993, respectively. He is currently employed at Anadigics Inc. in New Jersey, where he is responsible for GaAs materials and ion implantation.