Instruction Cycle vs Clock Cycle. Instruction Cycle: The time required to fetch and execute an instruction Clock Cycle: one clock cycle, during which one step of an execution is completed. - PowerPoint PPT Presentation
Instruction Cycle vs Clock Cycle Instruction Cycle: The time required to fetch and execute an instruction Clock Cycle: one clock cycle, during which one step of an execution is completed. Examples: In Chapter 5, T 0 , T 1 , T 2 , ….., T 15 , are used as symbols for a Clock Cycle. The Instruction Cycle of a Register- reference instruction consists of 4 clock cycles. The Instruction Cycle of a Memory-reference instruction consists of 5 to 7 clock cycles. 1
Transcript
Instruction Cycle vs Clock Cycle Instruction Cycle: The time required to fetch
and execute an instruction Clock Cycle: one clock cycle, during which
one step of an execution is completed. Examples: In Chapter 5, T0, T1, T2, ….., T15,
are used as symbols for a Clock Cycle. The Instruction Cycle of a Register-reference
instruction consists of 4 clock cycles. The Instruction Cycle of a Memory-reference
instruction consists of 5 to 7 clock cycles.
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Example: Adding two 32-bit numbers (A and B) by using the 16-bit Basic Computer
C = A + B Split A into 16 bit numbers: AX: more significant 16 bits; AY: less significant 16 bits Similarly B and C can be written as
BX:BY and CX:CY respectively. Store Carry-out from MSB in CZ.
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Storing data in memory4K memory locations: 000 to FFF in HEX
Data Memory LocationAX F00
AY F01
BX FO2
BY F03
CX F04
CY F05
CZ F063
ProgramMemory Location Nature of INSTRUCTION445 LDA direct from address F01446 LDA direct from address F00447 STA F05448 LDA direct from address F00449 SZE44A INC44B ADD direct from address F0244C STA F0444D CLA44E SZE44F INC450 STA F06
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memoryMemory Location
STORAGE PURPOSE
0 Reserved for storing the address of the next instruction, when a program is interrupted and branched out to service an I/O sub-program
1 Has a directly-addressed BUN instruction, which points to the START of the I/O sub-program
445-450 Program for adding two 32-bit numbers, using the 16-bit Basic Computer of Fig 5-4
29A-2A2 I/O sub-program
2A1 IEN 1 Last-but-one instruction of the I/O sub-program
2A2 Last instruction of the I/O sub-program: Indirectly-addressed BUN instruction, which puts back into PC, the address, which had been stored at address “0”, while Branching to the I/O sub-program 5
Q1The Table shows, at T0, contents of one register, two flip-flops and some of the memory locations:
Register/Flip-flop/Memory Location
Contents
PC 445R 0IEN 1
445 2F01F01 A35F001 429A
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Note: Use Figure 5-4 and Table 5-6 from your text-book for solving Q 1 and Q 2.
Q 1: Problem in Steps
Step 1: The first memory instruction at address 445 is executed. While executing this instruction, during clock cycle T4, R is set to 1.
Step 2: Three clock cycles of interrupt process are executed. At the end of this step R is cleared.
Step 3: The second memory instruction at address 001 is executed.
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Q 1: To Do ……….1 Specify the register transfer operation(s) being
executed during each clock cycle. For Step 1, answer the following:
What is the value of I immediately after the clock cycle T2 is over?
Which instruction is being executed during this Step? For Step 2, answer the following:
What is the value stored at address 0, immediately after clock cycle T1 is over?
What are the values of IEN and R immediately after the clock cycle T2 is over?
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Q 1: To Do ……….2 For Step 3, answer the following:
What is the value of I immediately after the clock cycle T2 is over?
Which instruction is being executed during this Step? Specify the contents (in hexadecimal) of
registers PC, AR, DR, AC, IR and TR at the end of each clock cycle. If the contents of a register are not yet known, specify it as X.
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Q2 The Table shows, at T0, contents of two registers, two flip-flops and some of the memory locations:
Register/Flip-flop/Memory Location
Contents
PC 2A2AC A35FR 0IEN 1
2A2 C000000 0446446 1F03F03 2A45
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Q 2: Problem in StepsStarting with the above initial values at T0,
the following steps are taken in sequence: Step 1: First the memory instruction at
address 2A2 is executed. Step 2: After executing Step 1, the
memory instruction at address 446 is executed.
During execution of the two steps, for each clock cycle, starting from T0 for each of the steps, work out the following:
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Q 2: To Do ……….1 Specify the register transfer operation(s) being
executed during the clock cycle. For Step 1, answer the following:
What is the value of I immediately after the clock cycle T2 is over?
Which instruction is being executed during the Step? For Step 2, answer the following:
What is the value of I immediately after the clock cycle T2 is over?
Which instruction is being executed during the Step? What is the value of E immediately after the clock cycle
T5 is over? Specify the contents (in hexadecimal) of registers PC, AR,
DR, AC and IR at the end of each clock cycle. If the contents of a register are not yet known, specify it as X. 12
