Date post: | 28-Dec-2015 |
Category: |
Documents |
Upload: | bruno-morris |
View: | 217 times |
Download: | 2 times |
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
The Front-End Driver Card for CMS Silicon Microstrip Tracker Readout
LEB2000 Krakow
S.A.Baird, K.W.Bell, J.A.Coughlan, R.Halsall,W.J.Haynes, I.R.TomalinCLRC Rutherford Appleton Laboratory
E. CorrinImperial College London
Presented by John Coughlan
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
CMS Silicon Tracker Readout
~ 10 million Silicon Microstrips
80K APV25 readout chips ON Detector
Analogue Optical readout
40K ADC readout system OFF Detector
Level 1 rate ~ 100 kHz
Front-End Driver:
Optical receivers, ADCs, Digital processing, Buffering, DAQ interface
Related talks... APV25 : Geoff HallOptical Links : Francois Vasey LHC Test Beam : Nancy MarinelliTrigger Thottle System : Attila RaczPixel Vertex Detector : Danek Kotlinski
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
FED Features
• FunctionsOptical Receiver
ADC
Digital Processing
Cluster Finding
Data Formatting
DAQ Buffering
Synchronisation Checking
Local Monitoring
• FunctionsOptical Receiver
ADC
Digital Processing
Cluster Finding
Data Formatting
DAQ Buffering
Synchronisation Checking
Local Monitoring
• InterfacesFront-End Electronics
DAQ
TTC
Trigger Throttle & Synchronisation System
Detector Controls System
• InterfacesFront-End Electronics
DAQ
TTC
Trigger Throttle & Synchronisation System
Detector Controls System
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
FED Architecture
FPGA
Opto RxP
D A
rra
y
ProgDelay
1
Fibre ribbon12 way
Post ADCProcessing
TTCrx1
FE 1
9
SBC
DAQ
SSRAM
2
2
fw
X
VME
BSCAN
FPGA
1 DualADC
DualADC
1
6
FPGA
Opto Rx
PD
Arr
ay
8
Post ADCProcessingFE 8
8 DualADC
DualADC
43
48
ProgDelay
Fibre ribbon12 way
READOUT
ASIC
ASIC
ASIC
DAQ
Serial I/O
RT Synch & Error
Clock
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
Post ADC Processing Block
ADC 1 10 10
trig1
sy
nc
8
trig2P
ed
su
b8
trig3
cm
su
bR
e-o
rde
r
108
Hit
fin
din
g
s-datas-addr8
16
hit
Pa
ck
eti
se
r
8
8headers
token in
data
DP
M 16
No hits
Se
qu
en
ce
r-m
ux
8 8a
d
a
d
ADC 12 10 10
trig1
sy
nc
8
trig2
Pe
d s
ub
8
trig3
cm
su
bR
e-o
rde
r
108
Hit
fin
din
g
s-datas-addr8
16
hit
Pa
ck
eti
se
r
8
token out
data
DP
M 16
No hits
Se
qu
en
ce
r-m
ux
8 8a
d
a
d
trig
8headers averages
averages
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
Backend Readout Block
Dat
a M
erge
r
1
8
Pro
g F
ilter
For
mat
SSRAM INT
SSRAM INT
INT
DA
Q IN
T
Pro
g F
ilter
For
mat
TTCINT
9
SBC
DAQX
VME
FE FPGA 1
FE FPGA 8
SSRAM
SSRAM
TTX Rx
Ctrl
FE FPGAsbus control etc
VMEFPGA
FPGA
8
8
Trigger in
Token backToken out
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
FED 9U Layout (96 ADC channels)
adc
adc
adc
DSPASIC
adc
adc
adc
adc
adc
adc
adc
adc
adc
DSPASIC
adc
adc
adc
DSPASIC
adc
adc
adc
adc
adc
adc
adc
adc
adc
DSPASIC
adc
adc
adc
DSPASIC
adc
adc
adc
adc
adc
adc
adc
adc
adc
DSPASIC
adc
adc
adc
DSPASICadc
adc
adc
adc
adc
adc
adc
adc
adc
DAQ
VME’ VME
FE 1
TTC
FE 2
FE 3
FE 4
FE 5
FE 6
FE 7
FE 8
360 MByte/s
150 MByte/s/%
100 KHz
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
B Scan
fwNN Synch
FEFPGA
TTCrxASIC
DAQ
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
50 MByte/s/%
• Board Input rate 3 Gbyte/s
• Board Output Rate 50 Mbyte/s per percent occupancy
• Board Input rate 3 Gbyte/s
• Board Output Rate 50 Mbyte/s per percent occupancy
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
Final System
• 420 Boards 96 ADC/Board
• 21 Crates
• 7 Racks
• 420 Boards 96 ADC/Board
• 21 Crates
• 7 Racks
• 40 K ADC Channels 10 Bit@40MHz• Trigger Rate 100 KHz• Input Rate 1.5 T Byte/s• Output rate 25 Gbyte/s/%
• 40 K ADC Channels 10 Bit@40MHz• Trigger Rate 100 KHz• Input Rate 1.5 T Byte/s• Output rate 25 Gbyte/s/%
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
FED Modelling Basics
• Modelling as a tool
Optimise the Design
Optimising the cost performance ratio
Elaborating & testing the Specification
• Modelling as a tool
Optimise the Design
Optimising the cost performance ratio
Elaborating & testing the Specification
• StudyBuffer Depths & Overflow
Bus Speeds
Algorithm
Data Format
Exception conditions & handling
Data Flow control
Different operating scenarios….
• StudyBuffer Depths & Overflow
Bus Speeds
Algorithm
Data Format
Exception conditions & handling
Data Flow control
Different operating scenarios….
Test Bench FED Model
TTC - CLK...
DAQ
‘VME’
ADC 0
ADC N
AnalyserOutput
Test Vectors
DAQOutput
SetupParam’s
Monte Carlo
Simulation EnvironmentDigital HDL Simulator
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
FED Modelling Implementation
• Implementation9U Design based on FED 1994 model
Used in 1996 Beam Test
1 ADC Channel in ~25K Gate FPGA
Limited at the time by FPGA technology
• Implementation9U Design based on FED 1994 model
Used in 1996 Beam Test
1 ADC Channel in ~25K Gate FPGA
Limited at the time by FPGA technology
• Additional FeaturesRe-ordering
Pedestal Removal
Threshold per strip
Data range monitoring & limiting
Sparsified & raw data readout
• Additional FeaturesRe-ordering
Pedestal Removal
Threshold per strip
Data range monitoring & limiting
Sparsified & raw data readout
adc 10 10
trig1
sy
nc
8
trig2
Ba
se
lin
e(a
ve
rag
e)
8
trig3
Th
res
ho
ld(p
er
str
ip)
sdatasaddr8 fi
fo 16
write
128 cycles 128 cycles
ctr fifo 8No hits
Pa
ck
eti
se
r
8
fifo 8proccessing status
fifo 8Raw Data
token in
token out
data
Qu
ad
ran
td
ata
bu
s
8
trig2
Pe
de
sta
lR
em
ov
al
Re-order
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
Software Architecture
• Software ArchitectureUser Customisable within a RT framework
Network
VME
Supervising WS
CRATE SBCsReal Time OS
HardwareFED, FEC, TTC FPGA
USER
USERTracker System ‘Kernel’
GUI
Network
Tracker Crate ‘Kernel’
Memory Map
Hardware Driver
Network
CalibrationSetup
Fast MonitoringException Handling
Hit FindingLogic Analyser
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
FED Status & Plans
• Interfaces Status
Opto Front-end specified (op-amp may be required)
TTC Rx concept well defined
Some areas less well defined, Throttle, Synchronisation (APV Emulation)
DAQ Specification not fully defined - DAQ TDR Q4/2001
Modularity: FE-FED Mapping, Occupancy, DAQ Rates, load balancing
• Timescales
PMC Prototype satisfies Labs and Test Beams 1999-2001
Design & Modelling of Final FED until mid 2001
(Clustering algorithm )
Final FED Prototype for test beam 2002
Final FED Production start in 2003
• Interfaces Status
Opto Front-end specified (op-amp may be required)
TTC Rx concept well defined
Some areas less well defined, Throttle, Synchronisation (APV Emulation)
DAQ Specification not fully defined - DAQ TDR Q4/2001
Modularity: FE-FED Mapping, Occupancy, DAQ Rates, load balancing
• Timescales
PMC Prototype satisfies Labs and Test Beams 1999-2001
Design & Modelling of Final FED until mid 2001
(Clustering algorithm )
Final FED Prototype for test beam 2002
Final FED Production start in 2003
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
FED-PMC Prototype
• 8 x 10 Bit 40 MHz ADC• 64K Memory/per ADC• 40 K Gate FPGA Control• PCI Interface• Mounts on Commercial VME CPU Board
(or with an adapter in a PC slot)
• 30 in service• 30 more about to be ordered• Present Generation of ADC PMC
Used in LHC test beam Y2000Used in LHC test beam Y2000
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
1 25
E-Net Switch
FECCRATES DCS
Tracker Control WS
TTCCRATES
DAQ
VME SBCRTOS
Tracker Monitoring & Control
• Trigger Rate 100 KHz• Input Rate from FE 1.5 T Byte/s• Output rate to DAQ 25 Gbyte/s per percent occupany
D-BASER/C
50K ADC Channels
FEDCRATES
Instrumentation Department J. Coughlan et al.Rutherford Appleton Laboratory 14 September 2000LEB2000 Krakow
Crate Layout
LAN
1 212
FE 1
DAQ
TTC
FE 2
FE 3
FE 4
FE 5
FE 6
FE 7
100MBit/s
• Crate Input Data Rate 60 Gbyte/s• Crate Output Data Rate 1GByte/s per pecent occupancy
B-Scan
F-Bus
NN Synch
100 KHz
FE 8
Throttle