Page 2
Major Fabrication Steps in MOS Process Flow
Used with permission from Advanced Micro DevicesUsed with permission from Advanced Micro Devices
Oxidation(Field oxide)
Silicon substrate
Silicon dioxideSilicon dioxide
oxygen
PhotoresistDevelop
oxideoxide
PhotoresistCoating
photoresistphotoresist
Mask-WaferAlignment and Exposure
Mask
UV light
Exposed Photoresist
exposedphotoresistexposed
photoresist
GS D
Active Regions
top nitride
S DG
silicon nitridesilicon nitride
NitrideDeposition
Contact holes
S DGG
ContactEtch
Ion Implantation
ox DG
Scanning ion beam
S
Metal Deposition and
Etch
drainS DGG
Metal contacts
PolysiliconDeposition
polysiliconpolysilicon
Silane gas
Dopant gas
Oxidation(Gate oxide)
gate oxidegate oxide
oxygen
PhotoresistStrip
oxideoxide
Ionized oxygen gas
OxideEtch
photoresistphotoresistoxideoxide
Ionized CF4 gas
PolysiliconMask and Etch
oxideoxide
Ionized CCl4 gas
CF4 or C3F8 or CHF3 O3 CF4+O2 or CL2
Page 3
But we are not finished yet…
• Front end of the line completed• Back end of line (BEOL) starts• Devices on the chip need to be
connected to one another• Interconnect Layers
Page 4
Integrated Circuit Manufacture
Integrated circuit 1992-19980.75 micron dielectric features
Integrated circuit 1998-Present
0.18 micron dielectric features
Page 5
M7
M6
M5
M4
M3
M2
M1
Metal Wire Interconnects
6.5 microns
5.6 microns
130nm node
90 nm node
Page 6
Dual Damascene process
CDOCu
Hermetic etch stop
1. Via etch (doesn’t expose Cu)2. Trench etch3. Etchstop etch (exposes Cu4. Barrier deposition5. Cu seed deposition PVD6. Electroplate Cu7. CMP to planarize
Page 7
Representative dual damascene process sequence.
Page 8
Cu seed
Polished Cu
TaN / Ta barrier
Silicon nitride
Electroplated Cu
Fig 1.
Barriers required: TaN less susceptible to oxidation; Ta has better wetting for Cu seed
After anneals, the PVD-deposited Cu seed and Electroplated Cu combine; Cu grains are columnar
Page 9
Simple model for interconnect.
H
X
W
T
L = length of interconnect.
Resistance: R = L/WTCapacitance vertical = 2o WL/HCapacitance horizontal = 2o TL/X
RC = 2o L2 [ (1/TH) + (1/WX) ]
If we take T=H and X=W, thenRC = 2o L2 [ (1/W2) + (1/T2) ]
Example:Length L = 10 mmInterconnect thickness T = 0.18 micronAssume T=H, X=WRC as function of pitch = X+W for Cu and Al and oxide as dielectric material
1 GHz
Page 10
Interconnection paradigm shifts for devices < 0.25 micron.
Page 11
Movement to reduce RC time constant for interconnection:R: conductor.
C: dielectric constant.
Al: 3 micro-ohm cm.Cu: 1.7 micro-ohm cm.Thus move from Al to copper can provide factor of 1.8.Movement has driven development of CMP processing
and metalization fabrication scheme known as Damascene Copper.
SiO2: = 4.0Polymers: = 2-2.7 1.5-2 improvementPorous materials: = 1.5-2 2-2.7 improvementAir: = 1.0 4 improvementMovement has driven development of polymeric
dielectric materials toward production and spurred development of many new materials and processes.
Page 12
ChemicalFamily
DepositionTechnique(s)
K Range RepresentativeVendors
Polyarylethers Spin – on 2.6 – 2.8AlliedSignal,
Dow Chemical,Schumacher
Organosilicates(Polysiloxanes) Spin – on, CVD 2.5 – 3.2
AlliedSignal, AMAT,Novellus,
Dow CorningAmorphous
Fluorocarbon( - CFx)
CVD 2.6 – 3.2 Novellus
HydrogenSilsesquioxane Spin – on ~ 3.0
Dow Corning
PTFE Spin – on ~ 2.1W.L. Gore
Porous Silica Spin – on 1.8 – 2.7AlliedSignal,
Asahi Chemical
Low K Materials for IC Intermetal Dielectrics:
The Leading (or at Least Most Mature) Chemistries
Page 13
Spin - On CVD• Evolutionary from Photoresist
• Rapid Film Deposition (High Throughput with Automated Cure Process)
• Gap Fill and Planarization• Organic, Inorganic and
Organosilicates• Lower Equipment Cost• Ease of Tool Cleaning • Non - Vacuum Method• Many Material Suppliers &
Tool Vendors• Detailed Chemical
Characterization (Pre - Deposition)
• Evolutionary from SiO2, Si3N4
• Solventless• Conformal Coatings•Simple, Monomeric
Precursors• Cluster Tool Processing
Possible•
Comparison: spin - on vs. CVD deposition for “Low-K”.
Page 14
High K Dielectrics• Capacitors, Filter, etc.
Page 15
Chemical and Mechanical Planarization (CMP).Chemical and Mechanical Planarization (CMP).
Developed at IBM in mid-1980’s.
Global planarization across wafer through selective removal of high elevation features.
Page 16
CMP: important features.CMP: important features.
Goals for CMP process:• Good planarity across die (150 nm max.).• Good film thickness uniformity across wafer (±2%, 1).• High removal rates: 100-200 nm/min.• Good selectivity or end point determination.• Minimal defect and particulate creation (<0.125
particles/cm at 0.06 micron).
Pad conditioner
Pad/slurry
Wafer / holder
Page 17
CMP: polishing mechanisms and technology.CMP: polishing mechanisms and technology.• Mechanism differs for each material being processed.• Mechanism can involve conversion of materials to chemical state
which is better suited to mechanical removal with slurry materials of selected hardness. Example: metals converted to oxides and etched with oxide particles.
• Preston’s law often is obeyed:Rate = Kp P v
Where Kp is Preston constant, P is applied pressure, and v is linear velocity of polishing pad relative to wafer.
-5 0 0
5 0 0
1 5 0 0
2 5 0 0
3 5 0 0
4 5 0 0
0 1 2 3 4 5 6 7 8 9
D o w n F o r c e (p si )
Rem
oval
Rat
e (Å
/min
)
C o llo id a l, i n -s i tu , g ro o ve
C o llo id a l, i n -s i tu , p e r f
C o llo id a l, i n -s i tu , g ro o ve - M o d e l
C o llo id a l, i n -s i tu , p e r f - M o d e lEtch rate (angstrom/min)
4500
00
00 8Downward force (psi)
Data for two different pad surfaced and two different slurries.
Page 18
Example slurries for CMP processing.
Material Slurry: solution Abrasive particles Selectivity
Metals and conductorsAlCu 150:1 Cu:SiO2
W Ferric nitrate, potassium phosphate Silica or alumina 120:1 W:SiO2
Poly Si
Dielectric materialsSiO2 Alkaline solution KOH Silicasilicon nitridepolymer
Page 19
CMP: polishing mechanisms and technology.CMP: polishing mechanisms and technology.Compliant nature of polishing pad is important for selectivity of material removal.
100
SEM of polishing pad.
Page 20
End point determination or detection.
Polish for predetermined time.Polish for limited time, measure, estimate remaining time.Monitor of motor current.Back side optical monitoring (infrared through silicon).Front side optical measurements
laser interferometer (“in-situ removal monitor” or ISRM).
Multiple wavelength reflectometry.
Page 21
Electron micrographs: CMP polishing pad conditioning disk.
SEM micrographs of a new diamond disk (tilted view) before pad conditioning [A], a new diamond disk (top view) afterpad conditioning [B], and a conventional diamond disk (tilted view) before pad conditioning [C].
Page 22
CVD SiO2
Silicon nitrideSilicon
Silicon nitrideCVD SiO2
Silicon
Example: CMP of CVD SiO2 in STI process.
Page 23
CMP defect examples.
Page 24
CMP equipment: general layout.
Page 25
Intel 0.18 micron technology IBM 1000 MHz Wafer
Starting point for assembly and packaging: the wafer.
Page 26
Modern wafer dicing machine.
Page 27
Conventional lead-frame package.
Page 28
Wire bond interconnection: thermo-compression.
Page 29
Typical wire bonds – thermocompression on chip.
Page 30
Electron micrographs: ultrasonic wire bond on chip.
Page 31
Wire bond detail: example.
Wire-bond advantages:Wire absorbs the mismatch between Si chip and PCB.Technology is very mature and automated.
Wire-bond disadvantages:Wire-bonding is complex mechanical process.Process time and complexity scales with number of interconnections:
6 bonds per second maximum rate today.Impractical for chip pin counts above 400 or so.
Page 32
Attachment Methodologies
• Wire Bond• Flip Chip• Tape
Automated Bonding
Page 33
• Can form many bonds at the same time
• One line of bonds on each side only, no double row.
Tape Automated Bonding
Page 34
Flip-chip interconnection.Flip-chip interconnection.Semiconductor chip
silicon tce=2 ppm/oC
Printed circuit boardpolymer, glass, copper tce=19 ppm/oC
PackagePackage purpose:
Conventional lead-frame package.
Page 35
Package configurations: DIP (dual in line package).Surface mount styles.
Page 36
Package configurations: DIP (dual in line package).
Surface mount.
Through hole mount.
Page 37
Quad flat pack package designs.
Page 38
Electronic Packaging Evolution:Quad Flat Pack
BGA-wire bondBGA-flip chip
Chip scale pkg.Chip on board
AlliedSignal Substrate Technology & Interconnect
Costa Mesa, California
ASTI: AlliedSignal’s new electronic packaging initiative
Packaging technologies:QFP: quad flat packBGA: ball grid arrayflip BGA: flip chip BGACSP: chip scale packageLDI: local density interconnect
Page 39
Flip-chip bonding: an alternative to wire bonding.
Wirebond BGA package.
Flip-chip BGA package.
Page 40
Solder bumps on package for flip chip mounting – 900 pin.
After reflow.
Before reflow.
Solder is screen-printed on package.
Typical reflow temperature is 180oC – 240oC.
Page 41
Flip-chip bonding: an alternative to wire bonding.
Wirebond BGA package.
Flip-chip BGA package.
Page 42
Example of stress in flip-chip interconnection.
Ceramic package.
Center of package Edge of package
Page 43
Advantages of flip-chip bonding:Parallel process – all interconnections formed in one process.
Disadvantages of flip chip bonding.Stress during processing due to thermal expansion mismatch can be a problem for large die (>18 mm).Metal solder bumps must be created on chip or package or both.Underfill polymer required in most cases.
Flip-chip bonding: Summary.
For all high technology devices (pin count above 400 leads), flip chip bonding is the interconnection medium of choice.
Page 44
Packaging Evolution
Outer lead pitchCircuit line / space.Via diameter
0.6 mm100 m125 m
1.3 mm100 m125 m
1.0 mm75 m50 m
0.5 mm50 m38 m
0.25 mm20 m25 m
0.15 mm15 m15 m
Materials RoadmapReinforcementThicknessPolymer: TgMoisture
Woven fiber100 micron1800C1.5%
Nonwoven microfiber50 micron2200C0.5%
Nonwoven microfiber35 micron3000C0.25%
Quad FlatPack
Advanced BGA Chip Scale Pkg Local DensityInterconnect.
4.5 cm.
Multiple chips
4.5 cm.
2.0 cm1.5 cm. 1.0 cm. 0.8 cm.
1998 2001 2004
UltraStableTM Technologies
Page 45
Chip Pitch Trends
0
50
100
150
200
250
1995 2000 2005 2010 2015
Dim
ensi
on (m
icro
n)
chip pitch-wire bondchip pitch TABchip pitch-flip chip
Semiconductor chip pitch trends....
Data from SIA National Technology Roadmap for Semiconductors, 1997
• Fundamental interconnection on-chip pushing toward 50 micron dimension.
• Flip chip dimension shrink will challenge technical capabilities.
• Wire bond and tape automated bond are being displaced with flip-chip interconnection.
IC chip
PWB
Package
Chip-Package Interconnect
Package-PWB Interconnect
IC chip pitch
Page 46
Interconnect density
0
500
1000
1500
2000
2500
1996 1998 2000 2002 2004 2006 2008 2010 2012
pins
/sq
inch
BGA pins per sq inch-high performance
Data from SIA National Technology Roadmap for Semiconductors, 1997
Chip to package interconnection density trends:
QFP BGA flip BGA CSP LDIpackage pin density (pin/sq.in.) 200 500 750 1100 1300Significant commercial impact 1996 1998 2001 2004 2007
Packaging technologies:QFP: quad flat packBGA: ball grid arrayflip BGA: flip chip BGACSP: chip scale packageLDI: local density interconnect
Page 47
0
20
40
60
80
100
120
140
160
180
200
1995 2000 2005 2010 2015
Pad
Size
(mic
ron)
high densitypad size(micron)
Data from SIA National Technology Roadmap for Semiconductors, 1997
0
5
10
15
20
25
30
35
40
45
50
1995 2000 2005 2010 2015
Line
wid
th (m
icro
n)
high densityline width(micron)
• Micro-via technologies will be required to obtain density.
• Mechanical drilling incapable of providing density, size.
• Laser drilling will dominate micro-via.
• Microvia capability enables high density interconnect, but has limits.
Conventional printed wiring technology cannot satisfy customer needs for packaging interconnect density.
Conventional printed wiring technology cannot satisfy customer needs for packaging interconnect density.
Trends in dimensions for high density circuitry....
Page 48
• Market is expanding rapidly, especially in critical flip-chip, BGA, and chip-on board products.
• Market is undergoing paradigm shift in package technology.
• Market is expanding rapidly, especially in critical flip-chip, BGA, and chip-on board products.
• Market is undergoing paradigm shift in package technology.
Worldwide Trends in Packaging Technology
0
20
40
60
80
100
120
140
1980 1985 1990 1995 2000 2005
Bill
ions
of I
nteg
rate
d C
ircui
ts
COB. flip chipBGA,CSPPGA,SIPSMTTABP-QFPDIP
Source: Amkor/Anam quoted in Advanced Packaging, February, 1998
Trends: market growth for electronic packages
High growth
Slow growth or shrink
Page 49
Increased pin count and reduced package dimensions require paradigm shift in interconnection.
Only a limited number of known feasible approaches can provide the high density interconnect needed.
1990 1994 1998 2002 2006 2010Year
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Inte
rcon
nect
ions
per
squ
are
inch
file: roadint4.axg revised 05/18/98
SIA Roadmap BGA 1997
ICP Roadmap 1997
Leading edge PWBCommodity PWB
State of art PWB
Unmet customer need
• SLC (surface laminar circuit) IBM, Japan
• ALIVH (Matsushita, Japan)
• Layer Pair ASTI
Semiconductor roadmap.
Printed Wiring board roadmap.
Technologies with known capability to satisfy need:
Page 50
Electrical Testing
• Probe Station
• Hot Probe• (Polarity tells doping)
Page 51
Probe Station
• Available in different level of automation.
• Probes generally individual items
• Test electronics separate
Page 52
Automatic Testing SystemParallel Computing Environment.- Runs testing algorithms.
Engineering Station- Debug Display- Productivity Monitoring
Universal Manipulator
- To adjust for attachment to other equipment
Test Head- Capable of digital
and analog signals
Page 53
What does a tester do?It is used at two places in the assembly line:• Front-End: Before the wafer is diced (cut)
• The test head will be pointed down and each die will be brought into contact with a the probes by a wafer handler.
• Non-conforming die’s are inked so that they are not further processed.
• Typically, this test is a sub-set of a full test.• Back-End: The last thing before it is shipped
• This is done after the chip has been bonded and packaged.
• Chips are fed one by one into a socket that uses the same pins that will be used in the field.
• This is a full test of all functionality.
Page 54
Types of Tests
• Analog signals• Digital signals• Often parallel tests on many pins,
complex test routines!• Time critical step/can take very long
Page 55
Metrology Tool
Optical or Electro-Optical Imaging System, that detetcs defects such as dust, incomplete or unwanted connects, etc. using pattern recognition
Page 56
Metrology Tool
• KLA-Tencor eS20
Page 57
Why electro-optical ?
• Today’s devices have features less than 0.15 micron
• Optical devices catch only 25% of killer defects
• Voltage variation can provide chemical contrast
Page 58
Defect Detection
Page 59
Combination Metrology Tools
Combination of optical and electro-optical tool common.
SEM Optical Defect Inspection
Page 60
Auto Defect Classification (ADC)
ADC classifiesdefect images filedwith the ADC server,with reference tothe classified andrecorded defect data
Page 61
Time of Flight Secondary Ion Mass Spectrometry
Time of Flight Secondary Ion Mass Spectrometry(TOF-SIMS)
high sensitivity- high transmission (Uex, ap, Eacc)
atoms <50%, molecules <100%- parallel mass detection
high mass resolution>10 000 for Tp<1 ns
high mass accuracy(1-10ppm)
high lateral resolution<100 nm at low mass resolution<500 nm at high mass resolution
high mass rangeup to 10 000 u
Page 62
The Applied Technique
Principle Modes of Operation
1. Surface Spectroscopy (static SIMS)Application of very low primary ion dose densities quasi non-destructive surface analysis
2. Surface ImagingRastering of a finely focussed ion beam over the surface mass resolved secondary ion images (chemical maps)
3. Depth ProfilingApplication of high primary ion dose densities successive removal of top surface layers elemental in-depth distribution
Page 63
Trace Metal Detection
Detection Limits with TOF-SIMSarea analyzed: 100 x 100 µm2
(one monolayer: around 1015 atoms/cm2)
Element Detection limit (atoms / cm2)Li 1 x 107
B 1 x 107
Na 1 x 107
Mg 1 x 107
Al 1 x 107
K 1 x 107
Ca 1 x 107
Cr 1 x 108
Mn 5 x 108
Fe 5 x 108
Ni 5 x 108
Cu 5 x 108
Page 64
TOF-SIMS Instrument
Page 65
Microscopy challenges from mm to nm
Page 66
Package cross-section overview
1 mm
Page 67
Pb-Sn solder bump between package and die
package
bump
die
100 microns
Page 68
0.13u Process Technology6-level Cu Metallization
ILD
M6
M5
M4
M3
M2
M1
MOSIsolation Transistor gate
gate
source
drain
100 nm
Page 69
1997 process
2003 process
Page 70
P1264“65nm node”
~40nm gatelength
P1262 “90nm node”~65nm gatelength
NMOS
Concern: Sample prep is harder both planar and cross-section
Page 71
M7
M6
M5
M4
M3
M2
M1
Metal Wire Interconnects
6.5 microns
5.6 microns
130nm node
90 nm node
Page 72
0
10
20
30
40
50
60
0 10 20 30% Increase in IDSAT
% In
crea
se in
I DLI
N
Increasing Strain
XRD data
Xiwei’s strain Electron Diffraction
From A 90nm High Volume Manufacturing Logic Technology Featuring
Novel 45nm Gate Length Strained Silicon CMOS Transistors IEDM 2003 by T. Ghani et al.
Epitaxial layer induces a large uniaxialcompressive strain in the channel region,
thereby resulting in significant hole mobility improvement.
Replacing S/D with epitaxial film improves performance without shrinking geometry
Page 73
Blanket films: strain measured by XRD
-0.8 -0.6 -0.4 -0.2 0.0 0.2
100
101
102
103
104
105
106
¢ µ (deg)
Inte
nsit
y (c
ps)
Layer
Thickness (Å) Ge composition (y)
Si --- --- SixGey 1752 17.63 SixGey 3133 Linear grade to 0 Si 4531 ---
Si
Ge
Si1-xGex = 5.431 + 0.20x + 0.027x2
Page 74
Why Cu + CDO?
• Resistivity: 1.7 vs. 2.7 ohmcm
• Dielectric constant: CDO 2.8 to 3.2 SiOF 3.7 SiO2 4
• Reliability: Cu interconnects that will last for 7 years would last about 26 days if they were made of Al(Cu) with doping and shunts.
020406080
100120140
0 200 400 600 800 1000 1200 1400
Pitch (nm)
RC
(ps/
mm
2)
180 nm Al + SiO2
130 nm Cu + SiOF
90 nm Cu + CDO
Page 75
Barriers chosen based on performance on flat wafers
Si
CuBarrier
Anneal
Si
CuSiBarrier
SiN
SiN
/ nmDepth10 20 30 40 50 60 70 80 90 100 110
1810
1910
2010
2110
[ato
ms/
cm3]
Con
cent
ratio
n
Mass
W334A1.TFD
90.91
W340A1.TFD
90.91
W657A1.TFD
90.91
“barrier 1”
SiN
Cu
BAR
Si
Barrier 2
Barrier 3 Formation of Cu silicide reaction product used to determine global barrier integrity