Interconnect Estimation for Fpga's

8/10/2019 Interconnect Estimation for Fpga's

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INTRODUCTION

As density increases placement and routing for FPGAs need more

careful attention to achieve successful design closure.

Interconnect during the design stage is the process of predicting the

routing resource requirement that the design may pose at the laterstage.

The design stage at which the estimation is done determines the

reliability and accuracy that is demanded of the estimation method.

The estimation at this stage should track modern back end routers

so that the design meets the requirements.


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Contd

Densityit refers to the number of logic componentssize which includes interconnected wires.

This is also a problem of custom and application specificcircuit design.

There are more number of problems like confidence ofroutability, good performance, total mapping time and

more.

But apart from all these we need to give importance towireability of circuit in FPGAs


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CONTD

A postplacement interconnect prediction method should

comply with the result of well known routers.

For this an algorithm need to be developed whichclosely match with the arbitrarily good router.

Here we derive a new interconnect estimation method

which is very reliable and gives very close estimation.

The advantage of this algorithm is it deals with very low

execution time overhead.


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PRIOR WORK

Interconnect estimationEstimation of total wire

length of a circuit

Rents rule (establishes link between number of pinsand number of logic blocks)

NP = KPNg

where NP number of pins

Ngnumber of logic blocks

KPaverage number of terminals per logic gates

Rents exponent


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PRELIMINARIES

FPGA architecture

Logic blocks are marked L

Connection boxes C

Routing matrix composed of routing channels and switch boxes.

Each routing channel consists of number of routing tracks.

The number of tracks in a channel is called track width W.


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PRELIMINARIES


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VPR : FPGA physical design

tool suite

It is capable of targeting a broad range of FPGA architecture based

on island a style architecture.

It consists of techmapper,a placer and a detailed router.

The placer in VPR is simulated annealing based and optimizes a

cost function consisting a wirelength estimate among other things.

It is based on path finder negotiated congestion algorithm.

It produces very tight results for placement and routing.


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ROUTER CHARACTERIZATION

To come up with good routability-estimation methods, the routing

process has to be satisfactorily characterized.

Rentsrule gives the relationship between the routability of a circuit

netlist with respect to a given routing graph.

From the interconnect-estimation point of view, the demands placed

on the routing elements by the router for successfully routing the

netlist is predicted.

By satisfactorily predicting these demands, we can estimate the

interconnect requirements of the design on the given FPGA device.


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Router Preliminaries

Routingis the process of assigning routing elements on the device to

individual nets in the netlist such that some cost function is optimized.

Commonly used cost functions include wirelength, critical path delay,

congestion, crosstalk, transmission line effects, etc.,

The routing process is broadly classified into

Global routing

Detailed routing

Global routers operate on a coarser routing graph with each vertex

representing many routing elements on the device. Global routers aretypically used to estimate wiring requirements and in interconnect

planning.

Detailed routers operate at a finer level, on a track by- track basis.

detailed routers are used to perform the actual routing.


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Rout ing prob lem

Given a routing graph G(V,E) and a netlist N, for each net nk N, find

route Rk G, such that some cost function is optimized and the

capacity constraints are met on all the routing elements vi V,0 i< |V |,

of the device.

Most routers employ some form of a heuristic to produce valid routes for

all the nets. The most commonly employed heuristic is maze routing,

which is basically a shortest path finding algorithm with obstacle

avoidance.

Many improvements that involve rip-up and retry schemes have been

proposed to the original maze-routing heuristic, all these methods are

dependent on the order in which the nets are ripped up and rerouted.


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Contd..

Coarse graph expansion (CGE) uses a different approach to arbitrate

congestion among nets.

Routing elements are allotted to those nets that place a higher demand,

which is computed by enumerating all possible paths on a coarsened

routing graph. McMurchie and Ebeling proposed an iterative routing heuristic called

PathFinder that resolved unroutes in an automatic manner without

relying on any specific net-ordering scheme. The method performs a

trade-off between congestion and delay in an iterative manner.

The method performs a trade-off between congestion and delay in aniterative manner. The PathFinder method is considered to be one of the

best routing frameworks and is widely used.


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Routing Flexibility and Routing

Demand

During the entire routing process, the router tries various routes for a

net, involving different routing elements.

Routing process and routing iteration are distinct, the routing process is

made up of a number of individual routing iterations. Each routingiteration is followed by a rip-up stage, where some or all the routes

computed in the previous routing iteration are removed.

Hence, Routing flexibility is defined as the total number of alternative

routes available to connect a net. At the end of the routing process, thenet is assigned a route from the set of all possible routes.


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Contd..

The routing-demand concept was introduced by Brown in CGE routerwork.Each net raises a certain routing demand on the routing elements

used by its paths.

This routing demand is a function of the routing flexibility and the

distribution of the routes. If P is the set of all possible routes for a net,and Pj P are those routes that use the routing element vj , then the

routing demand on vi due to the net is defined as.


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Expression for Routing Demand

Consider a net nkwith terminals TkG. Without loss of generality, the

process of routing this net can be considered to be made up of individual

steps of reaching each of its terminals. Consider the event of reaching

one of the terminals tkiTk, from a distant imaginary point (representing

the partial route of the net involving all the other terminals that have

already been reached). Let the vertex ViV represent the terminal tk

i on the routing graph G.

Consider any other routing element VjV. The distance lijis defined as

the shortest distance on the routing graph between Vi and Vj. This can

be determined by doing a breadth-first traversal of G starting from Vi,

until Vjis reached. The set of all routing elements at the same distance q= lijfrom vi is defined as the level set L

iq.


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Contd..

Theorem 1: If all possible unique paths of large lengths, originating from

a vertex vi G and expanding outwards, were to be enumerated, then

the ratio of the number of paths that contain any vertex Vj to the total

number of paths, will be at least 1/|Liq|, where q is the distance between

Viand Vj.

Proof: Let vi be the root vertex. Consider all the vertices at somedistance q from vi. The level set at q is then Liq. The number of vertices

in Liq is the number of alternative routing elements available for paths

coming in from distances greater than q. Let q+1 be the total number

of paths at distance q + 1, all of them proceeding towards vi. Since the

paths are all equally distributed about the periphery of the level q, theyare also equally distributed over the vertices in Liq. Hence, each vertex

in Liq will be used by q+1/|Liq | paths. Hence, the ratio of the number

of paths using a vertex in Liqto the total number of paths is 1/|Liq |.


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FAST GENERIC ROUTABILITY ESTIMATION FOR

PLACED FPGA CIRCUITS (fGREP) FORMULATION

fGREP directly operates on multiterminal nets to produce routingdemand values on every routing element of the device.

Demands Due to a Terminal of a Net:-

Let TDkijrepresent the terminal demand, due to a terminal tk

iTk, on

a routing element Vi at a distance lij= q. The terminal demand on the

routing element Vjis then


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Contd..

Figure shows the terminals and the bounding box of a two

terminal net on the FPGA layout. The terminal demands on the

channels due to each of the terminals is also shown. The terminaldemands are obtained by considering only those channels inside

the bounding box. The number of channels |Lq| in each level q are

calculated using a breadth-first search and the terminal demands

for all the channels in that level are assigned 1/|Lq|. The demand is

zero for all other channels outside the bounding box.


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Contd..

Demands Due to a Net: Interaction of Multiple Terminals:- The process of routing a net involves reaching all its terminals.At every

routing element, the terminal demands due to all the terminals have to be

considered for the net demand.

The terminal demand of a terminal that is nearer to a particular routing

element Vjwill dominate the demands due to the other terminals that are

farther away from Vj. This has the effect of creating regions of influence

around each terminal, where it contributes the most to the nets routing

demand.

The expression for the net demand on a routing element Vjdue to a net

nkis then


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Contd..

The routing demands of each channel aremarked next to the channels. The entries in

regular typeface are those due to terminal t1

and those in boldface are due to terminal t2.

The entries with circles on them are

equidistant from both the terminals.

Maximum of the demands is assigned due totwo terminals for them, which in this case

happens to have the same value of 1/9.

The sizes of the level sets for q = 1, 2, 3, . . .,

for the terminals T1, T2, subject to the

bounding-box constraints are given by


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Contd..

The terminals are labelled as T1, T2, and

T3. The routing demands on each channeldue to the net are marked next to the

channels. The entries in italics are due to

T1, those in boldface are due to T2, and the

normal typeface entries are due to T3. The

entries with little circles on them are

equidistant from more than one terminal andgot assigned the higher of the terminal

demands. The regions of influence of each

terminal are also shown. The sizes of the

level sets for q = 1, 2, 3, . . ., for the

terminals T1, T2, and T3, subject to the

bounding-box constraints are as follows:


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Contd..

Interaction of Multiple Nets

The routing demand on a routing element Vjdue to all the nets inthe netlist is the sum of the net demands due to every individual net.

The terminal demands due to all the terminals of all the nets are

calculated by performing a breadth-first traversal of the routing graph

with the terminal Vias the root vertex. At each step of the traversal, the

level set is enumerated and the demands are assigned.

Total WirelengthTotal wirelength is defined as the sum of the wirelengths of all

the nets in the design. Total wirelength is also the sum of all the tracks

used in the device.


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Improving Runtime Efficiency

The runtimes of fGREP are high for

large circuits with many high-fanoutnets. If Bk is the set of routing

elements in the bounding box of a net

nk, and Tk the set of terminals, then

the runtime is proportional to |Bk|

|Tk|.Typically, high-fanout nets spanthe entire device, and hence, add a

severe penalty to the fGREP

runtimes. This effect is clearly

illustrated in Figure which plots the

average fGREP execution time pernet against the number of terminals in

the net, for a few standard benchmark

circuits.


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Zone-Limited Search

The level sets are identified by performing a breadth-first search from each

terminal of a net. At each step of the search, the current elements form a

wavefront, which then expands outwards. By limiting the search to within the

terminalszone alone, fragmenting and clipping of the wavefront can occur.

An arbitrary five-terminal net with terminals {Ti},

1 i 5, is shown. The wavefront for the

terminal T1, at some arbitrary distance q fromT1, is shown by the dotted line. The zones are

marked by solid lines. The wavefront W of T1 is

divided into four arcs, two of which (W1 and

W3) are inside T1s zone, while the other two

(W2 and W4) are outside the zone. According

to fGREP, the cardinality of the level set at thisdistance will be |W1| + |W3|, which is far less

than that of the complete wavefront. This will

produce very high terminal demands for the

routing elements on this wavefront, which is

clearly erroneous.


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Zone-Limited Parallel Search

To overcome the wavefront clipping and fragmenting effects describedabove, the complete wavefront has to be maintained at all stages.

A simple yet effective solution to the problem is to maintain the complete

wavefront for the terminal as long as at least one routing element on the

wavefront is still contained in its zone.

If at any point all the elements on the wavefront of a terminal are outside

its zone, i.e., no element on the wavefront got its terminal demand from

this terminal, then zone is completely discovered and we stop the search

for that terminal. This process terminates when the zones of all theterminals are discovered.


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Contd..


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Conclusion

This paper proposes a new model to characterize the operationof modern routers and used it to formulate an interconnect estimation

method for placed FPGA circuits. This estimation method is

architecture independent and is able to produce both global and local

wiring estimates. Estimates match very closely with VPRs detailed

router on both global and local levels. The estimation errors of thismethod are very small, of the order of one track per channel over the

entire device. The runtime overheads of method are also very low,

thus making it ideal for deployment in regular FPGA physical design

flows.


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Thank you

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Interconnect Estimation for Fpga's

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