EE695K VLSI Interconnect
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Interconnect Modeling
Modeling of Interconnects
• Interconnect R, C and L computation• Interconnect models
– Lumped RC model– Distributed circuit models– Higher-order waveform in distributed RCL trees
• Accuracy and fidelity
EE695K VLSI Interconnect
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Interconnect Resistance Computation
WLR Resistance ⋅r
rR
L
W
Maxwell’s Equation of Differential Form
ρε =⋅⋅∇ )( E
zzyyxx nnn vvv∂∂
∂∂
∂∂ ++=∇
• Maxwell’s equation for static electric field:
– In Cartesian coordinate system, gradient operator is
– ε: permittivity of the field region– E: strength of electric field– ρ: charge density of the field region
EE695K VLSI Interconnect
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• Base on , the Posisson’s equation is
– ε: permittivity of the field region– E: strength of electric field– ρ: charge density of the field region
Poisson’s Equation
ρε =⋅⋅∇ )( E
ψ− ∇=E
ρψε −=∇⋅⋅∇ )(
• If assume ρ = 0 and homogenous dielectric, potentialψ satisfies Laplace’s equation
– is Laplacian operator– In Cartesian coordinate system, Laplace’s equation is
Laplace’s Equation
ρψε −=∇⋅⋅∇ )(
0)( 2 =∇⋅=∇⋅⋅∇ ψεψε
02
2
2
2
2
2
=++∂∂
∂∂
∂∂
zyxψψψ
2∇=∆
0=∆ψ
EE695K VLSI Interconnect
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Exact Extraction of Resistance
• Solving Laplace’s equation, ∇2 Ψ = 0• Relaxation method:
– Potential at every point is the average potential of itsneighbors
– Consider square grids
[ ]4/)1,()1,(),1(),1(),( −+++−++= yxyxyxyxyx ψψψψψ
– Point on an edge, mirror the potential about the edge, e.g.,right vertical edge
[ ]4/)1,()1,(),1(2),( −+++−= yxyxyxyx ψψψψ– Repeatedly replace the potential of all points with the
average of their neighbors
Equipotentials and Current Flow
Current flow potential
EE695K VLSI Interconnect
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Break Lines for Various Shapes
Potential Distribution for Parallel and DiagonalContacts
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Equivalent Perpendicular Contacts
2/
),min(
p
crp
l
lWl
=∆=
4/
),min(
p
crp
l
lWl
=∆=
All lines are rectilinear or diagonal (45º)
WLR =
WL
R =
14WL4L
R+
=12WL
2LR
+=
L
W
W
L
L
2W
1W 1W
L
2W
Resistance Computation for Non-rectangularShapes
[Horowitz-Dutton, T-CAD July 83]
EE695K VLSI Interconnect
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Calculating the Resistance of a Convex Region
Resistance Computation for Non-rectangularShapes (cont’d)
Shape Ratio Resistance
A 1 1 A 5 5
B 1 2.5 B 1.5 2.45 B 2 2.55 B 3 2.83
C 1.5 2.11 C 2 2.3 C 3 2.66 C 4 2.97
D 1 2.25 D 1.5 2.28 D 2 2.43 D 3 2.74
E 1.5 1.44 E 2 1.8 E 3 2.33 E 4 2.71
WLRatio =
L
W
A 2
1
WW
Ratio =
2W
1W
1W2W
B
2W
1W1W
2W
2
1
WWRatio =
C
1W
1W
2W
1
2
WWRatio =
E
2W
2W1W
1W1
2
WWRatio =D
EE695K VLSI Interconnect
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Accuracy of Resistance Extraction
Exact resistances are obtained by solving Laplace’s equation
Shape Ratio Extracted Exact %ErrorResistance Resistance
A 1 1 1 0 A 5 5 5 0
B 1 2.5 2.5 0 B 1.5 2.45 2.55 4 B 2 2.55 2.6 2 B 3 2.83 2.75 3
C 1.5 2.11 2.1 0 C 2 2.3 2.25 2 C 3 2.66 2.5 6 C 4 2.97 2.65 11
D 1 2.25 2.2 2 D 1.5 2.28 2.3 1 D 2 2.43 2.3 5 D 3 2.74 2.6 5
E 1.5 1.44 1.45 1 E 2 1.8 1.8 0 E 3 2.33 2.3 1 E 4 2.71 2.65 2
Current Spreading from a Small Contact
EE695K VLSI Interconnect
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Material Min. Typical Max.Metal[Al] 0.03 0.05 0.08Silicides 2.00 3.00 6.00Diffusion (n+ and p+) 10.00 25.00 50.00Polysilicon 15.00 50.00 100.00
Typical sheet resistance for conductorsSheet Resistance Ω /SQ.
What’s Capacitance?
• Simplest model: parallel-plate capacitor– It has two parallel plates and homogeneous dielectric
between them– The capacitance is
• ε: permittivity of dielectric• A: area of plate• d: distance between plates
– The capacitance is the capacity to store charge• charge at each plate is• one is positive, the other is negative
CVQ =
dAC ε=
++ +
+
- - -
-
+Q -Q
EE695K VLSI Interconnect
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General Picture
• For multiple conductors of any shapes and materials,and in any dielectric, there is a capacitance betweenany two conductors
• Mutual capacitance between m1 and m2 is C12 =q1/v2
– q1 is the charge of m1
– v1 = 0 and v3 = 0
m1
m3
m2
c23
c13
c12
Capacitance Matrix
• Capacitance is often written as a symmetric matrix
m1
m3
m2
c23
c13
c12
C = -c21 c22 -c23
-c31 -c32 c33
c11 -c12 -c13
)(1
ijccm
jijii ≠= ∑
=• is the self-capacitance for a conductor,
– e.g., c11 = c12 + c13
Tmmmm VCQ )(=• The charge is given by– e.g.,
)()( 31132112
3132121111
vvcvvcvcvcvcq
−+−=−−=
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Physical Design Domain
• Conductors: metal wire, via, polysilicon, substrate• Dielectrics: SiO2 ,...
• Total cap for a wire– delay, power
• Mutual cap between wires– signal integrity
victim victim
cross-section top-view
3D Model
• 3D model– Wires with finite width, thickness and length– Compute self-cap and mutual cap
3D model
• 2D model– Wires with finite width and thickness, but infinite length along
the 3rd dimension– Compute the unit-length cap (also called cap coefficient)
2D model
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Approximation of 3D Structure by a 2D Model
• Pick a 3rd dimension
3rd dimension
L2
L1
L3
3rd dimension
• Chop 3D structure into sections with distinguishprofiles
Approximation of 3D structure via 2D Model
• Solve each distinguish profile via 2D model– two types of profiles with unit-length cap c1 and c2
L2
L1
L3
3rd dimension
Type I:
Type II:
• Total cap is c1(L1+L3)+c2L2
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Approximation via Quasi-3D Model
• 2D model + effects of sidewalls along the 3rddimension– a correction capacitance for each sidewall
Classification (orthogonal to 3D/2D)
• Numerical method– accurate– any geometric structures– extremely expensive
• Formula-based method– efficient– limited accuracy and geometric structures– insight into dependency on design parameters
• Table lookup– accuracy -> numerical method– efficiency -> analytical method– More flexible handling of geometric structures than
analytical method
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Framework for Numerical Method
¶ Assume voltage [0, 0, … , 1, … , 0], i.e., onlyconductor i has unit voltage
Ë Compute charge qj for every conductor jÌ Obtain mutual cap cij =qj, and self-cap (sum of mutual
cap)Í Iterate through steps 1-3 using different voltage
assignments
Cmm =0 -c12 0 0
-c21 c22 -c23 -c240 -c32 0 00 -c42 0 0
0 1 0 0Vm =
m2
m1m3
m4
c21 c23
c24
victim
Solutions to Conductor Charge
• Differential-based– use Maxwell’s equation in differential form
• Integral-equation based– use Maxwell’s equation in integral form
EE695K VLSI Interconnect
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Capacitance Extraction - Electrostatic Analysis
• For m conductors solvem potential problems forthe conductor surfacecharges
• Each problem has oneconductor at 1V, the restat zero potential
Two Views of Capacitance
• Set up a system of charge neutrality equations
• Solve for V and q, then C12 = q
Can derive C12 from C12, C1∞, and C2∞
01
12212
12121 =
−
+
+
+−−+∞
∞
VV
CCCCCC
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Volume Methods -Finite-Differences/Finite-Elements
• Solve Laplace’s equation in the conductor exterior– Approximate derivatives by finite-differences– Conductors Provide potential boundary conditions– Voltage one on conductor 1, zero on conductor 2
• 2-D example
Conductor 1
Conductor 2
iψmψ
kψ
lψjψ
0))()((5.0))()((5.02
2
2
2
=−+−
−−
−−−
+−+−
−−−
−−
≈∂∂+
∂∂
jiik
ji
ji
ik
ik
liim
li
li
im
im
xxxxxxxx
xxxxxxxx
xx
ψψψψψψψψψψ
Volume Methods Generate Sparse Matrices
• One equation for each grid node• In 3-D, each equation involves at least 7 variables• Solve by matrix solution methods
– Sparse Gaussian Elimination– Incomplete Cholesky Conjugate-Gradient Method (ICCG)– Multigrid methods
EE695K VLSI Interconnect
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Two Different Boundary Conditions
• Closed box: Overestimates self C, underestimatescoupling C
• Open Box: Underestimates self C, overestimatescoupling C
Components of Interconnect Capacitance
• Classification based on profiles of interactinginterconnects– Area component
• Due to overlapping area of two interconnects on different layers
– Fringing component• Due to side-walls of an interconnect and the surface of an
interconnect on a different layer
– Lateral component• Due to side-walls of two interconnects on the same layer
EE695K VLSI Interconnect
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Capacitance: The Parallel Plate Model
SiO2
Substrate
H
W
L
tox
Electrical-fieldlines
WLt
Cox
oxε=int LL
wireC SSSSS =×=,
02
2
2
2
2
2 =++=∆∂∂
∂∂
∂∂
zyxψψψψLaplace’s equation is
21)( kxkx +=ψVkk =+⋅= 21 0)0(ψ0)( 21 =+⋅= kdkdψ
Vxx dV +−=)(ψ
V=)0(ψ 0)( =dψ
x
d
Parallel-Plate Capacitor
EE695K VLSI Interconnect
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Vxx dV +−=)(ψ
unit-area charge = dVx ⋅=∇⋅− εψε )(
unit-area cap = dε
parallel-plate cap = dAε
Parallel-Plate Capacitor
Typical Capacitance/Unit Area for 1µm CMOS
Interconnect Layer
Polysilicon to Substrate
Metal1 to Substrate
Metal2 to Substrate
Metal3 to Substrate
N+ Diffusion to Substrate (@ 0 Volt)
P+ Diffusion to Substrate (@ 0 Volt)
fF/µm2
0.058 ± 0.004
0.031 ± 0.001
0.015 ± 0.001
0.010 ± 0.001
0.36 ± 0.02
0.46 ± 0.06
EE695K VLSI Interconnect
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Fringing Capacitance
W
H
W - H/2H
+
Fringing Component Area Component
Fringing and Area Capacitances
−
+
+⋅++
⋅=oxoxoxox
ox t
HW
Ht
Ht
Ht
LC 2
22221ln
2πε
+
++
⋅=
5.025.0
06.106.177.0oxoxox
ox tH
tW
tW
LC ε
EE695K VLSI Interconnect
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Typical Fringing Capacitance/Unit Length for 1µmCMOS
Interconnect Layer
Polysilicon to Substrate
Metal1 to Substrate
Metal2 to Substrate
Metal3 to Substrate
fF/µm
0.043 ± 0.004
0.044 ± 0.001
0.035 ± 0.001
0.033 ± 0.001
Fringing-Field Effect
EE695K VLSI Interconnect
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Interwire Capacitance
Substrate
SiO2
Creates crosstalk
Level 1
Level 2
Coupling Capacitances
• Area component• Fringing component
– x0 measures how fringe capacitance varies for incrementallength of the fringing surface
• Lateral component
)( 0201 // xxxxffringingX eeLcC −−
− −××=x1
x2
dC lateralX
1∝−
EE695K VLSI Interconnect
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Interwire Capacitance for 1µm CMOS
Metal1 to Polysilicon
Metal2 to Polysilicon
Metal2 to Metal1
fF/µm2
0.055
0.022
0.035
fF/µm
0.049
0.040
0.046
Area Fringing
Impact of Interwire Capacitance
EE695K VLSI Interconnect
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Significance of Coupling Capacitance
0
0.2
0.4
0.6
0.8
1
0.25 0.18 0.15 0.13 0.1 0.07
Technology (u m)
Cx/Ctotal
Min. Spacing
2x Min. Spacing
Capacitance Crosstalk
fFCX 25=
For 5x5mm overlap of X and Y
fFC
fFC
fFC
XY
fringeXY
areaXY
9.1
049.052
055.055
,
,
=××=
××=
V
VCC
CV
XYX
XX
35.0
5
=+
=∆
Assume
EE695K VLSI Interconnect
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Coupling Noise
0
0.1
0.2
0.3
0.4
0.25 0.18 0.15 0.13 0.1 0.07
Technology (u m)
Lmax (mm)
10% Vdd min. Spacing
10% Vdd 2x min. Spacing
