International Electron Devices Meeting 2010

Summary and Outlook

Walter Snoeys – PH ESE ME – 2011 1

Some numbers ~1470 participants (about same level as 2009) 210 regular papers in 33 sessions over 3 days (somewhat less

in number) 555 papers submitted Paper acceptance rate = 35%

(acceptance of university papers low) Growing areas: design-device, packaging/3D, power devices,

energy solar…, bio 2 short courses:

15nm CMOS technology Reliability and Yield of advanced integrated technologies

Luncheon address J. Clifford (Qualcomm) : Evolution and Directions for Mobile Wireless Devices

Evening Panel Sessions: integration + power crunchWalter Snoeys – PH ESE ME – 2011 2

OUTLINE

CMOS

Lithography

Special devices

Metallization

Memories

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 3

CMOS in N-well technology

Walter Snoeys – PH ESE ME – 2011 4

N+N+P+ N+

N-well

P+ P+

B SS DDG

P-substrate

NMOS

BS

G

D

or G

D

BS

BS

G

D

B

G

D

SPMOS

The ‘real thing’

Mukesh Khare IBM

Walter Snoeys – PH ESE ME – 2011 5

Walter Snoeys – PH ESE ME – 2011 6

The real

thing

The MOS transistor: operation principle

Linear region (low Vds)

Electrons are attracted to SiO2-Si interface => conductive layer (channel) is created. (P-substrate gets inverted locally). The channel which links source and drain and forms a resistor between the two. Current increases significantly with increasing VDS

Walter Snoeys – PH ESE ME – 2011 7

n+ n+

SG

D

- - - -

The MOS transistor: operation principle

Saturation region (high Vds)

Significant current flow and resistive drop in the channel. Electrons near the drain are insufficiently attracted by the gate, and the channel gets pinched off. Beyond that point increasing VDS does not change current significantly.

Walter Snoeys – PH ESE ME – 2011 8

n+ n+

SG

D

Depletion layer

Note: before inversion layer is formed already current flow = weak inversion

Some examples of MOS characteristics

Walter Snoeys – PH ESE ME – 2011 9

Id=f(Vg) Linear scale

0.00E+002.00E-044.00E-046.00E-048.00E-041.00E-031.20E-031.40E-031.60E-03

-0.4

0

-0.1

0

0.2

0

0.5

0

0.8

0

1.1

0

1.4

0

1.7

0

2.0

0

2.3

0

Log(Id)=f(Vg) (Logarithmic scale)

1.00E-13

1.00E-11

1.00E-09

1.00E-07

1.00E-05

1.00E-03

1.00E-01

-0.40 0.05 0.50 0.95 1.40 1.85 2.30

Id=f(Vd)

0.00E+00

5.00E-06

1.00E-05

1.50E-05

2.00E-05

2.50E-05

3.00E-05

0.00 0.35 0.70 1.05 1.40 1.75 2.10 2.45

gm=f(Vg) (in linear regime)

0.00E+00

2.00E-05

4.00E-05

6.00E-05

8.00E-05

1.00E-04

1.20E-04

-0.35 0.10 0.55 1.00 1.45 1.90 2.35

The Boltzmann tyranny

Walter Snoeys – PH ESE ME – 2011 10

Log(Id)=f(Vg) (Logarithmic scale)

1.00E-13

1.00E-11

1.00E-09

1.00E-07

1.00E-05

1.00E-03

1.00E-01

-0.40 0.05 0.50 0.95 1.40 1.85 2.30

Ion

Ioff

Exp( )nkT/qVgs

Weak inversion

Strong inversion

Weak inversion slope ~ 60 mV/decade, Ion/Ioff=10e6 => 360 mV

Steep-slope devices (see session 16)

Tunneling (only over limited range) Floating body (hysteresis ! Potential in memories) Polarization in gate dielectric stack

Walter Snoeys – PH ESE ME – 2011 11

still really in development

Moore’s law‘The number of transistors per integrated circuit increases exponentially with time

(doubling roughly every two years)’

Walter Snoeys – PH ESE ME – 2011 12

More Moore and More Than Moore

Walter Snoeys – PH ESE ME – 2011 13

Walter Snoeys – PH ESE ME – 2011 14

More Moore and More Than Moore

How has Moore’s law been possible ?

How has Moore’s law been possible ?

K. De Meyer

K. De Meyer

Mobility enhancement (K. Kuhn) New materials (III-V) and Ge

High mobility but not in all valleys of the band, need to confine carriers to high mobility valley

Low Eg materials (eg Ge) can have higher Ioff due to band-to-band tunneling

Technological challenge: lattice mismatch and defect-free material growth on Si

Different orientations (no strain) On (100) PMOS best <100>, NMOS isotropic On (110) NMOS best <100>, PMOS best <110> Overall best : NMOS (100)<110>, PMOS (110) <110> Hetero Orientation Transistors (HOT)

Stress and Strain : apply strain to channel to change the energy band shape Reduce scattering Enhance mobility, reduce effective mass Pushing carriers in valleys with low effective mass,

Confinement

2008 Krishnamohan et al (session 36.5) PMOS

IEDM 2008 P. Packan et al. (Intel) Session 3.4

Stress improves PMOS and NMOS, but orientation change degrades NMOSConfinement limits this degradation -> Modeling ???

IEDM 2008 P. Packan et al. (Intel) Session 3.4

Confinement limits NMOS degradation -> Modeling ???

Lg = 160 nmReduction 40 %

Lg = 35 nmReduction 13 %

Note: also dependence on W…

‘Planar’ transistors (K. Kuhn)

Walter Snoeys – PH ESE ME – 2011 23Advanced spacer engineering for Cfringe: low k or removal

Going to 15 nm…

Walter Snoeys – PH ESE ME – 2011 24

M. Khare

Running out of steam in Bulk

Walter Snoeys – PH ESE ME – 2011 25

M. Khare

Reality more difficult than ITRS predictions

Walter Snoeys – PH ESE ME – 2011 26

Walter Snoeys – PH ESE ME – 2011 27

Reality more difficult than ITRS predictions

Orthogonal change in roadmap (T. Skotnicki)

Walter Snoeys – PH ESE ME – 2011 28

2009 ITRS Roadmap adjustments (T. Skotnicki)

Gate length scaling will be less aggressive than past roadmap predictions. Already included in 2008 with 3-5 year slow-down. Added another year in 2009.

Ring oscillator delay added to CV/I as more realistic metric (!)

Addition of PMOS saturation current

Subthreshold source-drain leakage currents are held constant

Criterion for source/drain parasitic resistance is set for 33% degradation vs ideal zero series resistance case

Walter Snoeys – PH ESE ME – 2011 29

Transistor performance metrics (T. Skotnicki)

Walter Snoeys – PH ESE ME – 2011 30

Importance of Drain Induced Barrier Lowering

Walter Snoeys – PH ESE ME – 2011 31

DIBL: new performance driver

Walter Snoeys – PH ESE ME – 2011 32

Walter Snoeys – PH ESE ME – 2011 33

Walter Snoeys – PH ESE ME – 2011 34

Who does better than bulk ? (T. Skotnicki)

Walter Snoeys – PH ESE ME – 2011 35

SOI: Why thin buried oxide ?

Avoid drain-to-channel coupling to reduce Short Channel Effects and Drain Induced Barrier Lowering

Walter Snoeys – PH ESE ME – 2011 36

Ultra Thin Body and Buried Oxide (UTBB)+ Body bias for tuning

Walter Snoeys – PH ESE ME – 2011 37

Can tune to system need !!

Less mismatch in SOI

Walter Snoeys – PH ESE ME – 2011 38

Mismatch and SRAM

Walter Snoeys – PH ESE ME – 2011 39

CMOS Ultrathin Body and Buried oxide quite some attention (ex

Leti/ST, paper 3.4.4):

Process papers on contact resistance, silicides, etc…

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ALTERNATIVE : FIN FET

Walter Snoeys – PH ESE ME – 2011 41

Significant challenges in manufacturing

Parasitics

Body bias more difficult

CMOS & Process Technology sessions CMOS

3: Ultra-thin Body Transistors and Device Variability 10: CMOS Performance Enhancing and Novel Devices 27: Advanced High-k metal Gate SOC and High

Performance CMOS Platforms 34: Advanced FINFETs and Nanowire FETs

Process Technology 2: Advanced 3D Integration 11: Channel Engineering and High-k Technology 18: Advanced Technologies for Ge MOSFETs and New

Concept Devices 26: Advanced Source/Drain and Channel Engineering 33: Novel Process Technologies

Walter Snoeys – PH ESE ME – 2011 42

Modeling and Reliability sessions Modeling and Simulation

8: High-Frequency and Multi-Gate Device Modeling 15: Challenges in Advanced Device Performance and

Variation Modeling 22: Simulation of Memory Devices 26: Simulation of Non-Silicon Materials and Devices

Characterization, Reliability and Yield 4: Front End of Line (FEOL) Reliability 28: RTN and Memory 35: Back-end SRAM and ESD Reliability

Walter Snoeys – PH ESE ME – 2011 43

Special session: technology and design17: Special Session – Confluence of Technology and Design –

Challenges for Non-Conventional Devices and 3D LSIs Through-chip interface as alternative to

Through Silicon Via (see below) Liquid cooling (EPFL) with regulation Transistors (see above): electrostatics & DIBL, parasitic

capacitance (corner + gate to contact capacitance), design with novel devices (Stanford)

May the fourth (terminal) be with you – circuit design beyond FinFET (AIST Japan), resistive connection to back gate

Variability and self feedback devices (Arizona) Circuits to interface with cells and molecules (Michigan)

Walter Snoeys – PH ESE ME – 2011 44

OUTLINE

CMOS

Lithography

Special devices

Metallization

Memories

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 45

Lithography (Sivakumar Intel)

Walter Snoeys – PH ESE ME – 2011 46

Rayleigh’s Equation

Walter Snoeys – PH ESE ME – 2011 47

€

Re solution = k1λ

NA

Walter Snoeys – PH ESE ME – 2011 48

Lithography (Sivakumar Intel)

“should maintain k1 above or equal to 0.3 for manufacturability”

Walter Snoeys – PH ESE ME – 2011 49

Lithography Sivakumar Intel

Now defect density on par with dry litho

Going to lower k1

Walter Snoeys – PH ESE ME – 2011 50

Going to lower k1

Walter Snoeys – PH ESE ME – 2011 51

Going to lower k1

Walter Snoeys – PH ESE ME – 2011 52

Going to lower k1

Walter Snoeys – PH ESE ME – 2011 53

Going to lower k1

Walter Snoeys – PH ESE ME – 2011 54

Dual pattern, pitch doubling etc…

Walter Snoeys – PH ESE ME – 2011 55

Changing λ -> Extended UV

Walter Snoeys – PH ESE ME – 2011 56

Steppers only becoming available now

Need special reflective masks, and need improvement on defect densities

Need at least 2x in light intensity to reach production grade volume

Immature photoresist

Walter Snoeys – PH ESE ME – 2011 57

Sivakumar Intel

Ultimately determined by cost

Walter Snoeys – PH ESE ME – 2011 58

OUTLINE

CMOS

Lithography

Special devices : emerging technologies

Metallization

Memories

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 59

Special devices sessions Quantum, Power and Compound Semiconductor Devices

6: Next Generation Digital Devices 30: Ultra High Speed Transistors

Solid-State and Nanoelectronic Devices 9: CNT, MTJ Devices and Nanowire Photodiodes 16: Low-Power and Steep Slope Switching Devices 23: Graphene Devices

13: Emerging Technologies: Next Generation Power devices and Technology

Walter Snoeys – PH ESE ME – 2011 60

Emerging technologies: AlGaN

Walter Snoeys – PH ESE ME – 2011 61

Several papers

Example:(30.1)

Record fT

HRL &

JPL laboratories

Emerging technologies: AlGaN

Issue is substrate availability, compatibility with Si if possible is huge advantage

Walter Snoeys – PH ESE ME – 2011 62

Samsung GaN epitaxial

films on 4” and 8” Si substrates

Emerging technologies: Ge & III-V

Several papers (like the previous one) on III-V structures and on strained Ge. Contact resistance issue for Ge NMOS

Several papers have been presented on Si substrate. Is an area which receives quite a bit of attention to improve standard CMOS

Walter Snoeys – PH ESE ME – 2011 63

Example 7.4: intel

Emerging technologies : GRAPHENE

Graphene is a 2D system, a single layer of carbon atoms.

Extreme electron mobility (200 000 cm2/Vs) Large hole mobility (~ 1500 cm2/Vs)

Interesting (early development) for fast electronics and fast photo detection

Contact resistance issue

Photon detection: need to create bandgap to reduce leakage, but excellent absorption and carrier transport (examining multilayers)

Walter Snoeys – PH ESE ME – 2011 64

Example:(23.1)

IBM

POWER DEVICES

13: Emerging Technologies: Next Generation Power devices and Technology

Significant production in Si Some special applications

requiring higher performance SiC GaN Not clear yet which one will

win or whether both will stay around

Walter Snoeys – PH ESE ME – 2011 65

Emerging technologies: Integrated photonics

Towards laser Strained Ge on SiDartmouth College & MIT

Optically pumped laser

and LED

Walter Snoeys – PH ESE ME – 2011 66

OUTLINE

CMOS

Lithography

Special devices : emerging technologies

Metallization

Memories

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 67

Metallization towards smaller pitches => need work on parasitics !!!

Walter Snoeys – PH ESE ME – 2011 68

Other metallization issues

Walter Snoeys – PH ESE ME – 2011 69

Dimension reduction Minimize sidewall/barrier/line edge roughness Intersection of pores with sidewall Patterning, cleaning and filling at nano-

dimensions Seed layers New materials/structures -> integr. complexity Increased number of layers

Thermo-mechanical issues Chemical Mechanical Polishing (CMP) Yield

Reliability Electromigration Stress induced voids Time Dependent Breakdown

Example (session 33.3): leakage between MIMcaps due to metal

penetration in pores

Walter Snoeys – PH ESE ME – 2011 70

3D (session 2) TSMC : Nice demonstration of

technology development, but date of full production unclear

IMEC+Japan: stress around via => keep-out zone for transistors

Chinese with IBM Chip fabrication where die can

be individually detached (DE) CEA – Leti – Minatec : various

substrates starting from original SOITEC technology, combined with TSV

Samsung

Walter Snoeys – PH ESE ME – 2011 71

Walter Snoeys – PH ESE ME – 2011 72

Walter Snoeys – PH ESE ME – 2011 73

OUTLINE

CMOS

Lithography

Special devices : emerging technologies

Metallization

Memories

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 74

Memories and Sensors sessions Memory Technology

5: Flash Memory 12: IT Magnetic RAM 19: Resistive RAMs 29: Phase Change Memory and 3-Dimensional Memory

Session 5: example Intel-Micron 64 Gb

Walter Snoeys – PH ESE ME – 2011 75

Flash NAND structures

Walter Snoeys – PH ESE ME – 2011 76

Work on vertical structures Scaling below 30nm requires significant work on the

transistors

Toshiba 2008

HYNIX

Non-Volatile Memories

Walter Snoeys – PH ESE ME – 2011 77

Already in 2007 more NAND and NOR flash memories shipped than DRAM in its entire history (1.9e18)

NVM now ~60 B$ market 80 000 $/GByte in 1987 (256kB unit) to 1.5 $/Gbyte (16Gbyte unit) in 2007 40% price drop per year (ahead of Moore’s learning curve of 30 % per

year) Litho, self-aligning, nand for less space, wafer size increase… Some ‘Partial’ 3D Now new possibility : cross-point memory

Cross-point memory

Walter Snoeys – PH ESE ME – 2011 78

Phase Change Memory: heating and then quenching, can be very small, can use Multi-level Cell (need PNV) and Multi-Layer Stacking. Ultimate question is cost.

RRAM: based on simple or more complex oxides which change conductive state, need more work on reliability and understanding of mechanism

IEEE Spectrum dec 2008

Programmable Metallization Cell

Normally in combination with switch, although recently some without

Cross-point memory

Walter Snoeys – PH ESE ME – 2011 79

Spin Torque Transfer RAM infinite endurance and high speed

Work to reduce cell size but there are good perspectives (HYNIX 54 nm, Samsung perspectives for 30nm)

Increase cell transistor drive current and reduce magnetic tunnel junction switching current

HYNIX

IBM : yields ok for 64 Mb

OUTLINE

CMOS

Lithography

Special devices

Metallization

Memories

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 80

DISPLAYS, SENSORS and MEMS

7: MEMS Resonators: used as frequency references

Walter Snoeys – PH ESE ME – 2011 81

Panasonic/IMECQ>200 000 @ 20 MHz

UC Berkeley

DISPLAYS, SENSORS and MEMS 14: Image sensors

Walter Snoeys – PH ESE ME – 2011 82

14.3. Single Photon Avalanche

Diode with no afterpulses

(Toyota)

21: Thin Film transistors 31: PV (solar cells) and Energy Harvesting (vibration and

photovoltaic) 36: Biosensors and MEMS

CONCLUSIONS CMOS : according to some (!)

Bulk running out of steam (many tricks already done and now DIBL)

Ultra Thin Body and Buried oxide is good alternative for some time to come

Lithography For 15 nm need advancement on EUV or need to work

with double pattern (in combination with computational lithography). Ultimately a question of cost.

Special devices Intensive work to prepare improvement of MOS, some

things (Ge) already included

Metallization :

need reduced parasitics but porous low k is a challenge

Memories

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 83

CONCLUSIONS Metallization

need reduced parasitics but porous low k is a challenge 3D : Some nice examples but timeline for full production

not clear. Some alternatives using capacitive or inductive coupling.

Memories DRAM and NAND in nonvolatile NAND multilevel and vertical structures Crosspoint memory: Phase Change Ram, ReRam,

STTRam as most likely successors

Displays, Sensors and MEMS

Walter Snoeys – PH ESE ME – 2011 84

Intel: 22 nm in full production this summerfull RF implemented in 0.32 nm

Walter Snoeys – PH ESE ME – 2011 85

1/f noise improves (Cox dependence)

Semiconductor companies

Walter Snoeys PH ESE ME – 2011 86

Foundries excluded

Significant growth in 2010

Foundries: operating fabrication plants

Walter Snoeys PH ESE ME – 2011 87

Source: wikipedia

More Moore and More Than Moore

Walter Snoeys – PH ESE ME – 2011 88

THANK YOU

Walter Snoeys – PH ESE ME – 2011 89