Interrupt Programming 8051

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CSULB -- CECS 285 Chapter Eleven

Fall 2010 -- R.W. Allison 1


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Interrupts allow a system to respond toevents (not in program flow) and

handle the events while another task is running

An gives the illusion of doingmany things simultaneously (multitasking on one CPU)

Interrupts routines are activated by the occurrence ofeither an or an event (a.k.a. )

The routine that deals with a specific interrupt iscalled an Interrupt Service Routine ( ) or an

Interrupt routines are said to run in the while the main system program runs in the


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Interrupts allow the 8051 to respond to asynchronous events(external or internal) only when required.



Interrupt Vector

Address

Number

Bytes

Pin Flag Clearing Comment

Reset 0000H 3 Auto Power-on

INT0 0003H 8 P3.2 Auto External Hardware

TF0 000BH 8 Auto Timer 0

INT1 0013H 8 P3.3 Auto External Hardware

TF1 001BH 8 Auto Timer 1

RI/TI 0023H 8 Programmer Serial Communication

TF2/EXF2 002Bh 3 Programmer Timer 2

Interrupts introduce the concept of where one interruptis given preference over another simultaneous interrupt

o The alternative is called polling testing status bits - which can betime consuming, wasting precious CPU resources/cycles

--where is the when a

particular interrupt occurs? (Atmel 89C51RD2 has 3 more not covered)


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Finishes the instruction currently being executed Saves the current status of all the interrupts and stores the

current PC Stack Vectors (i.e. jumps) to the corresponding location within the

interrupt vector table, i.e. PC Vector Table address

Option 1: If the ISR fits in the available space you can immediately

service the interrupt Option 2: If the ISR is too large then the vector table contains a

long jump (ljmp) to the Interrupt Service Routing (ISR)

Original PC is popped off the stack returning to whereprogram was when the interrupt occurred

The last instruction of the ISR is a (Return from Interrupt)

Responsibility of ISR to save/restore any registers that it uses,including the , having the same number of pushes and popsto/from the stack for the instruction to work correctly


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All interrupts are disabled (masked) at system reset



EA -- ET2 ES ET1 EX1 ET0 EX0

7 6 5 4 3 2 1 0

IE.7 . If EA = 0, no interrupt is acknowledged.If EA = 1, each interrupt source is individually enabled or disabledby setting or clearing its enable bit

Software enables those interrupts required

(A8h) nterrupt nable SFR is used to enable/disable interrupts

- IE.6 Not implemented. Dont set.

ET2 IE.5 Enables/disables Timer 2 TF2 or EXF2 interrupt (8052)

ES IE.4 Enables/disables Serial Port RI or TI interrupt

ET1 IE.3 Enables/disables Timer 1 overflow interrupt

EX1 IE.2 Enables/disables External interrupt 1

ET0 IE.1 Enables/disables Timer 0 overflow interrupt

EX0 IE.0 Enables/disables External interrupt 0


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-- IP.7 Undefined

-- IP.6 Undefined

PT2 IP.5 Priority for Timer 2 interrupt

PS IP.4 Priority for serial port interrupt


PX1 IP.2 Priority for external 1 interrupt


PX0 IP.0 Priority for external 0 interrupt

Prioritized allows resolution of interrupts Prioritized interrupts allow for interrupt handlers

(B8h) nterrupt riority SFR Priority is either high (1) or low (0) If an ISR is active and a higher priority interrupt occurs, it is

interrupted (i.e. preempted). A high level ISR can not beinterrupted.


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(00, 01, 10, 11)



-- IP (H/L). 7 Undefined

-- IP (H/L). 6 PCA (Programmable Counter Array)

PT2 IP (H/L). 5 Priority for Timer 2 interrupt

PS IP (H/L). 4 Priority for serial port interrupt

PT1 IP (H/L). 3 Priority for Timer 1 interruptPX1 IP (H/L). 2 Priority for external 1 interrupt

PT0 IP (H/L). 1 Priority for Timer 0 interrupt

PX0 IP (H/L). 0 Priority for external 0 interrupt

(B7h) Interrupt Priority HIGH (B8h) Interrupt Priority LOW

Priority from highest to lowest (3,2,1,0)

If an ISR is active and a higher priority interrupt occurs, it isinterrupted. A higher level ISR can not be interrupted. Equalpriorities yield to polling sequence (cf. page 75, AT8951RD2 spec)


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;--Upon wake-up go to Main, jump over the Interrupt Vector TableORG 0000hljmp Main ;bypassing the Interrupt vector table

;--Main program for executionORG 0030H ;after vector space

Main: mov TMOD, #02h ;Timer 0, mode 2 (auto-reload)mov TH0,#-92 ;TH0=A4H for -92

mov P0, #0FFh ;make P0 an input portmov IE,#82h ;IE = 10000010 enable Timer 0setb TR0 ;Start Timer 0

Back: mov A,P0 ;get data from P0mov P1,A ; and echo it to P1sjmp Back ;stay in this loop untilEND ; we are interrupted by TF0

ORG 0003h ;--External INT0 Vectoriret ; ISR stubORG 000Bh ;--Actual Timer 0 ISR that willcpl P2.1 ; toggle P2.1 pinreti ; to generate a square waveORG 0013h ;--External INT1 Vectorreti ; ISR stubORG 001Bh ;--Timer 1 Vectorreti ; ISR stub

ORG 0023h ;--Serial Port VectorretiORG 001Bh ;--Timer 2 Vectorreti ; ISR stub


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Tied to external pins: INT0 (P3.2), INT1 (P3.3) P3.2 and P3.3 are general purpose I/O pins until the respective

Interrupt Enable bits are set (i.e. EX0 and EX1, respectively)

8051 external interrupts activated in one of two ways

(1) Level-triggered of (2) edge-triggered

TCON.0 (IT0) and TCON.2 (IT1) defines interrupt type

IT0/IT1 = 0 for level-triggered interrupts (default)

IT0/IT1 = 1 for edge triggered interrupts

INT1

Vcc

8051

Pull-up

IE1 IT1

TCON (88h)

7 6 5 4 3 2 1 0IE0 IT0TF1 TR1 TF0 TR0


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CSULB -- CECS 285

Chapter Eleven


The LOW on the pin must be removed before the last instruction in theISR (reti) is executed else another interrupt will occur

INT0/INT1 held normally HIGH. A LOW level on one of these signalswill trigger the respective interrupt

The 8051 keeps sampling INTn for a LOW once each machine cycle

Some 8051s specify that the pin must be held in a LOW state until the startof the execution of the ISR. If the INTn pin is brought back to a HIGH beforethe start of the ISR, there will be no interrupt.

Thus, to ensure activation of an external interrupt, it must remain LOW for atleast 4 machine cycles


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CSULB -- CECS 285

Chapter Eleven


INT1/INT0 held normally HIGH. A HIGH-to-LOW transition on one ofthese signals will trigger the respective interrupt

In edge-triggered interrupts, the INT1/INT0 signal must be held HIGHfor at least one machine cycle, and then held LOW for at least onemachine cycle to ensure that the transition is seen by the 8051

Upon execution of a RETI instruction, the respective IEn bit will be cleared

automatically, indicating the edge-triggered interrupt has been serviced While the ISR is being executed, the 8051 ignores all transitions on the

external interrupt signals INT1/INT0

Setting IT1 or IT0 to 1 programs the 8051 to detect edge-triggered

signals

Regarding the Interrupt Type bits (IT1/IT0) in the TCON register, thefollowing two points must be emphasized:

The 8051 automatically sets the respective External Interrupt EdgeFlag (IE1/IE0) in the TCON register when using edge-trigerring

IE1 IT1 TCON (88h)

7 6 5 4 3 2 1 0

IE0 IT0TF1 TR1 TF0 TR0


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CSULB -- CECS 285

Chapter Eleven


ORG 0000hljmp Main ;bypassing interrupt vector table

;--MAIN program for initialization

ORG 30hMain: mov IE,#10000100b ;enable external INT1Here: sjmp Here ;forever loop

END

Toggle an LED to indicate arrival of the interrupt (LOW)

INT1 ISRs longer than 8 code bytes should implement aljmp into normal code space

;--ISR for hardware interrupt INT1 to turn on LED

ORG 0013H ;INT1 ISRsetb P1.3 ;turn on LEDmov R3,#255 ;load counter

Back: djnz R3,Back ;keep LED on for a whileclr P1.3 ;turn off the LEDreti ;return from ISR


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(ver. 2)

CSULB -- CECS 285

Chapter Eleven


ORG 0000hljmp Main ;bypassing interrupt vector table

;--ISR for hardware interrupt INT1 to turn on LEDORG 0013H ;INT1 ISR

ljmp Int1_ISR ; vector off to actual routine;--MAIN program for initialization

ORG 30hMain: mov IE,#10000100b ;enable external INT1Here: sjmp Here ;forever loop

Int1_ISR: push 03 ;save R3setb P1.3 ;turn on the LED

mov R3,#255 ;load counterBack: djnz R3,Back ;keep LED on for a while

clr P1.3 ;turn off the LEDpop 03 ;restore R3 andreti ; then return from ISR

END

Fixing two bugs:

Original ISR was longer than 8 bytes (fix with ljmp) Original ISR didnt save/restore R3 (fix with push/pop)


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Chapter Eleven


Bit Symbol Comment

TCON.7 TF1 T1 Overflow FlagTCON.6 TR1 T1 Run Control (1=ON, 0=OFF)TCON.5 TF0 T0 Overflow FlagTCON.4 TR0 T1 Run Control (1=ON, 0=OFF)TCON.3 IE1 EI1 edge flag. SET on H2L transition. Cleared by CPUTCON.2 IT1 I1 type control. 1=falling edge,0=low-level activatedTCON.1 IE0 EI0 edge flag. SET on H2L transition. Cleared by CPUTCON.0 IT0 I0 type control. 1=falling edge,0=low-level activated

the input must be held HIGH for one cycle and LOW for another.IE0/IE1 automatically cleared when CPU vectors to interrupt

the input must be held until interrupt generated. Must alsobe de-activated before the ISR is completed. Usually the ISR acknowledgesthe interrupt and the interrupting device removes the interrupt request

External Interrupts are sampled once each machine cycle so input should beheld for at least 12 oscillator periods to ensure proper sampling


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(Transmit Interrupt) is set when the last bit of frameddata, the stop bit, is transmitted indicating that is

empty and ready for another byte

CSULB -- CECS 285

Chapter Eleven


(Receive Interrupt) is set when an entire frame of datais correctly received indicating that now has a byteready to be read

Behavior of and is the same whether we are polling

or using interrupts. Difference is how we detect andrespond to its occurrence

and are ORd to generate a single interrupt

Always clear or prior to execution of reti

User must determine which is the source in the ISR

Typical use relies on for data received but will poll

to ensure data sent Analogous to receiving and generating a phone call


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Write a program to read data from P0 and echo it toP1continuously while giving a copy of it to the serialCOM port to be transmitted out serially

CSULB -- CECS 285

Chapter Eleven


For setup purposes, assume XTAL = 11.0592 MHzwith BAUD = 9600

Setup Code:Main: mov P0, #0FFh ;Initialize P0 as 8 inputs

mov TMOD, #00100000b ;Init Timer1 AUTO RELOAD (M2)

mov TH1, #0FDh ;Init Timer1 for 9600 BAUD

mov SCON, #01010000b ;Init UART 8-N-1; Rx Enabled

mov IE, #10010000b ;Enable Serial Interrupt

setb TR1 ;Start Timer 1

Positively: Excellence is in paying attention to .

Negatively: The devil is in the .

or, Whatever a man sows, that will he also reap.


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Chapter Eleven


ORG 0 ;VECTOR TABLE SETUPljmp Main ;Reset to Main

ORG 23hljmp Uart_ISR ;Vector off to the Serial ISRORG 30h ;Start of Main code

Main: mov P0, #0FFh ;Initialize P0 as 8 inputsmov TMOD, #00100000b ;Init Timer1 AUTO RELOAD (M2)mov TH1, #0FDh ;Init Timer1 for 9600 BAUD

mov SCON, #01000000b ;Init UART 8-N-1P; Rx Enabledmov IE, #10010000b ;Enable Serial Interrupts

setb TR1 ;Start Timer 1

Back: mov A, P0 ;read Port0

mov P1, A ; and echo it to both Port1mov SBUF, A ; and the serial I/F

sjmp Back ;loop endlessly

ORG 100h ;ISR for the Serial Port

Uart_ISR: jb TI, TX ;If TI then its a TX interruptmov A, SBUF ;Else its RX so get charclr RI ; clear RI interrupt flag

reti ; and leave

TX: clr TI ;It was a TX so clear TI flagreti ; and leave

END

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Interrupt Programming 8051

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