Introducing the MPC8569E PowerQUICC® III Processor · 2016-03-12 · Target Markets for QUICC...

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.

Bridging the Gap to the All-IP Network (Version 1)Introducing the MPC8569E PowerQUICC® III Processor

July 2009

Colin CuretonProduct Marketer

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 2

Target Markets for QUICC Engine™ Technology

Primary markets• Wireless infrastructure • Wireline/telecom

Metro Ethernet control• Enterprise networks

IP-PABX• SME enterprise

SME router Office-in-a-box

• SOHO/residential gateway

Adjacent• Industrial networking

WirelineInfrastructure

WirelessInfrastructure

DSLAM control & MTU

Multi-ServiceSwitchRouter

Add-DropMultiplexer

Radio NetworkController

NodeB (Base Transceiver Station)

Media Gateway

EnterpriseNetworking

Multi-ServiceProvisioning Platform

WirelessLAN

Router

EnterpriseMedia Gateway

Enterprise Router

IP PBX

Small MediumEnterprise

IP Access Router& VPN Gateway

SME Integrated Access Router for Teleworking

Mobile Access Router

Psuedowire Backhaul

Metro EthernetControl


MPC8569E and Freescale PowerQUICC® QUICC Engine™ Portfolio

Communications ProcessorsNo. 1 supplier of integrated communications processorsNo. 1 in embedded MPUs

Customer’s Equipment I/O Requirements PowerQUICC® ProcessorsI/O: up to 16 TDMs, 4 GbE or 8 FE, one Utopia / POS Multi-PHY Level 2 (16 bit), one x4 PCI Express® (PCIe), one 4x Serial RapidIO® (sRIO) or Dual 1x sRIO

MPC8569E1.33 GHz e500 CPU core, 512 KB L2 cacheDatapath offload in QUICC Engine™ module (4 RISC)

I/O: up to 8 TDMs, 5 GbE or 8 FE, two Utopia / POS Level 2 (16 bit), one x8 PCIe, one x4 sRIO

MPC8568E1.33 GHz e500 CPU core, 512 KB L2 cacheDatapath offload in QUICC Engine module (2 RISC)

I/O: up to 8 TDMs, 2 GbE or 8 FE, two Utopia / POS Multi-PHY Level 2 (16 bit), one PCI

MPC8360E667 MHz e300 CPU core, no L2 cacheDatapath offload in QUICC Engine module (2 RISC)

I/O: up to 2 TDMs, 3 FE, one Utopia Multi-PHY Level 2 (8 bit), one PCI

MPC8323E333 MHz e300 CPU core, no L2 cacheDatapath offload in QUICC Engine module (1 RISC)


MPC8569E PowerQUICC® III Communication Processor - Target Markets

Primary Market = All-IP and multi-service network interface and control processors.

• IP and multi-service base station backhaul (2G/3G/LTE/WiMAX)• Access gateway (IPV4 forwarding/security)• Legacy GPRS/3G control • Microwave backhaul• Gigabit SME applications• Industrial networking

Wireless Base Station

Access Aggregation/ Media Gateway

SME router

►Application Challenges : • Acceleration of network connected devices

Mix of services: voice and data Mix of protocols: IP, Ethernet, MPLS, TDM, ATM, IMA, A-bis/A-ter, PseudoWire… Mix of physical layer: E1/T1, PDH, SDH/SONET, OFDM-base microwave, g.SHDSL, ADSL2+, PON, Point2Point Ethernet. …

• Growing broadband wireline/wireless data-rates (including Gigabit IP forwarding)• Lower power to reduce OPEX and carbon footprint

►Device Advantages• High performance integration to meet cost and power pressures across Ethernet/ATM/TDM• New high speed interfaces for seamless connectivity

For Ethernet switches (SGMII), DSPs / FPGA / ASICs (sRIO) and Host/Peripherals (PCI-Ex) For Supporting dominant memory technologies - DDR II/III SDRAM

• Secure/encrypted networking over a diversity of transport networks (IPSec)• Network synchronization, including precision Timing-Over-Packet. (IEEE® 1588)

Industrial Networking


Power Architecture® Technology Platform RoadmapD

ecre

asin

g Po

wer

Increasing Performance, Reducing Power

Increasing Performance (Frequency, System Performance)

PowerQUICC® I

PowerQUICC II

PowerQUICC II Pro

PowerQUICC III

MPC86XX

QorIQ™ P1platform

QorIQ P2platform

QorIQ P3 platform

QorIQ - T1platform

QorIQ - T2platform

QorIQ - T3platform

QorIQ – T4platform

QorIQ P4platform

QorIQ P5platform QorIQ - T5

platform

Incr

easi

ng P

erfo

rman

ce

QorIQ - X1platform

QorIQ - X2platform

QorIQ - X3platform

QorIQ – X4platform

First Generation45 nm

Second Generation32 nm

Third Generation22 nm


MPC8569E PowerQUICC III: Bridging the Gap to the All-IP Network

• e500 core, built on Power Archtiecture® Technology, from 800 MHz to 1.33 GHz

• 512 KB L2 Cache w/ ECC• 36-bit physical addressing• Double precision floating point

• System Interfaces• 64b or 2x32-bit DDR2/3 w/ ECC• 800 Mbps/pin data rate• 16-bit Local Bus for SRAM/flash• Timers, DUART, 2xI²C, GPIO, SPI• USB 2.0 full speed

• High Speed Serial Interfaces• Dual SGMII• Dual x1 Serial RapidIO® or PCI Express®

• QUICC Engine• 4 RISCs up to 667 MHz• Maximum of 8 Ethernet interfaces, one per UCC:

• 4 x Gigabit Eth (up to 2 w/SGMII)• Up to 8 x 10/100 Ethernet

• Multi-PHY UTOPIA/POS-PHY L2 (16-bit)• IEEE® 1588 Support v2• 16 x T1/E1 (512 x 64kbps channels)

• Security Engine (SEC 3.0)• ARC4, 3DES, AES, RSA/ECC, RNG, XOR, Single

pass SSL/TLS, Kasumi, SNOW• Four-channel DMA• 45 nm SOI process technology• Target <7W Power (@ 800 MHz e500)


►Asynchronous architecture scaling from one to four RISCs at 200-667 MHz• Code compatible• Compatible with existing PowerQUICC® CPM architecture

►Eight unified communication controllers (UCCs) support virtually any interface• 10/100/1000 Gigabit Ethernet• Utopia / POS Multi-PHY Level 2 ports• Serial ATM

►Multi-channel communications controller supporting time multiplexed protocols• Supports up to 16 T1/E1 interfaces• 256 HDLC or 128 SS7 channels on 8 TDMs• Serial ATM (up to 64 TC layers)• ML/MC-PPP

►Support for SPI, USB and other interfaces

►Protocol termination and interworking for a wide range of communication protocols including ATM, Ethernet, PPP, HDLC, TDM, UTOPIA and POS

QUICC™ Engine – Architecture: Flexible, Scalable and Packet-friendly

Baud RateGenerators

TimersSDMAsSlave

Interface

Multi UserRAM

Accelerators

32-bit RISC andProgram ROM/RAM

Accelerators


SPI

SPI

USB

MC

C

UC

C1

UC

C3

UC

C5

UC

C7

UC

C2

UC

C4

UC

C6

UC

C8

Communication Interfaces

16 TDM Ports

8 MII/RMII

1 UTOPIA/POS (16 bit MPHY)

4 GMII/RGMII/TBI/RTBI

Comprehensive CodeWarrior™ and 3rd-Party Enablement Ecosystem



H/W SchedulerM

CC1 RISC 2 RISC 4 RISC

MHz Range 200 200-533 200-667IRAM Memory 8K Bytes 48K-64K Bytes 256K Bytes

MURAM Memory 16K Bytes 48K-64K Bytes 128K Bytes

ROM Memory 96K Bytes 192K bytes N/AEthernet Ports Up to 3 x 10/100 Up to 8 10/100

Up to 3 x 10/100/1000

Up to 8 x 10/100Up to 4 x

10/100/1000UTOPIA/POS Ports 1 2 1

TDM ports 4 8 16

IEEE1588 Support No Yes (MPC8360 only)

Yes

UPC124

Time Slot Assigner


QUICC Engine™

BlockPHYs

QUICC Engine™

BlockPHYs

QUICC Engine™ – Protocol Termination vs. Interworking

► Protocol Termination:• Both control and data plane traffic are terminated

by the CPU• Predominant approach used with CPM based

PowerQUICC devices• Protocol processing and interworking is performed

by CPU software

► Protocol Interworking:• Data plane traffic is forwarded directly by QUICC

EngineTM technology. Control plane traffic is terminated by the CPU.

• Benefits: Greater headroom in CPU, improved throughput, minimized latency and jitter

• Powerful API and drivers provided to facilitate effective use of interworking

CPU

Control Plane and Data Plane

CPU

ControlPlaneData Plane

PowerQUICC® Device PowerQUICC Device

• Interworking applications are typically complex from a Freescale solution perspective, and often customer specific, as they rely upon implementing functions previously done using CPU software in microcode

• Termination applications rely upon customer implemented software, and therefore are less complex from a Freescale solution perspective


QUICC Engine™ Netcomm Device Drivers Overview

►Device Drivers: Modular set of platform, peripheral and protocol device drivers Operating system independent APIs (e.g. bare board) for customer

application use and porting– Operating system porting guide provided

Platform level drivers supported – MMU, cache, interrupt controller, memory controllers, timers, DUART, I2C, security, etc.

Built-in use cases demonstrating functionality and performance Complete device driver source code and comprehensive documentation

provided


QUICC Engine™ Netcomm Device Drivers Overview

►Comprehensive feature set, including: Interrupt or polling modes for communication peripherals Statistics gathering Protocol interworking Support for both default (simple) and advanced (detailed) driver

configurations External memory management for parameters, tables and BD’s Memory management support for system bus, secondary bus and local bus

►Hardware support: Support for MDS processor and I/O boards


QUICC Engine™ Linux® Drivers

Ethernet IMA STACK

LinuxKernel Space

Linux®

User SpaceUser Space Libraries

EthernetTermination

Interworking PPPTermination

Filter Interworking

PacketFiltering

Kernel Drivers

IMA Stack Config

PPP LLD & Stack

IMA LLDETH ATM PPP

QUICC Engine Linux driver package contains:

• Low-level drivers (bare board)

• User space libraries• The user space API is a

mirror of the bare board API

Supported features include:• Ethernet termination• ATM termination• IMA termination• PPP termination• ATM2ETH interworking• ETH2ETH interworking• PPP2ETH interworking• ATMoIMA2ETH

interworking• Packet filtering

ATM

ATM Termination


Approved QUICC Engine™ Partners For Custom QUICC Engine Microcode Solutions

► These companies are the route to take customer specifications and produce application-specific or feature-enhanced microcode packages

* indicates companies with most extensive knowledge and protocol solutions experience.

►Third-party developers:

• DoGav Systems*: www.dogav.net

• Wipro Technologies*: www.wipro.com

• IndusRAD Inc: www.indusrad.com

• Interphase Inc : www.interphase.com

• PD3: www.pd3.com.br/v1/

http://www.dogav.net/�

http://www.wipro.com/�

http://www.indusrad.com/�

http://www.interphase.com/�

http://www.pd3.com.br/v1/�


MPC8569 System Scenarios

For “All IP” and Multi-protocol Systems


“QUICC Connect” Companion Support

Control viasRIO, PCI-Ex, RGMII

QUAD RISC QUICC Engine

8569

>6000 DMIPS ControlExtern Host

8572/x

Data

Inde

pend

ently

Sc

alab

le

► Companion Set

MPC8569

Network Control

Added Control Performance Via 2 Companion Chips

MPC8572/26

Family of IP and Multi-Protocol Network Interface Cards

<1200 DMIPS Control

MPC8323MPC8360

DataSingle/Dual RISC QUICC Engine

e300C

ost &

Pow

er

Opt

imal

Network Options• 10/100/1000 Eth • STM1• Multi E1/T1• DS3

Net

wor

k In

terf

ace

► Integrated Control / Data

Adds sRIO, PCI-E or RGMII

>3000 DMIPS Control

Dual RISC QUICC Engine™

MPC8568

Integrale500Host

Data

Hi-P

erfo

rman

ce

Syst

em o

n C

hip

Control viaPCI, RGMII

Dual RISC QUICC Engine

MPC8360

3000-6000 DMIPS ControlExternal

HostMPC

8548/72

Data

Inde

pend

ently

Sc

alab

le

► Companion Set

► Single Chip





8569


8572/x

Data

Inde

pend

ently

Sc

alab

le

► Companion Set

MPC8569

Network Control


MPC8572/26


► Integrated Network/Control

Quad RISC QUICC Engine

Adds sRIO, PCIe or SGMII

>3000 DMIPS Control

► Next Generation MPC8569E :- Highly integrated networking interface device -

effectively two chips into one – network and control

- Doubles data-plane communication performance

- Optimized system power/cost- High-speed serial Interfaces for

switches/hosts/FPGAs including SGMII, Serial RapidIO®, PCI Express®

- Integrated IEEE® 1588 network synchronization- Integrated IPsec / security

MPC8569

Integrale500Host

Network Data

<1200 DMIPS Control

MPC8323MPC8360

DataSingle/Dual RISC QUICC Engine

e300C

ost &

Pow

er

Opt

imal

Network Options• 10/100/1000 Eth • STM1• Multi E1/T1• DS3

Net

wor

k In

terf

ace

► Integrated Control / Data

Adds sRIO, PCI-E or RGMII

>3000 DMIPS Control

Dual RISC QUICC Engine™

MPC8568

Integrale500Host

Data

Hi-P

erfo

rman

ce

Syst

em o

n C

hip

Control viaPCI, RGMII

Dual RISC QUICC Engine

MPC8360

3000-6000 DMIPS ControlExternal

HostMPC

8548/72

Data

Inde

pend

ently

Sc

alab

le

► Companion Set

► Single Chip





8569


8572/x

Data

Inde

pend

ently

Sc

alab

le

► Companion Set

MPC8569

Network Control


MPC8572/26


► Integrated Network/Control

Quad RISC QUICC Engine

Adds sRIO, PCIe or SGMII

>3000 DMIPS Control

► Next Generation MPC8569E :- Highly integrated networking interface device -

effectively two chips into one – network and control

- Doubles data-plane communication performance

- Optimized system power/cost- High-speed serial Interfaces for

switches/hosts/FPGAs including SGMII, Serial RapidIO®, PCI Express®

- Integrated IEEE® 1588 network synchronization- Integrated IPsec / security

MPC8569

Integrale500Host

Network Data


Octal T1/E1Framer

Octal T1/E1Framer

Time Slot Interchange

(TSI)

8xE1

8xE1

802.3adLink Aggr

BACKHAUL: TDM + (ATM or POS)

BACKPLANE: Ethernet

802.3adLink Aggr

SerDes

SerDes

BackplaneEthernetSwitch

STM-4 or 4xSTM-1Framer

Console port etc

Serial EEPROM

Flash

64 or 32-bit

32-bit

T3/E3Framer

Nibble mode1 nibble port

2 x 16 MHz TDM I/For 4 x 8 MHz TDM I/For8 x 4 MHz TDM I/F

Basestation Network Interface Card #1Ethernet Backplane

50 MHz16-bit

External Host Processor1 to 4 SPHYs

Full Speed at 12 Mbps

Debug

Maintenance / Debug ports

MPC8569E

DDR2/3

R/GMII

R/GMII

UL2 orPL2

DUART

Local Bus

DDR2/3

GPIO

SRIO or PCIe

USB 2.0

JTAG

2 x I2C or 2 x SPI

R/MII

R/MII

TDMPorts SGMII

R/GMII

SGMIIR/GMII


Octal T1/E1Framer

Octal T1/E1Framer

Time Slot Interchange

(TSI)

8xE1

8xE1

802.3adLink Aggr

BACKPLANE: ATM

BackplaneCell

Switch

STM-4 or 4xSTM-1Framer

Console port etc

Serial EEPROM

64 or 32-bit

32-bit

T3/E3Framer

Nibble mode1 nibble port

2 x 16 MHz TDM I/For 4 x 8 MHz TDM I/For8 x 4 MHz TDM I/F

Basestation Network Interface Card #2ATM Backplane

50 MHz16-bit

External Host Processor1 to 4 SPHYs

Full Speed at 12 Mbps

Debug

MPC8569

DDR2/3

SGMIIR/GMII

SGMIIR/GMII

UL2 orPL2

DUART

Local Bus

DDR2/3

GPIO

SRIO or PCIe

USB 2.0

JTAG

2 x I2C or 2 x SPI

R/MII

R/MII

TDMPorts

UL2

Flash

Maintenance / Debug ports

50 MHz16-bit

BACKHAUL: TDM + (ATM or POS)


Device Migration

Product Family MPC8560E MPC8360E MPC8568E MPC8569E

Core Control e500 e300 e500 e500

Max Core Frequency 1 GHz 667 MHz 1.33/1.5 GHz 1.33 GHz

CPM or QE 1 2 2 4

CPM/QE Memory 64K IRAM, 32K MURAM 48K IRAM, 48K MURAM, 192K ROM

64K IRAM, 64K MURAM, 192K ROM 256K IRAM, 128K MURAM

Max CPM/QE Frequency 333 MHz Up to 500 MHz Up to 533 MHz Up to 667 MHzEthernet (MII, RMII) 3 8 8 8Ethernet (GMII, RGMII) 2 2 3 4 (incl 2 SGMII)ATM UTOPIA M-PHY 1 2 2 1POS-PHY - 2x128 1x31 1x128TDMs 8 8 8 16MCC (256 HDLC ch) 2 1 1 2USB (full/low speed) - 1 - 1SPI 2 2 2 2Encryption (Option) Y Y Y YIEEE 1588 - Y (V2) - Y (V2)

Availability Now Now Now SamplingProcess 130 nm 130 nm 90 nm SOI 45 nm

Package 783 FC-PBGA 668 PBGA740 TBGA 1023 FCPBGA 783 FC-PBGA

Typical Power 16.5W @ 1GHz3-3.5W PBGA,

5-7W TBGA 13-19W Est<7W@800 MHz core (<[email protected] GHz core)


MPC8569E: Optimizing Power and Cost

► Integrated network control and data-plane in one device ► “All-IP” and multi-protocol networking under one hood►Autonomous interworking support offloads e500 core►Support of dominant DDR2/3 memory► Integrated SerDes reduces system interconnect costs

• SGMII connect to next generation Ethernet switches and transceivers

• PCI Express® connects to Freescale’s high-end Power Architecture® companion processors or next-generation peripheral devices

• Serial RapidIO® interconnect to DSP and backplanes►Addressing future packet timing and security challenges►Energy efficient solution - low power by design


Q&A

►Thank you for attending this presentation

►We’ll now take a few moments for the audience’s questions and then we’ll begin the question and answer session

TM

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