G.H.Raisoni College of Engineering(An Autonomous Institute under UGC Act 1956 & Affiliated to Rashtrasant Tukdoji Maharaj

Nagpur university,Nagpur)

Department of Electronics And Telecommunication Engineering TAE IV “Application Specified Intregated Circuit”

Submitted by: 7th ETC Shruti Sharma-B19 Shruti Dhapke-B20 Sonia Kharwade-B22

Introduction

Two major HDL’s:VHDL standardized by IEEE in 1987,1993, 2002,2006 object-oriented, very widely used Has Verbose syntax like ADAVerilog standardized by IEEE in 1995, 2001, 2005 has concise syntax like C

ABOUT VHDL

VHDL is an acronym of VHSIC Hardware Description Language

VHSIC is an acronym of Very High Speed Integrated Circuits

A Formal Language for Specifying the Behavior and Structure of a Digital Circuit

Allows Top-Down Design

Origin of the VHDLVHDL originated in the early 1980s

The American Department of Defense initiated the development of VHDL in the early 1980s

because the US military needed a standardized method of describing electronic systems

VHDL was standardized in 1987 by the IEEEIt is now accepted as one of the most important standard

languages forspecifyingverifying designing of electronics

VHDL Design Flow

VHDL Constructs

Entity definition Architecture definition Configuration Process Subprogram PackageA VHDL design can be broken into multiple files.A VHDL design can be broken into multiple files.Each file contains entity and architectureEach file contains entity and architecturedefinitions, or packages.definitions, or packages.

Design Entity A component or a system to be designed is a VHDL

“design entity” VHDL divides entities into two parts:

External (interface): how it connects to other components Internal (architecture): how it behaves and how it is

implemented Behavioral Structural Hybrid

Entity definition To define an entity First an “entity declaration” is given. Thisspecifies one or more input, output, or input-outputports that are wired to neighboringentities. Then one or more “architecture definition(s)” isgiven. This determines how the entity functionsand how it is implemented.

VHDL Alphabet

VHDL alphabet consists of all of the characters in the ISO eight-bit character set.

The first 128 characters in the ISO set are the ASCII characters.

VHDL is not case-sensitive. Two consecutive dashes (--) start a VHDL

comment. The comment extends to the end of current line.

VHDL Identifiers

VHDL identifiers: Must start with an alphabetic letter, May only contain uppercase and lowercase letter,

digits, and underscore ( _ ), May not end with an underscore character, May not contain two consecutive underscore

Characters, Can be arbitrarily long.

VHDL Keywords

Data Types

VHDL is a strongly typed language. You mustassign a data type to all ports, signals, variables, and constants.Four classes of data types1. Scalar types (integer, real, time, …)2. Composite types (array, record, …)3. File types (binary file, ascii file)4. Access types

Scalar Types

Integers (at least 32 bits signed) Permissible operations: + - * / mod rem abs ** Floating point numbers (32 bits at least)

Permissible operations: + - * / abs ** Physical units

1) Type time is predefined in VHDL. E.g. 20 fs, 34 ps, 10 ns, 21 us, 320 ms, 2 sec, 12 min, 3 hr2) Other physical types can also be defined.

Enumeration types Predefined: bit (‘0’,’1’), character, boolean (false,true) Users can define other enumeration types.

VHDL Operators

Boolean Operators

NOTANDORNANDNORXORXNOR

Comparison Operators

==/<=<>=>

Arithmetic Operators

+- ABSMODREM*/**

Concat.Operators

&

Logic value system

ValueRepresentingRepresenting

''UU''UninitializedUninitialized

''XX''Forcing UnknownForcing Unknown

''00''Forcing 0Forcing 0

''11''Forcing 1Forcing 1

''ZZ''High ImpedanceHigh Impedance

''WW''Weak UnknownWeak Unknown

''LL''Weak 0Weak 0

''HH''Weak 1Weak 1

'-''-'Don’t careDon’t care

Modeling Concurrency

Delay and concurrency is inherent in any real circuit and must be simulated. Event-driven simulation method is used.

VHDL Statements

VHDL has two kinds of statements:Sequential statements: they are executed one after another, like

C or Pascal Signal and variable assignments, flow control constructs (if, case, while, loop,

…), subprogram call, wait

Concurrent statements: all are executed at the same time. Processes, block statements, component instantiations, generate statements,

concurrent assignments and concurrent procedures

Syntax

Port Modes: In : port can only be read Out : port can only be assigned Inout : Can be read and assigned a value. The value read is not the assigned

value. Buffer : Similar to out, but can be read