Introduction to Altera Board

7/30/2019 Introduction to Altera Board

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CSCE 488

An Introduction toFPGA and SOPC Development Board

(Adapted from material developed by Yong Wang& Stefan Hass)

Yuyan Xue


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CSCE488-2005 2

What are Programmable Logic Devices? Architecture and Examples

Why FPGA? Vendors and Device Series

Development on Altera Devices

Summary

Outline


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Programmable Logic Devices


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Programmable Logic Devices

Programmable digital integrated circuit

Desired functionality is implemented by configuringon-chip logic blocks and interconnections

(compared with ASIC) Developers only care about the logic design but

not the internal hard-wire connection ( softwarelizethe hardware design)


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ASIC Vs. Programmable Logic Device

ASIC (Application SpecificIntegrated Circuit)

Programmable LogicDevice

Faster performance Longer delay

>10,000 chips Good for medium to lowvolume products

Lower cost if produced in highvolume

Higher cost per chip

Longer design cycle andcostlier ECO (EngineeringChange order)

Shorter design cycle andcheaper ECO

Energy saving More power consumption


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Type of Programmable Logic Devices

PLD (Programmable Logic Device)

CPLD (Complex Programmable Logic Device)

FPGA (Field Programmable Gate Array)


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Architecture and Examples


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PLD - Sum of Products

A B C

CBACBAf +=1

CBABAf +=2

AND plane

Programmable AND array followed by fixed fan-in OR gates

Programmable switch or fuse

any logical function can be written in SOP(Sum of Products) form

=>

any function can be implemented by AND

gates generating products which feed to anOR gate that sums them up

Product Terms


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CSCE488-2005 9

PLD - Macrocell

Can implement combinational or sequential logic

A B C

Flip-flop

Select

Enable

D Q

Clock

AND plane

MUX

f


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CSCE488-2005 10

CPLD Structure

Integration of several PLD blocks with a programmableinterconnect on a single chip

PLD

Block

PLD

BlockPLD

Block

PLD

Block

Interconnection MatrixInterconnection Matrix

I/OBloc

k

I/OBlock

I/OBloc

k

I/OBlock

PLD

Block

PLD

BlockPLD

Block

PLD

Block

I/OBlock

I/OBlock

I/OBlock

I/OBlock

Interconnection MatrixInterconnection Matrix


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CSCE488-2005 11

CPLD Example - Altera MAX7000

EPM7000 Series Block Diagram


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CSCE488-2005 12

CPLD Example - Altera MAX7000

EPM7000 Series Device Macrocell


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CSCE488-2005 13

FPGA - Generic Structure

FPGA building blocks: Programmable logic blocks

Implement combinatorial andsequential logic

Programmable interconnectWires to connect inputs, outputs

and different logic blocks Programmable I/O blocks

Special logic blocks at the

periphery of device for external

connections

I/O

I/O

Logic block Interconnection switches

I/O

I/O


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CSCE488-2005 14

FPGA Basic Logic Element

LUT(Look Up Table) to implement combinatorial logic

Register for sequential circuits

Additional logic (not shown): Carry logic for arithmetic functions

Expansion logic for functions requiring more than 4 inputs

LUTLUT

Out

Select

D Q

A

B

C

D

Clock


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CSCE488-2005 15

Look-Up Tables (LUT) Look-up table with N-inputs can be used to implement any

combinatorial function of N inputs

LUT is programmed with the truth-table

A B C D Z

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 11

0 1 0 0 0

0 1 0 1 1

0 1 1 0 1

0 1 1 1 1

1 0 0 0 0

1 0 0 1 11 0 1 0 1

1 0 1 1 1

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

LUTLUT

A

B

C

D

Z

A

B

C

D

Z

Truth-table Gate implementation

LUT implementation


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CSCE488-2005 16

Other FPGA Building Blocks

Clock distribution

Embedded memory blocks Special purpose blocks:

DSP blocks:

Hardware multipliers, adders and registers

Embedded microprocessors/microcontrollers

High-speed serial transceivers


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CSCE488-2005 17

Special Features

Clock management

PLL,DLL

Eliminate clock skew between external clock inputand on-chip clock

Low-skew global clock distribution network Support for various interface standards

High-speed serial I/Os Embedded processor cores

DSP blocks


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CSCE488-2005 18

Configuration Storage Elements

SRAM

Logical configuration is controlled by the state of SRAM

bits FPGA needs to be configured at power-on by anotherseparated ROM

Flash

Logical configuration is implemented by floating-gatetransistors that can be turned off by injecting charge onto

its gate. FPGA itself holds the program reprogrammable, even in-circuit


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Example: Altera Stratix Series


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CSCE488-2005 20

Why FPGA?

handle dense logic and memory elements

offering very high logic capacity Easy to revise the logic design

Lower cost and shorter development cycle Complete integrated design environment (IDE)

Easy to learn and use


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CSCE488-2005 21

FPGA Vendors Altera

Xilinx Virtex-II/Virtex-4: Feature-packed high-performance

SRAM-based FPGA Spartan 3: low-cost feature reduced version

CoolRunner: CPLDs

Actel

Lattice

QuickLogic


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CSCE488-2005 22

Introduction to Altera Devices

Programmable Logic Families

High & Medium Density FPGAs

Stratix II, Stratix, APEX II, APEX 20K, & FLEX10K

Low-Cost FPGAs

Cyclone & ACEX1K

CPLDs

MAX7000 & MAX 3000

Embedded Processor Solutions

Nios, ExcaliburT

Configuration Devices EPC


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CSCE488-2005 23

Nios: The processor in software

a user-configurable, 16-bit instruction setarchitecture (ISA), general-purpose RISCembedded processor

designers can use the SOPC (system-on-a-programmable-chip) Builder system

development tool to very easily create customprocessor-based systems


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CSCE488-2005 24

Development on Altera Devices


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CSCE488-2005 25

What is available?

Altera Stratix Nios Development Board

Altera UP2 Development Board


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CSCE488-2005 26



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CSCE488-2005 27


Stratix EP1S10F780C6

10,570 Logic Elements 920 Kb on-chip memory

Provide hardware platform for developingembedded system

Comes pre-programmed with a 32-bitNiosprocessor reference design


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CSCE488-2005 28


8 MB of flash Memory,1MB of static RAM, 16MB ofSDRAM

On-board Ethernet MAC/PHY device

Compact Flash connector hearder

Two RS-232 DB9 serial ports 50MHz oscillator and zero-skew clock distribution

circuitry

Four push-button switches

Dual 7-segment LED display

Al UP2 D l B d


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CSCE488-2005 29


Alt UP2 D l t B d


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CSCE488-2005 30


EPF10K70RC240-4 device

EPM7128SLC-7 device

One RS-232 serial port

Four push-button switches

Dual 7-segment LED display 25.175MHz oscillator

FPGA D i Fl


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CSCE488-2005 31

FPGA Design Flow

Design Entry

Simulation

Synthesis

Place & Route

Simulation

Program device & test

Design Specification

FPGA Design Flow


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CSCE488-2005 32

FPGA Design Flow

SynthesisTranslate Design into Device Specific Primitives

Design Specification

Place & RouteMap Primitives to Specific Locations insideTarget devices

Design Entry/RTL CodingBehavioral or Structural Description of Design

LEMEM I/O

RTL SimulationFunctional SimulationVerify Logic Model & Data Flow(No Timing Delays)

FPGA Design Flow


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CSCE488-2005 33

FPGA Design Flow

Timing Analysis- Verify whether Performance Specifications Were Met- Static Timing Analysis

Gate Level Simulation- Timing Simulation- Verify whether Design Will Work in Target Device

Program & Test-Download Design Program to the device-& Test Device on Board

tclk

D i E t M th d


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CSCE488-2005 34

Design Entry Methods

Text-based

VHDL(Very High SpeedIntegrated CircuitHardware DescriptionLanguage)

Verilog HDL

Block Diagram


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CSCE488-2005 35

Block Diagram

Contents of a block can beany type of design unit

State Diagram


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CSCE488-2005 36

State Diagram

Bubble diagram

States

Conditions

Transitions

Outputs

Useful for developingcontrol modules

ProgramDevices


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CSCE488-2005 37

Program Devices

Once we verify our design, itshould be downloaded to the

FPGA devices

Designs can be downloadedthrough parallel port in PC to

the J TAG connector on boardusing download cables

Designs can also bedownloaded via the Internetto a target device

Introduction to Altera Design Software


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CSCE488-2005 38

Introduction to Altera Design Software

Software & Development Tools:

Quartus II

Stratix II, Stratix, Stratix GX, Cyclone,APEX II, APEX 20K/E/C, Excalibur, &Mercury Devices

FLEX 10K/A/E, ACEX 1K, FLEX 6000,

MAX 7000S/AE/B, MAX 3000A Devices

Quartus II Web Edition

Free Version

Not All Features & Devices Included

MAX+PLUS II

All FLEX, ACEX, & MAX Devices

Quartus II Development System


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CSCE488-2005 39

Quartus II Development System

Fully-Integrated Design Tool

Multiple Design Entry Methods

Logic Synthesis

Place & Route

Simulation

Timing & Power Analysis

Device Programming

SignalTap II & SignalProbe Debug Tools

Quartus II Operating Environment


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CSCE488-2005 40

Quartus II Operating Environment

Main Toolbar & Modes


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CSCE488-2005 41

Main Toolbar & Modes

Window & new file

buttons

Compiler Report

Floorplans

Execution Controls

Simulation Controls

Project Navigator

Summary


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Summary

Prerequisite

Electronics and circuits

Digital logic design

VHDL

FPGA

Combine technologies in hardware & software

Benefits

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Introduction to Altera Board

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