Introduction toCMOS VLSI

Design

Lecture 10: Sequential Circuits

David Harris

Harvey Mudd College

Spring 2004

CMOS VLSI Design10: Sequential Circuits Slide 2

Outline Floorplanning Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking

CMOS VLSI Design10: Sequential Circuits Slide 3

Sequencing Combinational logic

– output depends on current inputs Sequential logic

– output depends on current and previous inputs– Requires separating previous, current, future– Called state or tokens– Ex: FSM, pipeline

CL

clk

in out

clk clk clk

CL CL

PipelineFinite State Machine

CMOS VLSI Design10: Sequential Circuits Slide 4

Sequencing Cont. If tokens moved through pipeline at constant speed,

no sequencing elements would be necessary Ex: fiber-optic cable

– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses– But dispersion sets min time between pulses

This is called wave pipelining in circuits In most circuits, dispersion is high

– Delay fast tokens so they don’t catch slow ones.

CMOS VLSI Design10: Sequential Circuits Slide 5

Sequencing Overhead Use flip-flops to delay fast tokens so they move

through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay

– Called sequencing overhead Some people call this clocking overhead

– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence

CMOS VLSI Design

Pipelining

10: Sequential Circuits Slide 6

CMOS VLSI Design10: Sequential Circuits Slide 7

Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches

Flip-F

lopsF

lop

Latc

h

Flo

p

clk

1

2

p

clk clk

Latc

h

Latc

h

p p

1 12

2-Phase T

ransparent LatchesP

ulsed Latches

Combinational Logic

CombinationalLogic

CombinationalLogic

Combinational Logic

Latc

h

Latc

h

Tc

Tc/2

tnonoverlap tnonoverlap

tpw

Half-Cycle 1 Half-Cycle 1

CMOS VLSI Design10: Sequential Circuits Slide 8

Timing Diagrams

Flo

p

A

Y

tpdCombinational

LogicA Y

D Q

clk clk

D

Q

Latc

h

D Q

clkclk

D

Q

tcd

tsetup thold

tccq

tpcq

tccq

tsetup tholdtpcq

tpdqtcdq

tpdLogic Prop. Delay

tcdLogic Cont. Delay

tpcqLatch/Flop Clk-Q Prop Delay

tccqLatch/Flop Clk-Q Cont. Delay

tpdqLatch D-Q Prop Delay

tcdqLatch D-Q Cont. Delay

tsetupLatch/Flop Setup Time

tholdLatch/Flop Hold Time

Contamination and Propagation Delays

CMOS VLSI Design10: Sequential Circuits Slide 9

Max-Delay: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetuptpcq

sequencing overhead

pd ct T

CMOS VLSI Design10: Sequential Circuits Slide 10

Max-Delay: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetuptpcq

setup

sequencing overhead

pd c pcqt T t t

CMOS VLSI Design10: Sequential Circuits Slide 11

Min-Delay: Flip-Flops

cdt CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq

CMOS VLSI Design10: Sequential Circuits Slide 12

Min-Delay: Flip-Flops

holdcd ccqt t t CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq

CMOS VLSI Design

Positive Skew & Negative Skew

10: Sequential Circuits Slide 13

PS Clk & Data Same Direction

NS Clk & Data Difft Direction

CMOS VLSI Design10: Sequential Circuits Slide 14

Skew: Flip-Flops setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetuptpcq

CMOS VLSI Design10: Sequential Circuits Slide 15

Skew: Flip-Flops setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq

CMOS VLSI Design10: Sequential Circuits Slide 16

Safe Flip-Flop In class, use flip-flop with nonoverlapping clocks

– Very slow – nonoverlap adds to setup time– But no hold times

In industry, use a better timing analyzer– Add buffers to slow signals if hold time is at risk

D

X

Q

Q

CMOS VLSI Design10: Sequential Circuits Slide 17

Summary Flip-Flops:

– Very easy to use, supported by all tools 2-Phase Transparent Latches:

– Lots of skew tolerance and time borrowing Pulsed Latches:

– Fast, some skew tol & borrow, hold time risk