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7/27/2019 Introduction to IC Technology IV ECE -26the June
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Basic VLSI Design
B LOKESHWARAssistant Professor
ECE DepartmentRVR & JC College of Engineering
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Outlines
Introduction to IC Technology
Introduction to MOS Technology
MOSFETs ModesNMOS Fabrication
CMOS Fabrication
BiCMOS Fabrication
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Introduction to IC technology:• It is a circuit where all discrete components
such as passive as well as active elements arefabricated on a single crystal chip
• Until 1950, electronic technology dominated by vacuum tube
• The first semiconductor chip held twotransistors each
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Introduction to IC technologyAs on increasing the number of components(or
transistors) per IC the technology was developed
asSSI
MSI
LSI
VLSI
ULSI (Advances in VLSI)
GSI
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Integrated Circuit Evolution
Year Technology Transistors/chip Examples1947 Invention of the
transistor 1 -
1950 DiscreteComponents
1 Tran and Diode
1961 SSI 10-100 Logic gates and flipflops
1966 MSI 100-1000 Counters andregisters
1971 LSI 1000-20000 8 bit mp, ROM,
RAM1980 VLSI 20000- 100000 16,32 bit mp
1990 USLI 100000 -1million Special purpose processors
2000 GSI More than 1 million Embedded system,
system on chip
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VLSI(Very large scale integration)is the process of created integrated circuits by
combining thousands of transistors into a single chip.
VLSI begins in the 1970’s when complexsemiconductor and communication technologies were
being developed.
The microprocessor is a VLSI device.
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Very large scale integration( Cont..)VLSI chips are widely used in various branches of engineering like
Digital signal processing.
Wireless LAN
Bluetooth
Bus interface via PCI,USB.
Commercial electronics: TV sets, DVD.
Computers and computer graphics.
Automobiles, toys.
Medicine: Hearing aids, implants for human body
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Moore’s LawIn 1965, Gordon Moore, an industry pioneer,
predicted that the number of transistors on a chip
doubled every 18to 24 months.He also predict that semiconductor technology will
double its effectiveness every 18 months
Many other factors also grow exponentially those are – clock frequency
– processor performance
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Moore’s Law(Cont..)Transistors count will be doubled for every 18
months
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Introduction to MOS TechnologyWhatever the IC (it may be simple logic gate,
microprocessor), that we are seeing outside can be
manufactured using different MOS technologies.
The devices by which we can fabricate the different
types of ICs
These devices can be any type of the following:
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Introduction to MOS Technology(Cont..)
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Introduction to MOS Technology(Cont..)
Comparison of available Technologies
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Introduction to MOS Technology(Cont..)To know about each type of MOS technology, we just
look about to know transistor, types of transistors.
Transistor:A transistor is a semiconductor device used to amplify and
switch electronic signals and power.
It is composed of a semiconductor material with at leastthree terminals for connection to an external circuit.
Today, some transistors are packaged individually, but many
more are found embedded in integrated circuits.
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Types of Transistors:BJT:
FET:
Problems:• Low
resistance• Noise
Problems:
• gate must be reversebiased(decreasing theconductivity)
• Called depletion mode of transistor)
Channel width decreased
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MOSFETHowever, there is a FET that can be operated to
enhance the width of the channel(Enhancement Mode)
Such FET is called MOSFET(depends on mode of operation.)
Dua l
Mode
MO S F E T
En hancemen t
Mode MO S F E
T
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MOSFETPrinciple :
is that the source-to-drain current(SD current) is
controlled by the gate voltage, or better, by the gateelectric field.
Heart: MOS Capacitor
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MOS Capacitor
Figure 1: A Parallel Platecapacitor
Figure 2: A corresponding
MOS capacitor
Figure 3: The MOScapacitor withaccumulation of holes
• If the electric field penetrates the
semiconductor, the holes in the p-type
semiconductor will experience a force
toward the semiconductor interface
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MOS Capacitor(Cont..)
Figure 1: Effect of +Vegate bias
Figure 2: Induced space charge
region due to moderate +veate bias
Figure 3: Due to larger+ve gate bias
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MOS Capacitor(Cont..)When a larger positive voltage is applied to the gate,
the magnitude of the induced electric field increases.
Minority carrier electrons are attracted to the oxidesemiconductor interface, as shown in Figure
This region of minority carrier electrons is called an
electron inversion layer. The magnitude of the
charge in the inversion layer is a function of theapplied gate voltage.
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MOSFET(Cont..)Therefore , apply the concepts of concepts of an inversion
layer charge in a MOS capacitor to create a transistor.
Such transistor is called Metal Oxide Semiconductor Field
Effect Transistor
Also called Insulated Gate FET
Depending upon the type of mode, it can be classified into
Depletion mode MOSFET
Enhancement Mode MOSFET
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MOSFET(Cont..)Enhancement Mode:
The term enhancement mode means that a voltage must
be applied to the gate to create an inversion layer.For the MOS capacitor with a p-type substrate, a positive
gate voltage must be applied to create the electron inversion
layer.(nMOS E-MOSFET)
For the MOS capacitor with an n-type substrate, a negative
gate voltage must be applied to create the hole inversion
layer.(pMOS E-MOSFET)
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MOSFET(Cont..)Depletion Mode:
The term depletion mode means that a channel exists
even at zero gate voltage.A negative gate voltage must be applied to the n-channel
depletion mode MOSFET to turn the device off.(much
behave like n channel FET)
NMOS D-MOSFET
PMOS D-MOSFET
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MOSFET(Cont..)Channel is established due to the implant even when
Vgs = 0 and the channel can be cut off by applying a
negative voltage between the gate and source.
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Enhancement Mode Transistor
Metal
p-diffusion
n-diffusion
Poly silicon
oxide
p-Substrate
n-Substrate
depletion
Symbols:
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NMOS E-Mode Transistor
Figure: nMOS Enhancement modetransistor
• Lightly doped p-type
substrate• Tow heavily doped N+
regions are diffused• Thin Sio2 is grown over the
entire surface
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Operation:1. When Vgs < Vtn no inversion layer no conduction
2. When Vgs > Vtn electron inversion layer
but no conduction since Vds=0
5. When Vgs > Vtnelectron inversion layer conductiontakes place
but the transistor in non saturation region since Vds< Vgs-
Vtn
6. When Vgs > Vtn
electron inversion layer
conductiontakes place
but the transistor in saturation region since Vds >Vgs-Vtn
Where Vgs-Vtn= Vds(sat)
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Operation :
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Operation(Cont..)
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Characteristics:
Figure: VI Characteristics of n channel E-
MOSFET
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Silicon wafer Fabrication
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n-MOS fabrication process
1) Process is carried out on a thin wafer (75 to150 mm dia, .4mm thick)
Doped with boron impurity concentration of 1015/cm3 to make substrate
Substrate
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n-MOS fabrication process
2) A layer of SiO2 grown all over the surface(1µm thick) to protect.
SubstrateSiO2
RVR & JC College of Engineering- B
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Photolithography
3) Then the oxidized wafer is covered withPhoto resist.
SubstrateSiO2
Photo-Resist
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Photolithography
4) Now the wafer is exposed to UV Lightthrough a photo mask to define regions.
SubstrateSiO2
Photo-Resist
Photo-Mas
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Photolithography
5.1) Now oxide which is unprotected fromphotoresist is etched away.
SubstrateSiO2
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Photolithography
5.2) The rest of the photo resist is removed. Then the further fabrication process iscarried out, say doping.
SubstrateSiO2 SiO2
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6) Thin layer of SiO2(0.1µm) grown and thenpolysilicon is deposited on top to form gatestructur.
6) Polysilicon layer consists of heavily doped
polysilicon depositd by CVD.
Substrate
SiO2 Thinox
Polysilicon on thin oxid
Poly Si
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Metallization
7) Use mask to remove exposed area intowhich n-type impurities(phosphorus) are tobe diffused to form source and drain.
Substrate
SiO2
Thinox
Poly Si
n n
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Metallization
8) Again thinox is grown all over the surfaceand is then masked to expose selectedareas of gate, drain and source to makeContact holes (cut)
Substrate
SiO2 Thinox
Poly Si
n n
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Metallization
9) Finally, whole chip is metal deposited overits surface for required interconnectionpattern.
Substrate
SiO2 Thinox
Poly Si
n n
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nMOS FabricationStep 1:
Step 2:
Step 3:
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nMOS FabricationStep 4:
Step 5:
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nMOS Fabrication
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CMOS fabricationWhen we need to fabricate both nMOS and pMOS
transistors on the same substrate we need to followdifferent processes.
The three different processes are , P-well process ,N-well process and Twin tub process.
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CMOS fabricationTo accommodate both pMOS and nMOS devices, special
regions must be created in which the we place semiconductor
is opposite to the substrate type.
These regions are called wells or tubes
A p-well is created in the p-type substrate, alternatively an n-
well is created in the n-type substrate
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CMOS fabricationIn the simple n-well CMOS fabrication technology
The nMOS transistor is crated in the p-type substrate and
The pMOS transistor is crated in the n-well which is built in into the P-type
substrate
Similarly, in the p-well CMOS fabrication technology
The pMOS transistor is crated in the n-type substrate and
The nMOS transistor is crated in the p-well which is built in into the p-type
substrate
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N-well process- Flow chart
Main step in a typical n-well process
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Formation of n-well regions
Define nMOS and pMOS active areas
Field and gate oxidations (thinox)
Form and pattern polysilicon
p+ diffusion
n+ diffusion
Contact cuts
Deposit and pattern metallization
Over glass with cuts for bonding pads
Main step in a typical n well process
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Poly silicon patterning
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P-diffusion
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Metallization
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Mask sequence.
Mask 1: Defines the areas in which the deep p-well
diffusion takes place. Mask 2: Defines the thin oxide region (where the thick
oxide is to be removed or stripped and thin oxide grown) Mask 3: It’s used to pattern the polysilicon layer which is
deposited after thin oxide.
P-well process
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Mask 4: A p+ mask (anded with mask 2) to define areas
where p-diffusion is to take place.
Mask 5: We are using the –ve form of mask 4 (p+ mask) It
defines where n-diffusion is to take place.
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Mask 6: Contact cuts are defined using this mask.
Mask 7: The metal layer pattern is defined by this mask.
Mask 8: An overall passivation (overglass) is now applied and italso defines openings for accessing pads.
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n-Well CMOS
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Twin-tub COMSn-type material and then we create both n-well and p-
well region.
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Bi-CMOSDriving capability of MOS transistors is less
Bi-CMOS technology capable to drive large
capacitive loads.
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1. The npn transistor is formed an n-well & the additional
p+ base region is located in the well to form the p-base
region of the transistor.
2. The second additional layer, the buried n+ subcollector (BCCD) is added to reduce the n-well (collector)
resistance & thus improve the quality of the bipolar
transistor .
Bi-CMOS
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Comparison between CMOS and
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pBipolar technologies
Low static power dissipation
High input impedance
Scalable threshold voltage
High noise margin
High packing density
High delay sensitivity to load
Low output drive current
Low gm
Bidirectional capability
A near ideal switching device
High power dissipation
Low input impedance
Low voltage swing logic
Low packing density
Low delay sensitivity to load
High output drive current
High gm
Essentially unidirectional
CMOS Bipolar technologies
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cost versus delay graph
CMOS for logic
BiCMOS for I/O
ECL for critical highspeed parts
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