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Chapter 11: Basic I/O Interface
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Chapter Objectives
. E3p$ain the operation of the basic input andoutput interfaces!
. 4ecode an -5 165 and 725bit I/O de&ice so
that they can be used at any I/O port address!. 4efine handsha8ing and e3p$ain ho( to use it
(ith I/O de&ices!
. Interface and progra the -2C,,prograab$e para$$e$ interface!
Upon completion of this chapter, you will be able to:
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Chapter Objectives
. Interface C4 disp$ays E4 disp$ays8eyboards 4C 4C and &arious other
de&ices to the -2C,,!
. Interface and progra the 16,,0 seria$counications interface adapter!
. Interface and progra the -2,+
prograab$e inter&a$ tier!
Upon completion of this chapter, you will be able to:
cont(;
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Chapter Objectives
. Interface an ana$og5to5digita$ con&erter and adigita$5to5ana$og con&erter to the
icroprocessor!
. Interface both 4C and stepper otors to theicroprocessor!
Upon completion of this chapter, you will be able to:
cont(;
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
11–1 IN!O O I"O IN#!$%C#
. I/O instructions I' I'# O" and O"#; are
e3p$ained!. $so iso$ated direct or I/O apped I/O; and
eory5apped I/O the basic input and output
interfaces and handsha8ing!. <no($edge of these topics a8es it easier to
understand the connection and operation of the
prograab$e interface coponents
and I/O techni=ues!
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The Intel Microprocessors:8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
he I"O Instructions
. One type of instruction transfers inforation
to an I/O de&ice O";!
. nother reads fro an I/O de&ice I';!
. Instructions are a$so pro&ided to transfer
strings of data bet(een eory and I/O!
> I'# and O"# found e3cept the -0-6/-0--
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. Instructions that transfer data bet(een an I/O
de&ice and the icroprocessor?s accuu$ator
@ or E@; are ca$$ed IN and OU!. he I/O address is stored in register 4@ as a
165bit address or in the byte p-; iediate$y
fo$$o(ing the opcode as an -5bit address! > Inte$ ca$$s the -5bit for p-; a fi&ed address
because it is stored (ith the instruction usua$$y
in a %OA
. he 165bit address is ca$$ed a variableaddress because it is stored in a 4@ and then
used to address the I/O de&ice!
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. Other instructions that use 4@ to address
I/O are the I'# and O"# instructions!
. I/O ports are - bits in (idth! > a 165bit port is actua$$y t(o consecuti&e -5bit
ports being addressed
> a 725bit I/O port is actua$$y four -5bit ports
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. hen data are transferred using I' or O"
the I/O address port number or sip$y
port; appears on the address bus!. E3terna$ I/O interface decodes the port
nuber in the sae anner as a eory
address! > the -5bit fi3ed port nuber p-; appears on
address bus connections * >0 (ith bits
1, >- e=ua$ to 000000002
> connections abo&e 1, are undefined for
I/O instruction
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. he 165bit &ariab$e port nuber 4@;
appears on address connections 1, >0!
. he first 2,6 I/O port addresses 00>;are accessed by both fi3ed and &ariab$e I/O
instructions!
> any I/O address fro 0100 to is on$y accessed by the &ariab$e I/O address
. In a PC coputer a$$ 16 address bus bits
are decoded (ith $ocations 0000>07! > used for I/O inside the PC on the I#
industry standard architecture; bus
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. I'# and O"# instructions address an I/O
de&ice using the 4@ register!
> but do not transfer data bet(een accuu$ator and I/O de&ice as do the I'/O" instructions
> Instead they transfer data bet(een eory
and the I/O de&ice
. Pentiu + and Core2 operating in the 6+5bit
ode ha&e the sae I/O instructions!
. here are no 6+5bit I/O instructions in the 6+5
bit ode!
> ost I/O is sti$$ - bits and $i8e$y (i$$ reain so
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Isolated and 'emory('apped I"O
. (o different ethods of interfacing I/O:
isolated I"O and memory(mapped I"O!
. In iso$ated I/O the I' I'# O" and O"#
transfer data bet(een the icroprocessor?s
accuu$ator or eory and the I/O de&ice!. In eory5apped I/O any instruction that
references eory can accop$ish the
transfer!. he PC does not use eory5apped I/O!
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Isolated I/O
. he ost coon I/O transfer techni=ue
used in the Inte$5based syste is iso$ated I/O! > isolated describes ho( I/O $ocations are iso$ated
fro eory in a separate I/O address space
. ddresses for iso$ated I/O de&ices ca$$edports are separate fro eory!
. Because the ports are separate the user can
e3pand the eory to its fu$$ siDe (ithoutusing any of eory space for I/O de&ices!
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. disad&antage of iso$ated I/O is that data
transferred bet(een I/O and icroprocessor
ust be accessed by the I' I'# O" andO"# instructions!
. #eparate contro$ signa$s for the I/O space are
de&e$oped using A/IO and /% ; (hichindicate an I/O read IO%C; or an I/O (rite
%4; operation!
. hese signa$s indicate an I/O port address(hich appears on the address bus is used
to se$ect the I/O de&ice!
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
$i)ure 11–1 he eory and I/O aps for the -0-6/-0-- icroprocessors! a;
Iso$ated I/O! b; Aeory5apped I/O!
> in the PC iso$ated I/Oports are used to contro$
periphera$ de&ices
> an -5bit port address isused to access de&ices$ocated on the systeboard such as the tierand 8eyboard interface
> a 165bit port is used to
access seria$ and para$$e$ports &ideo and dis8 dri&esystes
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Memory-Mapped I/O
. Aeory5apped I/O does not use the I' I'#
O" or O"# instructions!. It uses any instruction that transfers data bet(een
the icroprocessor and eory!
>treated as a eory $ocation in eory ap
. d&antage is any eory transfer instruction can
access the I/O de&ice!
. 4isad&antage is a portion of eory syste is
used as the I/O ap!
> reduces eory a&ai$ab$e to app$ications
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
asic Input and Output Interfaces
. he basic input de&ice is a set of three5state
buffers!
. he basic output de&ice is a set of data
$atches!
. he ter I' refers to o&ing data 'rom the
I/O de&ice into the icroprocessor and
. he ter O" refers to o&ing data out of
the icroprocessor to the I/O de&ice!
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
The Basic Input Interface
. hree5state buffers are used to construct the
-5bit input port depicted in igure 11>7!
. E3terna$ data are connected to the inputs
of the buffers!
> buffer outputs connect to the data bus
. he circuit of a$$o(s the processor to read the
contents of the eight s(itches that connect to
any -5bit section of the data bus (hen these$ect signa$ becoes a $ogic 0!
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
$i)ure 11–- he basic input interface i$$ustrating the connection of eight s(itches!
'ote that the *+#2++ is a three5state buffer that contro$s the app$ication of the
s(itch data to the data bus!
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. hen the I' instruction e3ecutes contentsof the s(itches copy to the register!
. his basic input circuit is not optiona$ andust appear any tie input data areinterfaced to the icroprocessor!
. #oeties it appears as a discrete part ofthe circuit as sho(n in igure 11>7!
> a$so bui$t into a prograab$e I/O de&ices
. #i3teen5 or 725bit data can a$so be interfaced
but is not near$y as coon as -5bit data!
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
The Basic Output Interface
. %ecei&es data fro the processor and usua$$y
ust ho$d it for soe e3terna$ de&ice! > $atches or f$ip5f$ops $i8e buffers in the input
de&ice are often bui$t into the I/O de&ice
. ig 11>+ sho(s ho( eight $ight5eitting diodesE4s; connect to the processor through a set of
eight data $atches!
. he $atch stores the nuber output by the
icroprocessor fro the data bus so that theE4s can be $it (ith any -5bit binary nuber!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
$i)ure 11–. he basic output interface connected to a set of E4 disp$ays!
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. atches ho$d the data because (hen theprocessor e3ecutes an O" data are on$ypresent on the data bus for $ess than 1!0 )s!
> the &ie(er (ou$d ne&er see the E4s i$$uinate
. hen the O" e3ecutes data fro @or E@ transfer to the $atch &ia the data bus!
. Each tie the O" e3ecutes the #E signa$acti&ates capturing data to the $atch!
> data are he$d unti$ the ne3t O"
. hen the output instruction is e3ecuted datafro the register appear on the E4s!
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
/andsha0in)
. Aany I/O de&ices accept or re$ease inforation
s$o(er than the icroprocessor!. ethod of I/O contro$ ca$$ed handsha0in) or
pollin) synchroniDes the I/O de&ice (ith the
icroprocessor!. n e3ap$e is a para$$e$ printer that prints a fe(
hundred characters per second CP#;!
. he processor can send data uch faster!
> a (ay to s$o( the icroprocessor do(n to atch
speeds (ith the printer ust be de&e$oped
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. ig 11>, i$$ustrates typica$ input and output
connections found on a printer!
> data transfers &ia data connections 4* >40;. #CII data are p$aced on 4* >40 and a pu$se
is then app$ied to the #B connection!
> B"# indicates the printer is busy > #B is a c$oc8 pu$se used to send data to printer
. he strobe signa$ sends or c$oc8s the data
into the printer so that they can be printed! > as the printer recei&es data it p$aces $ogic 1 on
the B"# pin indicating it is printing data
$i 11 h 4B2, t f d t d th C t i 76 i
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
$i)ure 11– he 4B2, connector found on coputers and the Centronics 765pin
connector found on printers for the Centronics para$$e$ printer interface!
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Barry B! Brey
. he soft(are po$$s or tests the B"# pin todecide (hether the printer is busy!
> If the printer is busy the processor (aits > if not the ne3t #CII character goes to the printer
. his process of interrogating the printer orany asynchronous de&ice $i8e a printer isca$$ed handsha8ing or po$$ing!
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Barry B! Brey
. ig 11>6 sho(s a togg$e s(itch proper$y
connected to function as an input de&ice!
. pu$$5up resistor ensures (hen the s(itch isopen the output signa$ is a $ogic 1!
> (hen the s(itch is c$osed it connects to
ground producing a &a$id $ogic 0 $e&e$. standard range of &a$ues for pu$$5up
resistors is bet(een 1< Oh and 10< Oh!
$i)ure 11 2 sing$e po$e sing$e thro( s(itch interfaced as a de&ice
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Barry B! Brey
$i)ure 11–2 sing$e5po$e sing$e5thro( s(itch interfaced as a de&ice!
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Barry B! Brey
. Aechanica$ s(itch contacts physica$$y bounce(hen they are c$osed
> (hich can create a prob$e if a s(itch is usedas a c$oc8ing signa$ for a digita$ circuit
. o pre&ent prob$es (ith bounces one of thecircuits sho(n in ig 11>* can be used!
> the first is a c$assic te3tboo8 bounce e$iinator
> second is a ore practica$ &ersion of the sae
. he first &ersion costs ore to construct
> the second costs re=uires no pu$$5up resistorsand t(o in&erters instead of t(o ''4 gates
$i)ure 11 3 4ebouncing s(itch contacts: a; con&entiona$ debouncing and b;
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$i)ure 11–3 4ebouncing s(itch contacts: a; con&entiona$ debouncing and b;
practica$ debouncing!
> as the H input fro the s(itch becoes a $ogic 0it changes the state of the f$ip5f$op
> if the contact bounces a(ay fro the H input thef$ip5f$op reebers no change occurs and thusno bounce
O
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Output Devices
. Output de&ices are ore di&erse than input
de&ices but any are interfaced in a uniforanner!
. Before an output de&ice can be interfaced (e
ust understand &o$tages and currents fro theicroprocessor or interface!
. Go$tages are 5copatib$e fro the
icroprocessor of the interfacing e$eent!
> $ogic 0 0!0 G to 0!+ G
> $ogic 1 2!+ G to ,!0 G
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. Currents for a processor and any interfacing
coponents are $ess than for standard !
> ogic 0 0!0 to 2!0 > $ogic 1 0!0 to +00 J
. ig 11>- sho(s ho( to interface a sip$e
E4 to a icroprocessor periphera$ pin! > a transistor dri&er is used in 11>-a;
> a in&erter is used in 11>-b;
. he in&erter standard &ersion; pro&idesup to 16 of current at a $ogic 0 $e&e$
> ore than enough to dri&e a standard E4
$i)ure 11–4 Interfacing an E4: a; using a transistor and b; using an in&erter
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$i)ure 11–4 Interfacing an E4: a; using a transistor and b; using an in&erter!
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. input signa$ has iniu &a$ue of 2!+ G
. 4rop across eitter5base Kunction is 0!* G!
. he difference is 1!* G > the &o$tage drop across the resistor
. he &a$ue of the resistor is 1!* G L 0!1 or
1*< ! > as 1*< is not a standard &a$ue an 1-<
resistor is chosen
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. In 11>-a; (e e$ected to use a s(itchingtransistor in p$ace of the buffer!
> 2'2222 is a good $o(5cost genera$5purposes(itching transistor (ith a iniu gain of 100
> co$$ector current is 10 F so base current (i$$be 1/100 of co$$ector current of 0!1
. o deterine the &a$ue of the base current>$iiting resistor use the 0!1 base currentand a &o$tage drop of 1!* G across the basecurrent>$iiting resistor!
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. #uppose (e need to interface a 12 G 4C 1otor to the icroprocessor!
. e cannot use a in&erter: > 12 G signa$ (ou$d burn out the in&erter
> current far e3ceeds 16 in&erter a3iu
. e cannot use a 2'2222 transistor:
> a3iu current is 2,0 to ,00 depending on the pac8age sty$e chosen
. he so$ution is to use a 4ar$ington5pair such
as a IP120! > costs 2,M can hand$e + current (ith heat sin8
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. ig 11>9 i$$ustrates a otor connected to the4ar$ington5pair (ith a iniu current gainof *000 and a a3iu current of +!
. Ga$ue of the bias resistor is ca$cu$ated e3act$ythe sae as the one used in the E4 dri&er!
. he current through the resistor is 1!0 L*000 or about 0!1+7 !
. Go$tage drop is 0!9 G because of the t(odiode drops base/eitter Kunctions;!
. he &a$ue of the bias resistor is 0!9 G L 0!1+7 or 6!29< !
$i)ure 11–5 4C otor interfaced to a syste by using a 4ar$ington5pair
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$i)ure 11 5 4C otor interfaced to a syste by using a 4ar$ington pair!
> he 4ar$ington5pair ust usea heat sin8 because of the
aount of current > the diode ust be present to
pre&ent the 4ar$ington5pair fro being destroyed byinducti&e 8ic8bac8
11 * I"O +O! %66!#77
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11–* I"O +O! %66!#77
6#CO6IN8
. Gery sii$ar to eory address decoding
especia$$y for eory5apped I/O de&ices!
. he difference bet(een eory decoding
and iso$ated I/O decoding is the nuber of
address pins connected to the decoder!
. In the persona$ coputer syste (e a$(ays
decode a$$ 16 bits of the I/O port address!
6 di 4 it I"O + t %dd
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6ecodin) 4(it I"O +ort %ddresses
. i3ed I/O instruction uses an -5bit I/O port address
that on 1, >0 as 0000>00! > (e often decode on$y address connections
* >0 for an -5bit I/O port address
.he 4@ register can a$so address I/O ports 00>!
. If the address is decoded as an -5bit address (e
can ne&er inc$ude I/O de&ices using a 165bit
address! > the PC ne&er uses or decodes an -5bit address
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. igure 11>10 sho(s a *+#17- decoder
that decodes -5bit I/O ports 0 5 *!
> identica$ to a eory address decoder e3cept(e on$y connect address bits * >0 to the
inputs of the decoder
. igure 11>11 sho(s the P4 &ersion using a
N22G10 a $o(5cost de&ice; for this
decoder!
. he P4 is a better decoder circuit because
the nuber of integrated circuits has been
reduced to one de&ice!
$i)ure 11–19 port decoder that decodes -5bit I/O ports! his decoder generates
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) p p g
acti&e $o( outputs for ports 0>*!
$i)ure 11–11 P4 that generates part se$ection signa$s
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) g p g
6ecodin) 12 it I"O +ort %ddresses
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6ecodin) 12(it I"O +ort %ddresses
. PC systes typica$$y use 165bit I/O addresses!
> 165bit addresses rare in ebedded systes
. he difference bet(een decoding an -5bit and a
165bit I/O address is that eight additiona$
address $ines 1, >-; ust be decoded!. igure 11>12 i$$ustrates a circuit that contains a
P4 and a +5input ''4 gate used to decode
I/O ports E->E!. P4 generates address strobes for I/O ports
$i)ure 11–1* P4 that decodes 165bit I/O ports E- through E!
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) p g
4 and 12 it ide I"O +orts
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4( and 12(it ide I"O +orts
. 4ata transferred to an -5bit I/O de&ice e3ist in
one of the I/O ban8s in a 165bit processor suchas -07-6#@!
. he I/O syste on such a icroprocessor
contains t(o -5bit eory ban8s!. ig 11>17 sho(s separate I/O ban8s for a
165bit syste such as -07-6#@!
. Because t(o I/O ban8s e3ist any -5bit I/O(rite re=uires a separate (rite!
$i)ure 11–1- he I/O ban8s found in the -0-6 -01-6 -02-6 and -07-6#@!
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I/O d d ?t i t t b
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Barry B! Brey
. I/O reads don?t re=uire separate strobes!
> as (ith eory the processor reads on$y thebyte it e3pects and ignores the other byte
> a read can cause prob$es (hen an I/O de&iceresponds incorrect$y to a read operation
. ig 11>1+ sho(ss a syste (ith t(o different
-5bit output de&ices $ocated at +0 and +1!. hese are -5bit de&ices and appear in
different I/O ban8s!
> thus separate I/O (rite signa$s are generated toc$oc8 a pair of $atches that capture port data
$i)ure 11–1. n I/O port decoder that se$ects ports +0 and +1 for output data!
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> a$$ I/O ports
use -5bitaddresses
> ports +0 +1 can be
addressedas separate-5bit ports
> or as one
165bit port
ig 11 1, sho(s a 16 bit de&ice connected
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. ig 11>1, sho(s a 165bit de&ice connectedto function at -5bit addresses 6+ 6,!
. he P4 decoder does not ha&e a connectionfor address bits BE 0; and BE because
the signa$s don?t app$y to 165bit5(ide de&ices!
. he progra for the P4 i$$ustrated inE3ap$e 11>, sho(s ho( the enab$esigna$s are generated for the three5statebuffers *+C2++; used as input de&ices!
$i)ure 11–1 165bit5(ide port decoded at I/O addresses 6+ and 6,!
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-* it ide I"O +orts
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-*(it(ide I"O +orts
. Aay e&entua$$y becoe coon because of ne(er
buses found in coputer systes!. he EI# syste bus supports 725bit I/O as (e$$ as
the GE# $oca$ and current PCI bus!
> not any I/O de&ices are 72 bits in (idth
. ig 11>16 sho(s a 725bit input port for -07-64@ 5
-0+-64@ icroprocessor!
. he circuit uses a sing$e P4 to decode the I/O
ports and four *+C2++ buffers to connect the I/Odata to the data bus!
$i)ure 11–12 725bit5(ide port decoded at *0 through *7 for the -0+-64@
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Barry B! Brey
icroprocessor!
> I/O ports decodedby this interfaceare the -5bit ports*0>*7
> hen (riting to
access this portit is crucia$ to usethe address *0for 725bit input
> as instructionI' E@ *0
. ith the Pentiu Core2 and their 6+ bit data
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Barry B! Brey
. ith the Pentiu>Core2 and their 6+5bit databuses I/O ports appear in &arious ban8s asdeterined by the I/O port address!
. 725bit I/O access in the Pentiu systecan appear in any four consecuti&e I/O ban8s!
> 725bit ports 0100>0107 appear in ban8s 0>7
. I/O address range ust begin at a $ocation(here the rightost t(o bits are Deros!
> 0100>0107 is a$$o(ab$e
> 0101>010+ is not
. idest I/O transfers are 72 bits and there are
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. idest I/O transfers are 72 bits and there areno I/O instructions to support 6+5bit transfers!
> true for Pentiu + or Core2 in the 6+5bit ode
. #uppose (e need to interface a 165bit5(ideoutput port at I/O address 2000 and 2001!
> interface is i$$ustrated in igure 11>1*
> P4 progra is $isted in E3ap$e 11>*
. he prob$e that can arise is (hen the I/Oport spans across a 6+5bit boundary!
> e3ap$e a 165bit5 port at 200* and 200-
$i)ure 11–13 Pentiu + interfaced to a 165bit5(ide I/O port at port addresses
2000 d 2001
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2000 and 2001!
11–- /# +!O8!%''%;#
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11–- /# +!O8!%''%;#
+#!I+/#!%;
. -2C,, pro)rammable peripheral interface
PPI; is a popu$ar $o(5cost interface
coponent found in any app$ications!
. he PPI has 2+ pins for I/O prograab$e in
groups of 12 pins and groups that operate in
three distinct odes of operation!
. -2C,, can interface any 5copatib$eI/O de&ice to the icroprocessor!
. he -2C,, CAO# &ersion; re=uires (ait
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. he -2C,, CAO# &ersion; re=uires (ait
states if operated (ith a processor using
higher than an - AD c$oc8! > a$so pro&ides at $east 2!, of sin8 $ogic 0;
current at each output a a3iu of +!0
. Because I/O de&ices are inherent$y s$o( (ait
states used during I/O transfers do not ipact
significant$y upon the speed of the syste!
. he -2C,, sti$$ finds app$ication e&en in the
$atest Core25based coputer syste!
. -2C,, is used for interface to the 8eyboard
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Barry B! Brey
. -2C,, is used for interface to the 8eyboard
and para$$e$ printer port in any PCs!
> found as a function (ithin an interfacing chip set > a$so contro$s the tier and reads data fro the
8eyboard interface
. n e3perientation board is a&ai$ab$e that
p$ugs into the para$$e$ port of a PC to a$$o(
access to an -2,, $ocated on the board!
. he -2,, is prograed in either asseb$y
$anguage or Gisua$ C through dri&ers
a&ai$ab$e (ith the board!
asic 6escription of the 4*C
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Barry B! Brey
asic 6escription of the 4*C
. ig 11>1- sho(s pin5outs of the -2C,, in
4IP and surface ount f$at pac8; forat!. he three I/O ports $abe$ed B and C; are
prograed as groups!
> group connections consist of port P* >P0; and the
upper ha$f of port C PC* >PC+;
> group B consists of port B PB* >PB0; and the $o(er ha$f
of port C PC7 >PC0;
. -2C,, is se$ected by its C# pin for prograingand reading/(riting to a port!
$i)ure 11–14 he pin5out of the -2C,, periphera$ interface adapter PPI;!
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. ab$e 11>2 sho(s I/O port assignents used
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Barry B! Brey
. ab$e 11>2 sho(s I/O port assignents usedfor prograing and access to the I/O ports!
. In the PC a pair of -2C,,s or e=ui&a$entsare decoded at I/O ports 60>67 and a$soat ports 7*->7*B!
. he -2C,, is a fair$y sip$e de&ice to
interface to the icroprocessor and progra!
. or -2C,, to be read or (ritten the C# inputust be $ogic 0 and the correct I/O address
ust be app$ied to the 1 and 0 pins!. %eaining port address pins are don*t cares!
. ig 11>19 sho(s an -2C,, connected to the
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Barry B! Brey
ig 11 19 sho(s an -2C,, connected to the-07-6#@ so it functions at -5bit addressesC0 port ; C2 port B; C+ port C;and C6 coand register;! > this interface uses the $o( ban8 of the I/O ap
. $$ -2C,, pins are direct connections to the
-07-6#@ e3cept the C# pin! he pin isdecoded/se$ected by a *+#17- decoder!
. %E#E to -2C,, sets up a$$ ports as
sip$e input ports using ode 0 operation! > initia$iDes the de&ice (hen the processor is reset
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. fter a %E#E no other coands are
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
fter a %E#E no other coands areneeded as $ong as it is used as an inputde&ice for a$$ three ports!
. -2C,, is interfaced to the PC at portaddresses 60>67 for 8eyboard contro$!
> a$so for contro$$ing the spea8er tier and other
interna$ de&ices such as eory e3pansion. It is a$so used for the para$$e$ printer port at
I/O ports 7*->7*B!
+ro)rammin) the 4*C
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
+ro)rammin) the 4*C
. -2C,, is prograed through t(o interna$
coand registers sho(n in igure 11>20!. Bit position * se$ects either coand byte
or coand byte B!
> coand byte progras functions of group and B
> byte B sets 1; or resets 0; bits of port C on$y
if the -2C,, is prograed in ode 1 or 2
. Nroup B port B and the $o(er part of port C;
are prograed as input or output pins!
$i)ure 11–*9 he coand byte of the coand register in the -2C,,! a;
Progras ports B and C b; #ets or resets the bit indicated in the se$ect a bit fie$d
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Progras ports B and C! b; #ets or resets the bit indicated in the se$ect a bit fie$d!
> group B operates in ode 0 or
ode 1 > ode 0 is basic input/output ode
that a$$o(s the pins of group B tobe prograed as sip$e input
and $atched output connections > Aode 1 operation is the strobed
operation for group B connections
> data are transferred through port B
> handsha8ing signa$s are pro&idedby port C
. Nroup port and the upper part of port C;
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
Nroup port and the upper part of port C;are prograed as input or output pins!
. Nroup can operate in odes 0 1 and 2!
> ode 2 operation is a bidirectiona$ ode ofoperation for port
. If a 0 is p$aced in bit position * of the
coand byte coand byte B is se$ected. his a$$o(s any bit of port C to be set 1; or
reset 0; if the -2C,, is operated in either
ode 1 or 2! > other(ise this byte is not used for prograing
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$i)ure 11–*1 n -5digit E4 disp$ay interfaced to the -0-- icroprocessor through
an -2C,, PI!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
an -2C,, PI!
> ports B are prograed asode 0; sip$e $atched output ports
> port pro&ides segent data inputsport B pro&ides a eans of se$ectingone disp$ay position at a tie foru$tip$e3ing the disp$ays
> the -2C,, is interfaced to an -0--through a P4 so it functions atI/O port nubers 0*00>0*07
> P4 decodes the I/O address andde&e$ops the (rite strobe for the %pin of the -2C,,
. %esistor &a$ues in ig 11>21 are chosen so
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
%esistor &a$ues in ig 11 21 are chosen sothe segent current is -0 !
> re=uired to produce a&erage 10 currentper segent as the disp$ays are u$tip$e3ed
. si35digit disp$ay uses a segent current of60 for an a&erage of 10 per segent!
. Pea8 anode current in an eight5digit disp$ayis ,60 se&en segents × -0 ;!
> a&erage anode current is -0
. In a si35digit disp$ay pea8 current (ou$d be+20 se&en segents × 60 ;!
. In this disp$ay the segent $oad resistor
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
In this disp$ay the segent $oad resistorpasses -0 current and has appro3iate$y7!0 G across it!
. he &a$ue of the resistor is 7!0 G L 1-0 7*!, Oh! he c$osest standard resistor &a$ue of 79 Oh is used in ig11>21!
. Prograing the -2C,, is accop$ished bythe short se=uence of instructions $isted inE3ap$e 11>9!
. Ports and B are prograed as outputs!
%n ;C6 6isplay Interfaced to the
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
%n ;C6 6isplay Interfaced to the
4*C
. C4s li<uid crystal displays; ha&e rep$aced
E4 disp$ays in any app$ications!
. ig 11>22 sho(s an Optre3 4AC520+-1 C4
disp$ay interfaced to an -2C,,! > 4AC520+-1 is a +5$ine by 205characters5per5$ine
disp$ay that accepts #CII code as input data
. It a$so accepts coands that initia$iDe it andcontro$ its app$ication!
$i)ure 11–** he 4AC520+-1 C4 disp$ay interfaced to the -2C,,!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. he data connections (hich are attached to
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
the -2C,, port are used to input disp$aydata and to read inforation fro the disp$ay!
. or a +5bit interface 4+ >4* pins are used
(here the data ust be foratted (ith thehigh nibb$e first fo$$o(ed by the $o( nibb$e!
. fe( ne(er OE4 de&ices contain a seria$interface that uses a sing$e pin for the data!
. o progra 4AC520+-1 it ust first be
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
p ginitia$iDed!
. his app$ies to any disp$ay using the4++*-0 itachi; disp$ay dri&er IC!
. he entire $ine of sa$$ disp$ay pane$s froOptre3 and ost other anufacturers is
prograed in the sae anner!
. o progra 4AC520+-1 it ust first beinitia$iDed!
> this app$ies to any disp$ay using the 4++*-0itachi; disp$ay dri&er integrated circuit
. Initia$iDation is accop$ished &ia the fo$$o(ing:
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Barry B! Brey
p g
> 1! ait at $east 1, s after GCC rises to ,!0 G
> 2! Output the function set coand 70; and(ait at $east +!1 s
> 7! Output the function set coand 70; asecond tie and (ait at $east 100 )s
> +! Output the function set coand 70; athird tie and (ait at $east +0 )s
> ,! Output the function set coand 7-; afourth tie and (ait at $east +0 )s
> 6! Output 0- to disab$e the disp$ay and (aitat $east +0 )s
> *! Output a 01 to hoe the cursor and c$ear
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
the disp$ay and (ait at $east 1!6+ s
> -! Output the enab$e disp$ay cursor off 0C;
and (ait at $east +0 )s > 9! Output 06 to se$ect auto5increent shift
the cursor and (ait at $east +0 )s
. #oft(are to accop$ish the initia$iDation ofthe C4 disp$ay is $isted in E3ap$e 11>12!
. he tie de$ays can a$so be obtained by
using a tier in C!
. fter initia$iDation tie de$ays are no $onger
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
y gneeded (hen sending data or anycoands to the disp$ay!
. he c$ear disp$ay coand sti$$ needs a tiede$ay as the busy f$ag is not used !
. Instead of a tie de$ay the busy f$ag is tested
to see (hether the disp$ay has cop$eted anoperation!
. he B"# procedure tests the C4 disp$ay
and on$y returns (hen the disp$ay hascop$eted a prior instruction!
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. he on$y other procedure needed for a basic
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
y pdisp$ay is the c$ear hoe cursor procedureca$$ed C# sho(n in E3ap$e 11>1,!
. his procedure uses the #E'4 acro frothe initia$iDation soft(are to send the c$earcoand to the disp$ay!
. ith C# and the procedures presented thusfar you can disp$ay any essage on thedisp$ay c$ear it disp$ay another essage
and basica$$y operate the disp$ay!
A Stepper Motor Interfaced to the
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
pp
82!!"
. nother de&ice often interfaced to a coputersyste is the stepper motor (
> a digita$ otor because it is o&ed in discrete
steps as it tra&erses through 760Q
. n ine3pensi&e stepper otor is geared to
o&e perhaps 1,Q per step
. ore cost$y high5precision stepper otorcan be geared to 1Q per step!
. In a$$ cases these steps are gained through
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
p g g
any agnetic po$es and/or gearing!
. igure 11>27 sho(s a four5coi$ stepper otorthat uses an arature (ith a sing$e po$e!
> t(o coi$s are energiDed
. If $ess po(er is re=uired one coi$ ay beenergiDed at a tie causing the otor to
step at +,Q 17,Q 22,Q and 71,Q!
. he otor is sho(n (ith the arature rotatedto four discrete p$aces ca$$ed fu$$ stepping!
> accop$ished by energiDing the coi$s as sho(n
$i)ure 11–*- he stepper otor sho(ing fu$$5step operation: a; +,Q b; 17,Q c; 22,Q
d; 71,Q!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. he otor is dri&en by 'P' 4ar$ington ap
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
pairs to pro&ide a $arge current to each coi$!
. circuit that can dri&e this stepper otor isi$$ustrated in ig 11>2+!
> (ith the four coi$s sho(n in p$ace
. his circuit uses the -2C,, to pro&ide dri&e
signa$s used to rotate the otor arature ineither the right5 or $eft5hand direction!
. sip$e procedure that dri&es the otor is
$isted in E3ap$e 11>16 in both asseb$y$anguage and as a function in C!
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#ey Matri$ Interface
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. <eyboards coe in a &ariety of siDes fro
standard 10158ey HE% 8eyboards tospecia$ 8eyboards that contain + to 16 8eys!
. ig 11>2, is a 8ey atri3 (ith 16 s(itches
interfaced to ports and B of an -2C,,! > the s(itches are fored into a + × + atri3
but any atri3 cou$d be used such as a 2 × -
. he 8eys are organiDed into four ro(s andco$uns: %O0 >%O7; CO0 >CO7;
$i)ure 11–* + × + 8eyboard atri3 connected to an -0-- icroprocessor through
the -2C,, PI!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
> the -2C,, is decoded at I/Oports ,0>,7 for an -0--
> port is prograed as aninput port to read the ro(s
> port B is prograed as an
output port to se$ect a co$un > a f$o(chart of the soft(are
re=uired to read a 8ey fro the8eyboard atri3 and debounce
the 8ey is i$$ustrated in ig 11>26
$i)ure 11–*2 he f$o(chart of a 8eyboard5scanning procedure!
8 t b d b d $$
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
> 8eys ust be debounced nora$$y(ith a tie de$ay of 10>20 s
> the soft(are uses a procedureca$$ed #C' to scan the 8eys andanother ca$$ed 4E10 to (aste10 s of tie for debouncing
> the ain 8eyboard procedure isca$$ed <E and appears inE3ap$e 11>1*
> the <E procedure is generic and
can hand$e any configuration froa 1 × 1 atri3 to an - × - atri3!
. he #hort4e$ay procedure is needed as the
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
coputer changes port B at a &ery high rate !
> the tie de$ay a$$o(s the data sent to port B to
sett$e to their fina$ state
. his is not needed if scan rate tie bet(eenoutput instructions; does not e3ceed 70 <D!
> if the scanning fre=uency is higher the de&icegenerates radio interference
. If so the CC (i$$ not appro&e app$icationin any accepted syste
> (ithout certification the syste cannot be so$d
'ode 1 7trobed Input
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. Causes port and/or port B to function as
$atching input de&ices! > a$$o(s e3terna$ data to be stored to the port
unti$ the icroprocessor is ready to retrie&e it
. Port C is used in ode 1 operationRnot for data
but for contro$ or handsha8ing signa$s!
> to he$p operate either or both port and B as strobed
input ports
. ig 11>2* sho(s ho( both ports are structured forode 1 strobed input operation!
$i)ure 11–*3 #trobed input operation ode 1; of the -2C,,! a; Interna$ structure
and b; tiing diagra!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
7i)nal 6efinitions for 'ode 1
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
7trobed Input
7. he strobe input $oads data to the port $atch
(hich ho$ds the inforation unti$ it is input to
the icroprocessor &ia the I' instruction!
I$
. Input buffer full is an output indicating thatthe input $atch contains inforation!
IN!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. Interrupt re<uest is an output that re=uests an interrupt! he
I'% pin becoes a $ogic 1 (hen #B returns to a $ogic 1!
C$eared (hen data are input fro the port by the processor!
IN#. Interrupt enab$e signa$ is neither input nor outputF it is an interna$
bit prograed &ia
port PC+ port ; or PC2 port B; bit position!
+C3, +C
2
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3 2
. he port C pins * and 6 are genera$5purpose
I/O pins that are a&ai$ab$e for any purpose!
Stro%ed Input &$ample
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. n e3ap$e of a strobed input de&ice is a
8eyboard!. he 8eyboard encoder debounces the 8ey
s(itches and pro&ides a strobe signa$
(hene&er a 8ey is depressed! > the data output contains #CII5coded 8ey code
. igure 11>2- i$$ustrates a 8eyboard connected
to strobed input port !
$i)ure 11–*4 "sing the -2C,, for strobed input operation of a 8eyboard!
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'ode 1 7trobed Output
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. ig 11>29 sho(s the interna$ configuration and
tiing diagra of -2C,, (hen operated as astrobed output de&ice under ode 1!
. #trobed output operation is sii$ar to ode 0
output operation!
> e3cept contro$ signa$s are inc$uded to pro&ide
handsha8ing
. hen data are (ritten to a strobed output port the
output buffer full signa$ becoes $ogic 0 toindicate data are present in the port $atch!
$i)ure 11–*5 #trobed output operation ode 1; of the -2C,,! a; Interna$ structureand b; tiing diagra!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
7i)nal 6efinitions for 'ode 1
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
7trobed Output
O$. Output buffer full goes $o( (hene&er data are output
O"; to the port or B $atch! he signa$ is set to $ogic
1 (hen the C< pu$se returns fro the e3terna$ de&ice!
%C=
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. he ac0nowled)e si)nal causes the OB
pin to return to $ogic 1! he C< signa$ is a response fro an e3terna$
de&ice indicating that it has recei&ed data fro the -2C,, port!
IN!. Interrupt re<uest often interrupts the processor (hen the
e3terna$ de&ice recei&es the data &ia the C< signa$! Hua$ified by
the interna$ I'E interrupt enable; bit!
IN#
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. Interrupt enable is neither input nor outputF
it is an interna$ bit prograed to enab$e or disab$e the I'% pin! I'E
is prograed using PC6 bit! I'E B is prograed using the PC2 bit!
+C., +C
. Port C pins PC+ and PC, are genera$5purpose I/O pins! he bit
set and reset coand is used to set or reset these t(o pins!
Stro%ed Output &$ample
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. he printer interface deonstrates ho( to
achie&e strobed output synchroniDationbet(een the printer and the -2C,,!
. igure 11>70 i$$ustrates port B connected to
a para$$e$ printer (ith eight data inputs forrecei&ing #CII5coded data a 4# data
strobe; input to strobe data into the printer
and an C< output to ac8no($edge the
receipt of the #CII character!
$i)ure 11–-9 he -2C,, connected to a para$$e$ printer interface that i$$ustrates thestrobed output ode of operation for the -2C,,!
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'ode * idirectional Operation
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. Aode 2 is a$$o(ed (ith group on$y!
. Port becoes bidirectiona$ a$$o(ing datatransit/recei&e o&er the sae eight (ires!
> usefu$ (hen interfacing t(o coputers
. $so used for IEEE5+-- para$$e$ high5speedNPIB )eneral( purpose instrumentation
bus; interface standard!
. igure 11>71 sho(s interna$ structure andtiing for ode 2 bidirectiona$ operation!
$i)ure 11–-1 Aode 2 operation of the -2C,,! a; Interna$ structure and b; tiingdiagra!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
7i)nal 6efinitions for idirectional
' d *
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. Interrupt re<uest is an output used to interrupt theicroprocessor for inputand output conditions!
'ode *
O$
. Output buffer full is an output indicatingthe output buffer contains data for the
bidirectiona$ bus!
IN!
%C=
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. %c0nowled)e is an input that enab$es the three5state buffers so that data can appear
on port ! If C< is $ogic 1 the output buffers of port are at their high5ipedance
state!
7. he strobe input $oads the port input $atch (ith e3terna$ data
fro the bidirectiona$
port bus!
+C9, +C
1, and +C
*
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. hese pins are genera$5purpose I/O pins in ode
2 contro$$ed by the bit set and reset coand!
I$
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. Input buffer full is an output used to signa$ that the input
buffer contains data for the e3terna$ bidirectiona$ bus!
IN#. Interrupt enable are interna$ bits I'E1 I'E2; that enab$e the I'% pin! he
state
of the I'% pin is contro$$ed through port C bits PC6 I'E1; and PC+ I'E2;!
The Bidirectional Bus
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. he bidirectiona$ bus is used by referencing
port (ith the I' and O" instructions!. o transit data through the bidirectiona$ bus
the progra first tests to deterine (hether
the output buffer is epty! > if so data are sent to the output buffer &ia O"
. he e3terna$ circuitry a$so onitors the signa$
to decide (hether the icroprocessor hassent data to the bus!
. o recei&e data through the bidirectiona$ port
bus IB is tested (ith soft(are to decide
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bus IB is tested (ith soft(are to decide
(hether data ha&e been strobed into the port!
> if IB 1 data is input using I'
. he e3terna$ interface sends data to the port
by using the #B signa$!
> the IB signa$ becoes $ogic 1 and data at
port are he$d inside the port in a $atch
. hen the I' e3ecutes the IB bit is c$eared
and data in the port are o&ed into !
. #ee E3ap$e 11>21 for a procedure!
. he I'% >interrupt re<uest; pin can be
acti&ated fro both directions of data f$o(
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acti&ated fro both directions of data f$o(
through the bus!
. If I'% is enab$ed by both I'E bits the
output and input buffers both cause interrupt
re=uests!
. his occurs (hen data are strobed into the
buffer using #B or (hen data are (ritten
using O"!
4*C 'ode 7ummary
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. igure 11>72 sho(s a graphica$ suary of
the three odes of operation for the -2C,,!. Aode 0 pro&ides sip$e I/O!
. Aode 1 pro&ides strobed I/O!
. Aode 2 pro&ides bidirectiona$ I/O!
. hese odes are se$ected through the
coand register of the -2C,,!
$i)ure 11–-* suary of the port connections for the -2C,, PI!
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he 7erial ##+!O' Interface
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. In Chapter 10 igure 10>27 a seria$
EEP%OA is i$$ustrated but at that point inthe te3t no I/O e3isted for an interface!
. #uppose that port C of an -2C,, is used for
connection to this interface and soft(are isneeded to dri&e the interface!
. he PC0 pin is prograed as an output to
send data and as an input to recei&e datafro the EEP%OA!
Chapter 19, $i)ure 19–*- seria$ EEP%OA interface!
this eory interface
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> this eory interfacehas t(o signa$ $ines
> one is a seria$ c$oc8#C;F the other abidirectiona$ seria$ data$ine #4;
> not eant to rep$acesyste ain eory
> it is fast enough for usic
or other $o(5speed data
. %efer to igure 10>2+!
. he data forat for the soft(are for reading
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. he data forat for the soft(are for readingand (riting data to the EEP%OA is a$so
i$$ustrated in E3ap$e 11>22!
. his soft(are is (ritten in C (ith soeasseb$y $anguage but it can a$so be
de&e$oped in asseb$y $anguage!. I/O port address for the coand register is
031207 and 031202 for the port C register!
> the tie de$ay shou$d be 1!2, )s for a datarate of +00 <D
Chapter 19, $i)ure 19–*. 4ata signa$s to the seria$ EEP%OA for a read or a (rite!
th i $ d t t i
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> the seria$ data containsthe address in the firstbyte as (e$$ as a de&icecode of 1010 (hichrepresents the EEP%OA
> other seria$ de&ices ha&edifferent de&ice codes
> this is fo$$o(ed by theeory $ocation and the
data in additiona$ bytes
11–. 4*. +!O8!%''%;#
IN#!?%; I'#!
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IN#!?%; I'#!
. he -2,+ consists of three independent165bit prograab$e counters timers;!
. Each counter is capab$e of counting in binary
or binary5coded decia$ BC4;! > a3iu a$$o(ab$e input fre=uency to any
counter is 10 AD
. "sefu$ (here the icroprocessor ustcontro$ rea$5tie e&ents!
. "sage inc$udes rea$5tie c$oc8s e&ent
counters and otor speed/direction contro$
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
counters and otor speed/direction contro$!
. ier appears in the PC decoded at ports
+0>+7 to do the fo$$o(ing:
> 1! Nenerate a basic tier interrupt that occurs
at appro3iate$y 1-!2 D
> 2! Cause the 4%A eory syste to be
refreshed
> 7! Pro&ide a tiing source to the interna$
spea8er and other de&ices!. ier in the PC is an -2,7 instead of -2,+!
4*. $unctional 6escription
11 77 f -2
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. igure 11>77 sho(s the pin5out of the -2,+
a higher5speed &ersion of the -2,7 and adiagra of one of the three counters!
. Each tier contains:
> a C< input (hich pro&ides the basic operating
fre=uency to the tier
> a gate input pin (hich contro$s the tier in soe
odes
> an output O"; connection to obtain the outputof the tier
$i)ure 11–-- he -2,+ prograab$e inter&a$ tier! a; Interna$ structure and b;pin5out! Courtesy of Inte$ Corporation!;
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. he signa$s that connect to the processor arethe data bus pins 4*>40; %4 % C# and
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
the data bus pins 4* 40; %4 % C# and
address inputs 1 and 0!
. ddress inputs are present to se$ect any ofthe four interna$ registers!
> used for prograing reading or (riting to a
counter
. ier Dero generates an 1-!2 D signa$ thatinterrupts the icroprocessor at interrupt
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interrupts the icroprocessor at interrupt&ector - for a c$oc8 tic8!
> often used to tie progras and e&ents in 4O#
. ier 1 is prograed for 1, )s used onthe PC to re=uest a 4A action used to
refresh the dynaic %A!. ier 2 is prograed to generate a tone
on the PC spea8er!
+in 6efinitions for 4*.
% %
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. he address inputs se$ect one of four interna$ registers (ithinthe -2,+! #ee ab$e 11>+ for the function of the 1 and 0
address bits!
C;=. he cloc0 input is the tiing source for each of the interna$
counters! his input is often connected to the PC< signa$
fro the icroprocessor syste bus contro$$er!
%9, %
1
C7
Chi l t b$ -2,+ f i
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. Chip select enab$es -2,+ for prograing
and reading or (riting a counter!8
. he )ate input contro$s the operation of the
counter in soe odes of operation
8N6
. 8round connects to the syste ground bus!
OU
t t t i h th f
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. counter output is (here the (a&efor
generated by the tier is a&ai$ab$e!!6
. !ead causes data to be read fro the -2,+
and often connects to the IO%C signa$!
?cc
. +ower connects to the ,!0 G po(er supp$y!
!
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. rite causes data to be (ritten to the -2,+
and often connects to (rite strobe IOC!
+ro)rammin) the 4*.
E h t i d b iti
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth EditionBarry B! Brey
. Each counter is prograed by (riting a
contro$ (ord fo$$o(ed by the initia$ count! > fig 11>7+ $ists the progra contro$ (ord structure
. he contro$ (ord a$$o(s the prograer to
se$ect the counter ode of operation andtype of operation read/(rite;!
> a$so se$ects either a binary or BC4 count
$i)ure 11–-. he contro$ (ord for the -2,+52 tier!
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. Each counter ay be prograed (ith acount of 1 to F count of 0 is e=ua$
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F =to $ 6,,76; or 10000 in BC4!
. ier 0 is used in the PC (ith a di&ide5bycount of 6+< ; to generate the1-!2 D 1-!196 D; interrupt c$oc8 tic8!
> tier 0 has a c$oc8 input fre=uency of +!** AD + or 1!192, AD
. he order of prograing is iportant foreach counter but prograing of differentcounters ay be inter$ea&ed for bettercontro$!
Modes of Operation
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Barry B! Brey
$i)ure 11–- he si3 odes of operation for the -2,+52 prograab$e inter&a$ tier!
he N input stops the count (hen 0 in odes 2 7 and +!
> si3 odes 0>,; of
a&ai$ab$e to each ofthe -2,+ counters
> each ode functions
(ith the C< inputthe gate N; contro$
signa$ and O"
signa$
'ode 9
. $$o(s -2,+ to be used as an e&ents counter
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. $$o(s -2,+ to be used as an e&ents counter!
. Output becoes $ogic 0 (hen the contro$(ord is (ritten and reains unti$ ' p$us the
nuber of prograed counts!
. 'ote that gate N; input ust be $ogic 1 toa$$o( the counter to count!
. If N becoes $ogic 0 in the idd$e of the
count the counter (i$$ stop unti$ N againbecoes $ogic 1!
'ode 1
. Causes function as a retriggerab$e onostab$e
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. Causes function as a retriggerab$e onostab$e
u$ti&ibrator one5shot;!
. N input triggers the counter so it de&e$ops a pu$se
at the O" connection that becoes $ogic 0 for
the duration of the count!
> if the count is 10 the O" connection goes$o( for 10 c$oc8ing periods (hen triggered
. If N input occurs (ithin the output pu$se the
counter is re$oaded and the O" connectioncontinues for the tota$ $ength of the count!
'ode *
. $$o(s the counter to generate a series of
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. $$o(s the counter to generate a series of
continuous pu$ses one c$oc8 pu$se (ide!
> pu$se separation is deterined by the count
. or a count of 10 output is $ogic 1 for nine c$oc8
periods and $o( for one c$oc8 period!
. he cyc$e is repeated unti$ the counter is
prograed (ith a ne( count or unti$ the N pin is
p$aced at $ogic 0!
> N input ust be $ogic 1 for this ode togenerate a continuous series of pu$ses
'ode -
. Nenerates a continuous s=uare (a&e at the
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. Nenerates a continuous s=uare (a&e at the
O" connection pro&ided the N pin is $ogic 1!. If the count is e&en output is high for one ha$f
of the count and $o( for one ha$f of the count!
. If the count is odd output is high for onec$oc8ing period $onger than it is $o(!
> if the counter is prograed for a count of ,
the output is high for three c$oc8s and $o( for
t(o c$oc8s
'ode .
. $$o(s a sing$e pu$se at the output
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. $$o(s a sing$e pu$se at the output!
. If count is prograed as 10 output is high for 10c$oc8ing periods and $o( for one period!
> the cyc$e does not begin unti$ the counter
is $oaded (ith its cop$ete count
. Operates as a soft(are triggered one5shot!
. s (ith odes 2 and 7 this ode a$so uses the N
input to enab$e the counter!
> N input ust be $ogic 1 for the counter tooperate for these three odes
'ode
. hard(are triggered one shot that functions
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. hard(are triggered one5shot that functions
as ode +! > e3cept it is started by a trigger pu$se on the
N pin instead of by soft(are
. his ode is a$so sii$ar to ode 1 because
it is retriggerab$e!
'eneratin( a )aveform *ith the82!+
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Barry B! Brey
82!+
. ig 11>76 sho(s an -2,+ connected to I/Oports 0*00 0*02 0*0+ and 0*06 of an
-07-6#@!
. he addresses are decoded by using a P4that a$so generates a (rite strobe signa$ for
the -2,+ (hich is connected to the $o(5order
data bus connections!
$i)ure 11–-2 he -2,+ interfaced to an - AD -0-6 so that it generates a 100 <Ds=uare (a&e at O"0 and a 200 <D continuous pu$se at O"1!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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. he P4 a$so generates a (ait signa$ for theicroprocessor that causes t(o (ait states
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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(hen the -2,+ is accessed!
. he (ait state generator connected to theicroprocessor actua$$y contro$s the nuberof (ait states inserted into the tiing!
. E3ap$e 11>2+ $ists the progra thatgenerates a 100 <D s=uare5(a&e at O"0and a 200 <D continuous pu$se at O"1!
,eadin( a ounter
. Each counter has an interna$ $atch read (ith
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. Each counter has an interna$ $atch read (ith
the read counter port operation! > the $atches (i$$ nora$$y fo$$o( the count
. If counter contents are needed the $atch can
reeber the count by prograing thecounter $atch contro$ (ord!
. #ee igure 11>7*!
> counter contents are he$d in a $atch unti$ read
$i)ure 11–-3 he -2,+52 counter $atch contro$ (ord!
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. hen a read fro the $atch or counter isprograed the $atch trac8s the contents!
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Barry B! Brey
. hen necessary for contents of ore than
one counter to be read at the sae tie theread5bac8 contro$ (ord is used
. I$$ustrated in igure 11>7-!
$i)ure 11–-4 he -2,+52 read5bac8 contro$ (ord!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. ith the read5bac8 contro$ (ord the C' bitis $ogic 0 to cause the counters se$ected byC'0 C'1 d C'2 t b $ t h d
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C'0 C'1 and C'2 to be $atched!
. If the status register is to be $atched then thebit is p$aced at $ogic 0!
. igure 11>79 sho(s the status register
(hich sho(s: > the state of the output pin
> (hether the counter is at its nu$$ state 0;
> ho( the counter is prograed
$i)ure 11–-5 he -2,+52 status register!
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6C 'otor 7peed and 6irectionControl
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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. n app$ication of -2,+ is as a otor speedcontro$$er for a 4C otor!
. ig 11>+0 sho(s the scheatic diagra
of the otor and associated dri&er circuitry!. It a$so i$$ustrates the interconnection of the
-2,+ a f$ip5f$op and the otor and its dri&er!
$i)ure 11–.9 Aotor speed and direction contro$ using the -2,+ tier!
> if H output of the *+#112 is $ogic 1
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p g the otor spins in its for(ard direction
> if $ogic 0 the otor spins in re&erse
> if f$ip5f$op output a$ternates bet(een$ogic 1 and 0 the otor spins in eitherdirection at &arious speeds
> if the duty cyc$e of the H output is ,0Sthe otor (i$$ not spin at a$$ and
e3hibits soe ho$ding tor=ue
. ig 11>+1 sho(s soe tiing diagras andeffects on the speed/direction of the otor!
E h t t $ t diff t
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. Each counter generates pu$ses at different
positions to &ary the duty cyc$e at the H output ofthe f$ip5f$op!
. his output is a$so ca$$ed pulse idth modulation(
. E3ap$e 11>2, $ists a procedure that contro$sthe speed and direction of the otor!
$i)ure 11–.1 iing for the otor speed and direction contro$ circuit of igure 11>+0!a; 'o rotation b; high5speed rotation in the re&erse direction and c; high5speed
rotation in the for(ard direction!
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11– 129 +!O8!%''%;#CO''UNIC%ION7 IN#!$%C#
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
. 'ationa$ #eiconductor Corp?s PC16,,04is a prograab$e counications interface
designed to connect to &irtua$$y any type of
seria$ interface!. 16,,0 is a uni&ersa$ asynchronous
recei&er/transitter "%; fu$$y copatib$e
(ith Inte$ icroprocessors!
. 16,,0 operates at 0>1!, A baud!
> baud rate is bps bits transferred per second;
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inc$uding start stop data and parity
> bps are bits per secondF Bps is bytes per second
. 16,,0 a$so inc$udes a prograab$e baud
rate generator and separate IOs for input
and output data to ease the $oad on theicroprocessor!
. Each IO contains 16 bytes of storage!
. he ost coon counications interfacefound in the PC and any odes!
%synchronous 7erial 6ata
. synchronous seria$ data are transitted and
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
$i)ure 11–.* synchronous seria$ data!
synchronous seria$ data are transitted and
recei&ed (ithout a c$oc8 or tiing signa$! > sho(n here are t(o fraes of asynchronous
seria$ data
> each frae contains a start bit se&en data bits
parity and one stop bit
. 4ia$5up counications systes of the past such
as Copu#er&e Prodigy and erica On$ine
used 10 bits for asynchronous seria$ data (ith
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used 10 bits for asynchronous seria$ data (ith
e&en parity!. Aost Internet and BB# ser&ices use 10 bits but
nora$$y do not use parity!
>instead eight data bits are transferred rep$acing parity(ith a data bit
. his a8es byte transfers of non5#CII data
uch easier to accop$ish!
129 $unctional 6escription
. ig 11>+7 sho(s pin5outs of a 16,,0 "%!
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Barry B! Brey
g p
.he de&ice is a&ai$ab$e as a +05pin 4IPdual in(line pac0a)e; or as a ++5pin PCC
plastic leadless chip carrier ;!
. (o cop$ete$y separate sections are responsib$e
for data counications! > the recei&er and the transitter
. Because each sections is independent 16,,0 is
ab$e to function in sip$e3 ha$f5dup$e3 or fu$$5dup$e3 odes!
$i)ure 11–
.- he pin5out of the 16,,0 "%!
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. aKor feature of the 16,,0 is its interna$recei&er and transitter IO first5in first5out; eories
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out; eories!
. Because each is 16 bytes deep the "%re=uires attention fro the processor on$yafter recei&ing 16 bytes of data!
> a$so ho$ds 16 bytes before the processor ust (ait for the transitter
. he IO a8es this "% idea$ (heninterfacing to high5speed systes because
$ess tie is re=uired to ser&ice it!
. simple& syste is one in (hich thetransitter or recei&er is used by itse$f!
h i A f d l ti ;
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> such as in an A fre<uency modulation;
radio station. half(duple& syste is a CB citi@ens
band; radio!
> transit and recei&e but not at the sae tie. full(duple& syste a$$o(s transission
and reception in both directionssiu$taneous$y!
> the te$ephone is a fu$$5dup$e3 syste
. he 16,,0 can contro$ a modem modulator"demodulator ; a de&ice thatcon&erts seria$ data into audio tones
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Barry B! Brey
con&erts seria$ data into audio tones
that can pass through the te$ephone syste!. #i3 pins on 166,0 are for ode contro$:
4#% data set ready; 4% data terminal
ready; C# clear(to(send; %# re<uest(to(send; %I rin) indicator ; and 4C4 datacarrier detect;!
. he ode is referred to as the data set and
the 16,,0 is referred to as the data terina$!
129 +in $unctions%
9, %
1, %
*
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Barry B! Brey
. he address inputs are used to se$ect an interna$ register for prograing and a$so data transfer!
. #ee ab$e 11>, for a $ist of eachcobination of the address inputs andthe registers se$ected!
9 1 *
%67. he address strobe input is used to $atch
the address $ines and chip se$ect $ines!
. If not needed as in the Inte$ syste;
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If not needed as in the Inte$ syste;
connect this pin to ground!
. he 4# pin is designed for use (ith
Aotoro$a icroprocessors!
%U6OU. he baud out pin is (here the c$oc8 signa$ generated by the baud rate generator fro
the transitter section is ade a&ai$ab$e!
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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. It is ost often connected to the %C< input to generate a recei&er c$oc8 that is e=ua$ to the
transitter c$oc8!
C79, C71, C7*
. he chip select inputs ust a$$ be acti&e to
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p p
enab$e the 16,,0 "%!
C7. he clear(to(send if $o(; indicates that the ode or data set is ready
to e3change inforation!
. his pin is often used in a ha$f5dup$e3 syste to turn the $ine around!
69–63
. he data bus pins are connected to the
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icroprocessor data bus!
6C6. 6ata carrier detect input is used by the ode to signa$ the
16,,0 that a carrier is present!
6!. 6ata terminal ready is an output that indicates that the data
terina$ 16,,0;
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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terina$ 16,,0;
is ready to function!
IN!. Interrupt re<uest is an output to the icroprocessor used to re=uest an interrupt
I'%1; (hen the 16,,0 has a recei&er error it has recei&ed data and the
transitter is epty!
66I7. he disable driver output becoes $ogic 0
to indicate the icroprocessor is reading
data fro the "%
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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data fro the "%!
. 44I# can be used to change the direction
of data f$o( through a buffer!
67!. 6ata set ready is an input to the 16,,0 indicating that the
ode or data set isready to operate!
'!. 'aster reset initia$iDes the 16,,0 and shou$d
be connected to the syste %E#E signa$
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
be connected to the syste %E#E signa$!
OU1, OU*. User(defined output pins that can pro&ide signa$s to a
ode or any other de&ice as needed in a syste!
!C;C=
. !eceiver cloc0 is the c$oc8 input to therecei&er section of the "%!
!6, !6. !ead inputs either ay be used; cause data to be read fro
the register specified by the address inputs to the "%!
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g p y p
!I. !in) indicator input is p$aced at $ogic 0 by
the ode to indicate the phone is ringing!
!7
. !e<uest(to(send is a signa$ to the odeindicating that the "% (ishes to send data!
7IN, 7OU. hese are the serial data pins! #I' accepts
seria$ data and #O" transits seria$ data
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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seria$ data and #O" transits seria$ data!
!A!6B. !eceiver ready is a signa$ used to transfer
recei&ed data &ia 4A techni=ues!
A!6B. ransmitter ready is a signa$ used to
transfer transitter data &ia 4A!
!, !. rite either ay be used; connects to the icroprocessor
(rite signa$ to transfer coands and data to the 16,,0!
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Barry B! Brey
g
AIN, AOU. hese are the ain cloc0 connections!
. crysta$ is connected across these pins to for a crysta$ osci$$ator or @I' is connectedto an e3terna$ tiing source!
+ro)rammin) the 129
. Prograing is a t(o5part process inc$udes
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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the initia$iDation dia$og and operationa$ dia$og!
. In the PC (hich uses the 16,,0 or its
prograing e=ui&a$ent I/O port addresses
are decoded at 7- 5 7 for COA port 0
and 2- 5 2 for COA port 2!
Initialiin( the .!!0 . Initia$iDation dia$og after a hard(are or soft(are
t i t f t t
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reset consists of t(o parts:
> prograing the $ine contro$ register
> prograing the baud rate generator
. he $ine contro$ register se$ects the nuber
of data bits stop bits and parity (hether e&en orodd or if parity is sent as a 1 or a 0;
. Baud rate generator is prograed (ith a di&isor
that deterines the baud rate of the transittersection!
. ig 11>++ i$$ustrates the $ine contro$ register!
. he $ine contro$ register is prograed by
t tti i f ti t t 011 ;
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outputting inforation to port 011 2 1 0;!
. he rightost t(o bits of the $ine contro$
register se$ect the nuber of transitted
data bits , 6 * or -;!
. 'uber of stop bits is se$ected by # in the
$ine contro$ register!
> if # 0 one stop bit is used
> if # 1 1!, stop bits are used for fi&e data bits
t(o stop bits (ith si3 se&en or eight data bits
$i)ure 11–
.. he contents of the 16,,0 $ine contro$ register!
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1ro(rammin( the Baud ,ate . he baud rate generator is prograed at
I/O dd 000 d 001 ;
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I/O addresses 000 and 001 2 1 0;!
. Port 000 is used to ho$d the $east significant part
of the 165bit di&isor and port 001 is used to ho$d
the ost significant part!
> &a$ue used for the di&isor depends on thee3terna$ c$oc8 or crysta$ fre=uency
. ab$e 11>* i$$ustrates coon baud rates
obtainab$e if an 1-!+72 AD crysta$ is usedas a tiing source!
Sample Initialiation
. #uppose an asynchronous syste re=uires
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se&en data bits odd parity a baud rate of
9600 and one stop bit!
. E3ap$e 11>2+ $ists a procedure to initia$iDe
the 16,,0 to function in this anner!
. ig 11>+, sho(s the interface to the -0--
icroprocessor using a P4 to decode the
-5bit port addresses 0 through *!
$i)ure 11–
. he 16,,0 interfaced to the -0-- icroprocessor at ports 000>00*!
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. fter the $ine contro$ register and baud ratedi&isor are prograed into the 16,,0 itis sti$$ not ready to function!
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y
. he IO contro$ register ust sti$$ beprograed!
> at port 2 in the circuit of igure 11>+,
. ig 11>+6 i$$ustrates the IO contro$ registerfor the 16,,0!
> the register enab$es the transitter recei&er bit 01; c$ears the transitter recei&er IOs
> it a$so pro&ides contro$ for the 16,,0 interrupts
$i)ure 11–
.2 he IO contro$ register of the 16,,0 "%!
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. he $ast section of E3ap$e 11>26 p$aces a* into the IO contro$ register!
. his enab$es the transitter and recei&er
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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
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his enab$es the transitter and recei&er
and c$ears both IOs!. he 16,,0 is no( ready to operate but
(ithout interrupts!
> interrupts are autoatica$$y disab$ed (henthe A% aster reset; input is p$aced at $ogic 1by the syste %E#E signa$!
Sendin( Serial Data
. Before seria$ data can be sent or recei&ed
d t 8 th f ti f th $i
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(e need to 8no( the function of the $ine
status register
> see igure 11>+*
. he $ine status register contains inforation
about error conditions and the state of the
transitter and recei&er!
. his register is tested before a byte is
transitted or can be recei&ed!
$i)ure 11–
.3 he contents of the $ine status register of the 16,,0 "%!
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,eceivin( Serial Data . o read recei&ed inforation fro the 16,,0
test the 4% bit of the $ine stat s register
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test the 4% bit of the $ine status register!
> e3ap$e 11>2- $ists a procedure to test the 4%
bit to decide if the 16,,0 has recei&ed any data
. "pon the reception of data the procedure tests
for errors! > if an error is detected the procedure returns
(ith e=ua$ to an #CII TU?
> if no error has occurred the procedure returns (ith e=ua$ to the recei&ed character
A,T &rrors . Errors detected by 16,,0 are:
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> parity fraing and o&errun errors
. hese errors shou$d not occur during
nora$ operation!
. parity error indicates the recei&ed datacontain the (rong parity!
> if a parity error occurs it indicates noise
(as encountered during reception
. framin) error indicates the start and stop
bits are not in their proper p$aces!
> occurs if the recei&er is recei&ing data at
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occurs if the recei&er is recei&ing data at
an incorrect baud rate
. n overrun error indicates data ha&e
o&errun the interna$ recei&er IO buffer!
> occurs on$y if the soft(are fai$s to read the datafro the "% before the recei&er IO is fu$$
11–2 %N%;O8(O(6I8I%; >%6CD 6I8I%;(O(%N%;O8 >6%C
CON?#!#!7
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CON?#!#!7
. hese de&ices are used to interface the
icroprocessor to the ana$og (or$d!
. Aany e&ents onitored and contro$$ed bythe icroprocessor are ana$og e&ents!
. hese range fro onitoring a$$ fors of
e&ents e&en speech to contro$$ing otorsand $i8e de&ices!
he 6%C94-9 6i)ital(to(%nalo)Converter
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. fair$y coon and $o(5cost digita$5to5ana$ogcon&erter is the 4C0-70!
> a product of 'ationa$ #eiconductor Corp
. n -5bit con&erter that transfors an -5bitbinary nuber into an ana$og &o$tage!
. Other con&erters are a&ai$ab$e that con&ert
fro 105 125 or 165bit binary nubers intoana$og &o$tages!
. he nuber of &o$tage steps generated by
the con&erter is e=ua$ to the nuber of
binary input cobinations!
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binary input cobinations!
> an -5bit con&erter generates 2,6 &o$tage $e&e$s
> a 105bit con&erter generates 102+ $e&e$s
. he 4C0-70 is a ediu5speed con&erter
that transfors a digita$ input to an ana$ogoutput in appro3iate$y 1!0 )s!
. igure 11>+- sho(s pin5outs of a 4C0-70!
. he de&ice has eight data bus connections
for the app$ication of the digita$ input code
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for the app$ication of the digita$ input code!
. na$og outputs $abe$ed IO"1 IO"2 are
inputs to an e3terna$ operationa$ ap$ifier!
. Because this is an -5bit con&erter its output
step &o$tage is defined as >G%E reference
&o$tage; di&ided by 2,,!
> the step &o$tage is often ca$$ed the reso$ution
of the con&erter
$i)ure 11–
.4 he pin5out of the 4C0-70 digita$5to5ana$og con&erter!
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Internal Structure of the DA0830 . ig 11>+9 sho(s the interna$ structure!
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. his de&ice contains t(o interna$ registers! > the first is a ho$ding register
> the second connects to the %>2% interna$
$adder con&erter
. he t(o $atches a$$o( one byte to be he$d
(hi$e another is con&erted!
. he first $atch is often disab$ed and the
second for entering data into the con&erter!
$i)ure 11–
.5 he interna$ structure of the 4C0-70!
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. Both $atches (ithin the 4C0-70 aretransparent $atches!
> (hen N input is $ogic 1 data pass through
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> (hen N input becoes $ogic 0 data are $atched. he output of the %>2% $adder (ithin the
con&erter appears at IO"1 and IO"2!
. hese outputs are designed to be app$iedto an operationa$ ap$ifier such as a *+1or sii$ar de&ice!
onnectin( the DA0830 to theMicroprocessor"
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. P4 is used to decode the 4C0-70 at I/Oport address 20!
> (hen an O" 20 instruction is e3ecuted
contents of data bus connections 40 >4* are
passed to the con&erter in the 4C0-70
. he *+1 operationa$ ap$ifier a$ong (ith the >
12 G Dener reference &o$tage causes the fu$$5
sca$e output &o$tage to e=ua$ 12 G!
. #ee ig 11>,0!
$i)ure 11–
9 4C0-70 interfaced to the -0-6 icroprocessor at -5bit I/O $ocation20!
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he %6C949A %nalo)(to(6i)italConverter . coon $o(5cost 4C copatib$e (ith a
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coon $o(5cost 4C copatib$e (ith a
(ide range of icroprocessors!
> (hi$e there are faster 4Cs a&ai$ab$e (ith ore
reso$ution this de&ice is idea$ for app$ications
that do not re=uire a high degree of accuracy. 4C0-0@ re=uires up to 100 )s to con&ert an
ana$og input &o$tage into a digita$ output code!
. igure 11>,1 sho(s the pin5out of the 4C0-0+ con&erter!
$i)ure 11–
1 he pin5out of the 4C0-0+ ana$og5to5digita$ con&erter!
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. o operate the con&erter the % pin ispu$sed (ith C# grounded to start thecon&ersion process!
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. #ee ig 11>,2 for a tiing diagra thatsho(s the interaction of the contro$ signa$s!
. If a tie de$ay is used that a$$o(s at $east 100
)s of tie there is no need to test I'% pin!. nother option is to connect the I'% pin to
an interrupt input so (hen the con&ersion iscop$ete an interrupt occurs!
$i)ure 11–
* he tiing diagra for the 4C0-0+ ana$og5to5digita$ con&erter!
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The Analo( Input Si(nal . Before 4C0-0+ can be connected the t(o
ana$og inputs ust be understood:
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ana$og inputs ust be understood:
> GI'; and GI'>;
. hese differentia$ inputs are sued by the
operationa$ ap$ifier to produce a signa$ for
the interna$ ana$og5to5digita$ con&erter!
. hese inputs are connected to an interna$
operationa$ ap$ifier as sho(n in ig 11>,7!
$i)ure 11–- he ana$og inputs to the 4C0-0+ con&erter! a; o sense a 05 to ,!0
G input! b; o sense an input offset fro ground!
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'eneratin( the loc4 Si(nal . 4C0-0+ re=uires a c$oc8 source to operate!
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. It can be an e3terna$ c$oc8 app$ied to C< I'pin or can be generated (ith an %C circuit!
> perissib$e range of c$oc8 fre=uencies is
100 <D 5 1+60 <D!
> desirab$e to use a fre=uency as c$ose as possib$e
to 1+60 <D so con&ersion tie is iniiDed
. If generated (ith an %C circuit C< I' and
C< % pins are connected to an %C circuitas i$$ustrated in igure 11>,+!
$i)ure 11–. Connecting the %C circuit to the C< I' and C< % pins on the
4C0-0+!
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onnectin( the AD080+ to theMicroprocessor
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. 4C0-0+ interfaced to an -0-6 is i$$ustratedin igure 11>,,!
> G%E is not attached to anything (hich is nora$
. #uppose 4C0-0+ is decoded at I/O portaddress +0 for the data and address +2
for I'%!
. he procedure to read data is $isted inE3ap$e 11>29!
$i)ure 11– he 4C0-0+ interfaced to the -0-6 icroprocessor!
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Usin) the %6C949. and the6%C94-9
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. his i$$ustrates an e3ap$e using an 4C0-0+and a 4C0-70 to capture and rep$ay audio
signa$s or speech!
> a speech synthesiDer has been used in the past
to generate speech but =ua$ity (as poor
. or huan =ua$ity speech (e can use an
4C0-0+ to capture an audio signa$ and
store it for $ater p$aybac8 through a 4C0-70!
. ig 11>,6 sho(s circuitry re=uired to connectthe 4C0-0+ at I/O ports 0*00 and 0*02!
. he 4C0-70 is interfaced at I/O port *0+!
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p
> hese ports are in the $o( ban8 of a 165bit
icroprocessor such as the -0-6/-07-6#@
. he soft(are appears in E3ap$e 11>70!
. It reads a 15second burst of speech andp$ays it bac8 10 ties!
$i)ure 11–2 circuit that stores speech and p$ays it bac8 through the spea8er!
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. procedure ca$$ed %E4# reads the speech!
. second P# p$ays it bac8!
. he speech is sap$ed and stored in a
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p p
section of eory ca$$ed O%4#!. he sap$e rate is chosen at 20+- sap$es
per second (hich renders acceptab$e5
sounding speech!
7U''%!B. he -0-65Core2 icroprocessors ha&e t(o
basic types of I/O instructions: I' and O"!
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basic types of I/O instructions: I' and O"!
. he I' instruction inputs data fro an
e3terna$ I/O de&ice into either the -5bit;
or @ 165bit; register!
. he I' instruction is a&ai$ab$e as a fi3ed
port instruction a &ariab$e port instruction
or a string instruction -02-65Pentiu +;
I'#B or I'#!
7U''%!B. he O" instruction outputs data fro
or @ to an e3terna$ I/O de&ice and is
cont(;
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a&ai$ab$e as a fi3ed &ariab$e or string
instruction O"#B or O"#!
. he fi3ed port instruction uses an -5bit I/O
port address (hi$e the &ariab$e and stringI/O instructions use a 165bit port nuber
found in the 4@ register!
7U''%!B. Iso$ated I/O soeties ca$$ed direct I/O
uses a separate ap for the I/O space
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
p p p
freeing the entire eory for use by the
progra!
. Iso$ated I/O uses the I' and O"
instructions to transfer data bet(een theI/O de&ice and the icro5processor!
7U''%!B. Aeory5apped I/O uses a portion of the
eory space for I/O transfers!
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
y p
. In addition any instruction that addresses a
eory $ocation using any addressing
ode can be used to transfer data bet(een
the icroprocessor and the I/O de&iceusing eory5apped I/O!
7U''%!B. $$ input de&ices are buffered so that the
I/O data are connected on$y to the data bus
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
y
during the e3ecution of the I' instruction!
. he buffer is either bui$t into a
prograab$e periphera$ or $ocated
separate$y!
. $$ output de&ices use a $atch to capture
output data during the e3ecution of the
O" instruction!
7U''%!B. andsha8ing or po$$ing is the act of t(o
independent de&ices synchroniDing (ith a
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
p y g
fe( contro$ $ines!
. his counication bet(een the coputer
and the printer is a handsha8e or a po$$!
. Interfaces are re=uired for ost s(itch5
based input de&ices and for ost output
de&ices that are not 5copatib$e!
7U''%!B. he I/O port nuber appears on address
bus connections *50 for a fi3ed port I/O
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
p
instruction and on 1,50 for a &ariab$e
port I/O instruction note that 1,5-
contains Deros for an -5bit port;!
. In both cases address bits abo&e 1, areundefined!
7U''%!B. Because the -0-6/-02-6/-07-6#@
icroprocessors contain a 165bit data bus
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
p
and the I/O addresses reference byte5siDedI/O $ocations I/O space is a$so organiDed in
ban8s as is the eory syste!
. In order to interface an -5bit I/O de&ice tothe 165bit data bus (e often re=uire
separate (rite strobes an upper and a
$o(er; for I/O (rite operations!
7U''%!B. he I/O port decoder is uch $i8e the
eory address decoder e3cept instead
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
y p
of decoding the entire address the I/O portdecoder decodes on$y a 165bit address for
&ariab$e port instructions and often an -5bit
port nuber for fi3ed I/O instructions!. he -2C,, is a prograab$e periphera$
interface PI; that has 2+ I/O pins that are
prograab$e in t(o groups of 12 pinseach group and group B;!
7U''%!B. he -2C,, operates in three odes:
sip$e I/O ode 0; strobed I/O ode 1;
cont(;
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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
p ; ;
and bidirectiona$ I/O ode 2;!
. hen the -2C,, is interfaced to the -0-6
operating at - AD (e insert t(o (ait
states because the speed of is faster thanthe -2C,, can hand$e!
. he C4 disp$ay de&ice re=uires a fair
aount of soft(are but it disp$ays #5CII5coded inforation!
7U''%!B. he -2,+ is a prograab$e inter&a$ tier
(ith three 165bit counters that count in
cont(;
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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions
%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition
Barry B! Brey
binary or binary5coded decia$ BC4;!
. Each counter is independent and operates
in si3 different odes: 1; e&ents counter
2; retriggerab$e onostab$e u$ti&ibrator7; pu$se generator +; s=uare5(a&e
generator ,; soft(are5triggered pu$se
generator and 6; hard(are5triggered pu$segenerator!
7U''%!B. he 16,,0 is a prograab$e
counications interface capab$e of
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recei&ing and transitting asynchronousseria$ data!
. he 4C0-70 is an -5bit digita$5to5ana$og
con&erter that con&erts a digita$ signa$ to anana$og &o$tage (ithin 1!0 )s!
. he 4C0-0+ is an -5bit ana$og5to5digita$