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Changing face of VLSI Design
Domains are constantl c!an"in" Computer Revolution
Communication Revolution
Medical Revolution
#ame a compan t!at $as once kno$n as a computer maker %ut is kno$n in
t!e communication space toda.
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Integration
'ttempt to inte"rate multiple (unctionalities ) t!e *uest (or t!e
S$iss arm kni(e +ill it %e t!e computer
+ill it %e t!e cell p!one
+ill it %e somet!in" else
-o$ !as t!e *uest (or t!is kind o( inte"ration impacted VLSI Desi"n
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Consuer !ar"ets
Reac!in" out to a lar"er markets
Consumer devices /Tos, Cameras, 0ad"ets1
Consumers (rom di((erent countries
+!at do t!ese mean (rom a VLSI Desi"n vie$ point
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Consuers epect connecti$it%
Consumers $ant t!eir "ad"ets to communicate $it!
one anot!er
+ired communication
+ireless communication
-+34 5 6or t!e communication protocols s!o$n, make a ta%le t!at s!o$s t!e
tpe o( communication /serial7parallel, $ireless7$ired, s!ort ran"e7mediumran"e1 and 2 tpical applications
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Consuers epect graphical user
interfaces and ultiedia
Di"ital Si"nal7Ima"e Processin"
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Chip Design & Soe !etrics
+!at are some *ualit metrics (or a desi"n
Do all t!e metrics !ave t!e same $ei"!t +!ic! one do ou t!ink matters
most +!at are some tradeo((s ou can (oresee
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Tie to !ar"et and Design Cost
;suall, Test Time
?etter desi"n (lo$s and tools are needed to reduce
desi"n time
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IP 'euse based Design Flow - (enefits
Desi"n Reuse can !elp reduce desi"n time
Vendors provide IP suc! as processors, memories,
connectivit %locks
IP Reuse can !elp reduce desi"n cost
Team siAes and team skills
IP Reuse allo$s us to separate IP Creation (rom IP
Inte"ration
Consider t!e options o( /a1 -avin" an in5!ouse analo" team (or desi"nin" IP
suc! as 'DC7D'C versus purc!asin" suc! IP and inte"ratin". +!at are t!e
relative %ene(its7issues
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4B
Design Producti$it% )ap
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Chip Design Flows
Custom Desi"n 6lo$
RTL to 0DSII Desi"n 6lo$ /aka 'SIC Desi"n 6lo$1
IP5%ased Desi"n 6lo$
Plat(orm5%ased Desi"n 6lo$
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'TL-to-)DSII Design Flow & at 1*+***ft
RTL creation and veri(ication
?lock5level snt!esis, timin" analsis and 'TP0
6loorplannin"
Top5level RTL snt!esis, timin" analsis and 'TP0 P!sical Desi"n
Parasitic xtraction
Top5level timin" analsis and 'TP0
-ando((
?4 ?2
top.v/!d1
?4.v/!d1
?2.v/!d1
top."dsii
sc.li%
macros
constraints
reports
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IP integration challenges
Veri(ication in t!e context o( t!e SoC
Per(ormance
Standards Compliance
6unctionalit
;nconnected pins, ;nkno$n values, etc.
T!ree students /', ?, C1 (orm a team (or $ritin" a report. ? and C $rite sections.
' inte"rates t!em. +!at pro%lems mi"!t come up durin" inte"ration
Pa"e count exceeds limit, 6ile provided % C not compati%le, 6ile provided % ?
ma !ave a virus, Repetitions, Re(erencin" pro%lems, etc.
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,aple
Eou are desi"nin" a &25%it t$oFs complement
multiplier and $is! to use an adder as an IP
Eou onl !ave a 485%it adder availa%le
IP assumes t!at inputs are comin" MS?5(irst,$!ereas anot!er IP provides t!e outputs LS?5(irst
IP assumes ?i"5ndian stora"e o( dataG anot!er IP
stores data in Little5ndian (ormat
Volta"e levels o( t$o IP ma %e di((erent
Inter(ace $rappers are used to overcome t!ese pro%lems.
+rappers $ill result in over!eads.
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,ight eleents for udging the .ualit%
of Silicon /ardware0Software IP
CourtesH Snopss /2BB81
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/ard IP and Soft IP
-ard IP Tec!nolo" Dependent
Predicta%le ) alread
proved in silicon
More protected a"ainst
ille"al usa"e
Limitation ) cannot %e
customiAed
So(t IP Tec!nolo" Independent
Risk
Can %e modi(ied to suit t!e
needs o( t!e SoC
'pplication5speci(ic -ard IP ) tries to com%ine t!e %est o( %ot! $orlds.
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/ardware0Software Codesign
T$o important steps in IP inte"ration
Provide a !ard$are inter(ace Pin7Si"nal mappin", Protocol translation, ?u((erin"
So(t$are Driver 'ccess to IP (unctionalit t!rou"! t!e S
Implement some (unctions in !ard$are and ot!ers in
so(t$are (or area7per(ormance7po$er tradeo((
xample o( T'0H DCT in !ard$are, ot!er (unctions in
so(t$are
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2B
IP Standards
CP5IP is a $ell5kno$n standard to miti"ate t!e
pro%lem o( inter(acin" IP (rom multiple vendors
Man IP are CP5compliant
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Ideal ,SL Design FlowIdeal ,SL Design Flow
22K 2BB: Sudeep Pasric!a #ikil Dutt
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Platfor (ased Design
Most Sstem5on5C!ip need ne or more processors
Di"ital Si"nal Processors
-ard$are 'ccelerators
Perip!eral IP /touc! screen, etc1
Connectivit IP
m%edded Memories
'nalo"7Mixed5Si"nal IP
Custom Desi"nin" t!e SoC (or eac! application !asadvanta"es, %ut in(easi%le +!at are t!e limitations o( t!e top5do$n approac!
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/ow do %ou answer these .uestions3
Is multimedia per(ormance needed
+!at is t!e tar"et operatin" sstem
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Features of 4CP-IP
;ni*ue 6eatures o( CP IP penl licensed
Simple to Complex protocols needed in smart p!ones
Supported % man international industrial %odies
?us5independent
Scala%le
IP5O'CT (ormat 5 OML %ased lanua"e de(ined % t!e
SPIRIT consortium Snc!ronous and unidirectional si"nalin"
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&B
4!6P 787* used 4CP for the first tie
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&4
Cache Coherence
CPU
Cache
CPU
Cache
CPU
Cache
Shared Bus
SharedMemory
X: 24
CPU1: T = read X; // T has the value 24 and X s cachedCPU2: ! = read X; // ! has the value 24 and X s cachedCPU2: X = "2; // !ocal co#y o$ X s u#dated%CPU": M = read X;
&otce that havn' (rte)throu'h caches s not 'ood enou'h
1 2 3
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Snoop% Cache
ac! CP; cac!e snoopsF (or $rite activit on data
addresses $!ic! it !as cac!ed
#eeds a %us structure $!ic! is "lo%alF
'll communication can %e seen % all
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&&
5rite-In$alidate Protocol for Snoop%
Cache
CP; t!at $is!es to $rite to an address, "ets a %us ccle and sends
a ‘write invalidate’ messa"e
'll snoopin" cac!es invalidate t!eir cop o( appropriate cac!e %lock
CP; $rites to its cac!ed cop
'lso updates t!e s!ared memor i( +rite T!rou"!F protocol is (ollo$ed I( $e use +rite ?ackF sc!eme, t!in"s are more complex
'n s!ared read in ot!er CP;s $ill no$ miss in cac!e and re5(etc!
ne$ data
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5rite-9pdate Protocol for
ipleenting Snoop% Cache
CP; $antin" to $rite "ets a %us ccle and
%roadcasts ne$ data as it updates its o$n cop
'll snoopin" cac!es update t!eir cop
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!,SI Protocol
' practical multiprocessor invalidate protocol t!at attempts to
minimiAe %us usa"e
'llo$s usa"e o( a $rite %ackF sc!eme 5 i.e. main memor not
updated until dirtF cac!e line is displaced
;ses an extension o( usual cac!e ta"s invalid %lockF ta"
dirt %lockF ta"
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&8
8 states of a cache bloc" :!,SI
Protocol;
2 %its to represent states
In$alid ) ?lock is not valid /as in simple cac!e1
,clusi$e 5 cac!e %lock is t!e same as main memor and is t!e
onl cac!ed cop
Shared ) cac!e %lock is same as main memor %ut copies maexist in ot!er cac!es
!odified 5 cac!e %lock !as %een modi(ied, is di((erent (rom main
memor 5 is t!e onl cac!ed cop
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&9
Illustrating the states of cache bloc"s
P1 P2 P"
P1 P2 P"
P1 P2 P"
P1 P2 P"(
r
r
r
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Local 'ead /it
?lock must %e in one o( states 5 MS
I( in M state, it must !ave %een modi(ied locall
Simpl return value
#o state c!an"e
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Local 'ead !iss
Case 4 5 #o ot!er cop in cac!es
Processor makes %us re*uest to
memor
Value read to local cac!e, marked
Case 2 5 ne cac!e !as cop
Processor makes %us re*uest to
memor
Snoopin" cac!e puts cop value on t!e
%us
Memor access is a%andoned
Local processor cac!es value
?ot! lines set to S
Case & 5 Several cac!es !ave S cop
Processor makes %us re*uest to memor ne cac!e puts cop value on t!e %us
/ar%itrated1 Memor access is a%andoned Local processor cac!es value Local cop set to S
t!er copies remain S ne cac!e !as M cop
Processor makes %us re*uest to memor Snoopin" cac!e puts cop value on t!e %us Memor access is a%andoned Local processor cac!es value Local cop ta""ed S Source :!; $alue copied bac" to eor%
Source ta" M 5Q S
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Local 5rite /it
Line must %e one o( MS
Case M line is exclusive and alread
dirtF
;pdate local cac!e value no state c!an"e
Case ;pdate local cac!e value
State 5Q M
Case S Processor %roadcasts an
invalidate on %us
Snoopin" processors $it! S
cop c!an"e S5QI Local cac!e value is updated
Local state c!an"e S5QM
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Local 5rite !iss :1;
Case 4 5 #o ot!er copies Value read (rom memor to
local cac!e /1
Value updated
Local cop state set to M
Case 2 ) /ne or multiple S1 Value read (rom memor to
local cac!e 5 %us transaction
marked R+ITM /read $it!
intent to modi(1
Snoopin" processors see t!is
and set t!eir cop state to I
Local cop updated state set
to M
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Local Cache !iss :7;
'not!er cop in state M
4. Processor issues %ustransaction marked R+ITM
2. Snoopin" processor sees t!is
?locks R+ITM re*uest Takes control o( %us +rites %ack its cop to
memor Sets its cop state to I
&. ri"inal local processor re5
issues R+ITM re*uest
. Is no$ simple no5cop case Value read (rom memor to
local cac!e Local cop value updated
Local cop state set to M
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State Diagra for locall% initiated
access
*nvald
Mod+ed ,-clusve
Shared.eadt
.eadt
.eadt
.eadMss0sh
.ead
Mss0e-
rte
t
rtet
rtetrte
Mss
.*TM
*nvaldate
Mem .ead
Mem .ead
= 3us transacton
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State Diagra & 'eotel% initiated
access
*nvald
Mod+ed ,-clusve
Shared
Mem .ead
Mem .ead
Mem .ead
*nvaldate
.*TM.*TM
= co#y 3ac
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Director%-based protocols
#o need (or a s!ared %us /can use point5to5point connections1 T!ere(ore, more scalea%le /4BB> processors1
'llo$ eac! processor can !ave its o$n private memor
ac! node maintains a director storin" cac!e in(ormation
and memor in(ormation ' processor communicates $it! t!e director to access
memor
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Counicating with the director%
I( a processor re*uests a non5local memor pa"e, t!e director uses
its in(ormation to (ind t!e pa"e
T!en, it uses messa"es to retrieve t!e pa"e and insure all ot!er
processors !ave consistent in(o.
Since t!e director maintains $!ic! processors are cac!in" t!epa"e, it onl needs to send messa"es to t!ose processors
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Point-to-Point Counication
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'eading
!ttpH77tinurl.com7@8!e8
S. Pasric!ca and #. Dutt,S. Pasric!ca and #. Dutt, On-Chip CommunicationOn-Chip Communication
Architectures Architectures, Mor"an Jau((man, 2BB:.
http://tinyurl.com/y965he6http://tinyurl.com/y965he6