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ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

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ITEC 352 Lecture 24 Memory
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Page 1: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

ITEC 352

Lecture 24Memory

Page 2: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Review

• Questions?• Reminder: HW due on Wed. Night• Intel 8080 CPU

Page 3: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Outline

• Memory– How it works

Page 4: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

• When the copy of your floppy'sgetting sloppy on the disk,

and the microcode instructionscause unnecessary RISC,

then you have to flash your memoryand you'll want to RAM your ROM.

quickly turn off your computer

and be sure to tell your mom! • …• “

• - Gene Ziegler (Cornell University)

Fun quote

Page 5: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

The Memory Hierarchy: What is faster?

Page 6: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

RAM

• What we in layman terms usually call as “main memory”

• It is a collection of registers. Hence, basic building block is a flip flop.

• What is random about RAM?

• “Any memory location in the RAM can be accessed in the same amount of time”

Page 7: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Behavior

Activate the chip.

Select can be wired

to a clock and/or other inputs (e.g.,

enable)

This is a bi-

directional line to

both read and write

Page 8: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

SRAM / DRAM

• SRAM (Static RAM): Based on flip flops. They are considered static because the contents of each flip flop persist as long as power is applied to the chips.

• DRAM (Dynamic RAM): employ a capacitor which stores a minute amount of electric charge (representing 1 or 0). – Capacitors tend to be smaller than flip flops so DRAMs can be used to develop lot of

memory in smaller sizes than SRAMs.– DRAMs must be refreshed often to maintain charge. – Can you recognize any of the following names:– SDRAM, DDR – RAM, DDR2 RAM? Where do they fit in: SRAM or DRAM

© Wikipedia

Page 9: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

RAM Diagram

Address lines.There are “m” bits in the address, hence we can address: 2m

words.HOW MANY BITS can we store in this RAM chip. Assume, word =

w bits

When WR = 0, write into the chip. Else read

from the chip.

CS:Chip SelectWhen CS = 0, activate (or select the chip).

Data lines (connected to data bus). The line can

read/write one word (hence w bits) at a time. Notice: it is

bi-directional

Page 10: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Deeper

• A RAM chip is simply a collection of registers. Which are simply a collection of D flip flops.

RAM chip: collection

of registers

Registers:

Collection of flip flops

D flip flops.

If there are n flip flops, then each register is an n bit register.

Page 11: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Deeper(2)

• Goal: Develop a RAM that can store 4 four bit words.

• How many registers must the RAM have?• How many bits per register?• How many bits should we have in the Address line? • How many bits should we have for the data line?

Page 12: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Deeper(2)

• How many registers must the RAM have?• Answer: 4 registers to store 4 words.• How many bits per register?• Answer: 4 bits, because each word is 4 bits. (Also, this

means we need 4 flip flops)• How many bits should we have in the Address line? • Answer: 2 bits. Because we need to be able to select one of

the 4 registers.• How many bits should we have for the data line? • Answer: 4 bits. The data is going to be a word

Page 13: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Deeper look into RAM (3)

• Architectural details:• RAM requires 4 registers. Let’s represent them by

boxes.

• What about, the addressing the registers: we need a decoder to determine which register to pick.

Page 14: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

A Four-Word Memory with Four Bits per

Word in a 2D

Organization

Page 15: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Simplified Graphic

Page 16: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Decoder usage

Consider the decoder we just used. Its circuit diagram looks like this:

(1) How many AND gates are we using here?

(2) How many inputs do we have for each AND gate?

How many AND gates would we need for a Decoder in a 64 Mb RAM?

Page 17: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

So far, so good. But can we really use a decoder?

Consider the decoder we just used. Its circuit diagram looks like this:

(1) How many AND gates are we using here?

(2) How many inputs do we have for each AND gate?

How many AND gates would we need for a Decoder in a 64 Mb RAM?

64M = 226 so you would need 26-input AND gates!

Page 18: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Decoder distancing

• Suppose we need to store 32 words. How many AND gates will be need in the decoder? How many inputs to each AND gate?

• What is the size of the memory?

• This gets expensive – since RAM may reach sizes of 4 GB or more !!!

Page 19: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

2-1/2D Organization of a 64-Word by One-Bit RAM

Page 20: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Example memory module

– • Adapted from(Texas Instruments, MOS Memory: Commercial and Military Specifications Data Book, Texas Instruments, Literature Response Center, P.O. Box 172228, Denver, Colorado, 1991.)

Notice: here the same bits can be used for both address and data in and data out.

Page 21: ITEC 352 Lecture 24 Memory. Review Questions? Reminder: HW due on Wed. Night Intel 8080 CPU.

Memory

Other Elements

• We will look briefly at one more memory element: ROM (Read only memory)

• For the other memory: cache, and virtual memory – we will look at the main concepts but not at the hardware details.


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