CHAPTER 2
ITERATIVE INTERFERENCE CANCELLATION RECEIVERS
Single user detectors are not optimal for CDMA because they process other
user interference as unstructured channel noise. Better CDMA receivers can be
designed if the specific structure of multiple access interference (MAI) is fully
exploited. To realize this, novel receiver structures have been proposed over the years
that take advantage of the knowledge of MA1 signal parameters [144-1481. Such
receivers termed as multi-user receivers are more complex than conventional ones
because of their capability of using MA1 signal information to help recover the
desired user. A general multi-user detector depicted in Figure 2.1, is composed of an
initial correlation stage followed by a set of additional stages where a multi-user
detection algorithm is implemented. It is shown by Verdu that the set of correlator
outputs for each user forms a set of sufficient statistics which, if processed properly,
can lead to an optimal multi-user detection. The most commonly analyzed multi-user
detectors are presented in this section.
2.1.1 Optimal Detector
The optimal structure shown in Figure 2.2 consists of a bank of matched filters
providing first order user amplitude estimates to a Viterbi decision algorithm. Verdu
[I491 has shown that the optimal structure afforded significant performance
improvement over the conventional structures and is insensitive to the near-far
problem. The extraordinary performance enhancements however come at a price. The
optimal receiver assumes apriori knowledge of the received signal amplitudes as well
as delays; in practice, such ideals are usually not attainable. In addition to that the use
of Viterbi decision algorithm makes the receiver complex and more burdensome.
Fig. 2.1 General multi user receiver structure
f 3 Zl
Fig33 BPSK based optlmrl CDMA reeeiver
+
-+ I I I
I
: I I I
---*
/
L 1
Further processing/ Multiuser detection algorithm
' Correlator ' 21
\ J
First stage Processing/ Correlation
I I I
; ; ;
!
----+ f \
b
2 2
+ I I I I I I I I I I I I
zk b
user 1 - b,
r(t) - Viterbi Decision Algorithm
\ J
I, - b2 ; I I I I I I I I - 4
i J
' orr relator ' ' 2
+ L 1
I I I I I I I
z, + -----b UserK
user2 b '
The Viterbi decision algorithm performs maximal likelihood sequence
estimation over the entire sequence of received message bits, thereby decoding the
whole message sequence in a trellis with 2' states. The computational complexity per
bit decision then becomes exponential in the number of users, clearly rendering the
optimal receiver impractical for implementation. Due to its prohibitively expensive
complexity, the role of the optimal receiver has bem relegated to that of a benchmark
against which sub-optimal CDMA detectors exhibiting more reasonable
computational complexity are compared. Some important sub-optimal multi-user
receivers are discwed here.
2.1.2 Decorrelator
The Decorrelator [150-1521 is a linear multi-- detector with K' as upper
bound on complexity. It functions by applying a linear transformation to the set of
matched-filter outputs obtained from the first stage. As its name implies, the receiver
seeks to undo the various inter-user correlations so as to isolate users from one
another. This decorrelation attempt is canied out by computing PN code waveform
cross correlation values and storing these in a k x k matrix, and multiplying the
inverse of this matrix by the vector of matched-filter outputs from the first stage. The
decorrelator does not require knowledge of signal amplitudes and is completely
insensitive to the near-far effect. Its k2 complexity stems from the k x k matrix storage
requirement; and while not exponential, such complexity is formidable nonetheless.
This matrix is time varying as users come on and drop off of the system, thereby
making updates on such a large matrix expensive. Further, this correlation matrix
needs to be inverted, bringing about the issue of singularity. The decorrelator relies
upon accurate PN code correlation values, and if the inverse correlation matrix
becomes unstable or undefined even, then the detector ceases to function adequately.
Of concern as well is a noise enhancement produced by the decorrelation operation,
rendering decision statistics noisier.
In general, the decorrelator provides substantial performance and capacity
gains over the conventional receiver, however, it has many drawbacks and hence it is
not widely used.
2.1.3 Mldmum Mean Square Error Detector
The MMSE detector [ I S ] , like the decornlator, operates by applying a linear
transformation to the set of first stage matched-filter outputs. It seeks to minimize the
averaged square error between actual data and the sot? outputs from the first stage. In
this case, linear transformation TR=R" used in de-cornlator is replaced by
( T R = R + N ~ ~ ~ Y ' . The performance of MMSE approaches that of de-cornlator as the
noise level drops to zero i.e. No+O, but as No increases, the performance deteriorates
to that of conventional receiver. At low Ed No MMSE receiver outperfoms the de-
correlator while at high E d , , the de-correlator's performance approaches to that of a
MMSE receiver. MMSE receiver rectifies the decorrelator's shortcoming of
enhancing noise, but at the cost of requiring knowledge of signal amplitudes. Even
though near far resistance of MMSE is slightly better than that of decorrelator, both
MMSE and decorrelator has the same computational complexity due to the necessity
of computing the inverse of a matrix. Owing to the complexity of these suboptimal
detectors researchers concentrated on the less complex linear interference cancellation
receivers.
2.2 INTERFERENCE CANCELLATION RECEIVERS
Interference cancellation has received a great deal of attention in the literature
and the premier objective of this thesis is to design a Hybrid Interference Cancellation
scheme. Interference cancellation detectors seek to remove interference by actually
subtracting estimates of interfering signals from the received signal. A general
interference cancellation receiver is depicted in Figure 2.3. It comprises of an initial
stage of matched-filters, like the other multi-user receivers, followed by stages of
interference cancellation. Interference cancellation receivers typically come in two
forms: parallel and successive. In parallel interference cancellation, all interfering
users are cancelled (subtracted) concurrently (in parallel) from the received signal. In
the successive approach proposed by Patel and Holtzman [lo], users are cancelled
serially in the descending order of estimated received power, from strongest to
weakest. These two interference cancellation receivers are completely analyzed in the
next section based on which the hybrid interference cancellation receiver is designed.
Fig.2.3 BPSK based interference cancellation CDMA receiver
2.2.1 Successive Interference Cancellation Receiver
The successive interference cancellation scheme uses the algorithm shown in
Figure 2.4. During every iteration of the scheme, all the user's signals are estimated.
The signal with the largest power is then regenerated and subtracted from the buffered
received signal. The remaining signals are now re-estimated and a new largest user is
selected. The process is continued until all the users' signals have been recovered or
the maximum allowable number of cancellations is reached. Successive interference
cancellation is robust to imperfect power control in a CDMA system. This is because
of the fact that the interference offered by the best estimated signals are eliminated
h m the received waveform.
Figure 2.5 is the block diagram of successive interference cancellation
r='eceiver for the DS SS system. Estimating the power of the user is fairly
straightforward in a coherent DS BPSK system, since the receiver is equipped with
Bank of Complex Cornlaton
Regenerate Cancellation Decoded Signal
Fig.2.5 Block diagram of successive interference cancellation receiver
The reasons for canceling the signals in descending order of signal strength are
obvious. First, it is easier to acquire and perform demodulation on the strongest users
i.e. the probability of making a correct decision is high. Second, the removal of
strongest users offers the maximum benefit for the remaining users. Even though, the
strongest user will not benefit from any MA1 reduction; the weakest user however
will potentially see a huge reduction in their MAI. The SIC detector requires only a
minimal amount of additional hardware and has the potential to provide significant
improvement over the conventional detector. It does, however, pose a couple of
implementation difficulties. First, one additional bit delay is required per stage of
cancellation. Thus, a tradeoff must be made between the number of users that are
cancelled and the amount of delay that can be tolerated. Second, there is a need to
tr order the signals whenever the power profile changes. Again, a tradeoff must be
made between the precision of the power ordering and the acceptable processing
complexity.
A potential problem with the SIC receiver occurs if the initial data estimates
are not perfect. In this case, even if the timing, amplitude and phase estimates are
perfect, if the bit estimate is m n g , the interfering effect of the bit on the Signal to
noise ratio is quadrupled in power (The amplitude doubles, so the powa quadruples).
Thus, a certain minimum performance level of the conventional detector is required
for the SIC detector to yield improvements; it is crucial that the data estimates of at
least the strongest users that are cancelled fust be reliable. However, the SIC receiver
almost provides an optimal performance and is quite reliable. The only problem with
the SIC receiver is that the number of iterations to cancel out all the MA1 is directly
proportional to the number of wrs. Hence the computation time is quite large.
2.2.2 Parallel Interference Cancellation Receiver
In contrast to the SIC receiver, the Parallel interference cancellation (PIC)
receiver [156,157] estimates and subtracts out all of the MA1 for each user in parallel.
Fig. 2.6 Block dtgnm of paunllel interference cancellation receiver
25
The basic block diagram of a single stage PIC receiver is shown in Figure 2.6.
The first block is that of a matched filter bank, which is used to anive at the initial bit
estimates for each user. These bits are then rescaled by the amplitude estimates and
re-spread by the individual PN codes to produce an estimate of the received signals of
those users. The summer sums up all the estimated signals of various users and these
are in turn subtracted kom the total received signal. Hence a partially error fnc signal
with less effect of MA1 is obtained.
The advantage of the PIC receiver is that the process of cancellation is quite
fast and there is no delay incorporated at the receiver. But the problem with this type
of receiver is that the receiver complexity is quite large. Also the performance of the
receiver is not reliable for there is a possibility of improper cancellation. The PIC
receiver is faster than the SIC receiver, but at the same time, is more complex than the
SIC receiver. Hence in order to obtain an optimal receiver performance, a trade-off
between the computational time and receiver complexity is necessary [158]. This
trade-off is incorporated in the proposed SINR driven Hybrid Interference
Cancellation (HIC) receiver, presented in the next section.
2.2.3 Hybrid Interference Cancellation Receiver
SIC yields better performance with lot of processing time and PIC is superior
to SIC in terms of time delay but is inferior in terms of BER. Hence a mix of SIC and
PIC will yield an optimal result. The main idea behind hybrid IC is that instead of
canceling all k users either in series or in parallel, they are cancelled partially in
parallel and partially in series. The configuration for cancellation will be k-PC-S,,
where k is the total number of users and the number cancelled in parallel and in series
at each stage is denoted by PC and S,, respectively. The block diagram and flow chart
of HIC are shown in Figures 2.7 and 2.8 respectively.
The signals of the first PC stronger users (out of k) are chosen to perform PIC
between them. As a result of this action, the PC most reliable users are chosen, their
signals reconstructed and subtracted from the buffered version of the received signal.
Remaining k-PC (i.e. S,) users are arranged according to their strength and one by one,
Usen are detected and subtracted.
Fig. 2.7 Block diagram of hybrid interference cancellation receiver
Incoming - Desired
Compute decision statistic (d) for all
existing users
signal
+ 1 A T Cancel user
Fig.2.8 Flow diagram of hybrid interference cancellation receiver
Parallel interference cancellation stage
Successive interference cancellation stage
user's signal
Obviously, HIC p a f m s in an optimal way when compared with SIC and
PIC. Many researchers have worked on optimizing the value of P and S, but in this
work choosing of P and S is done in an optimistic way. Target BER is decided
depending on the type of senice offered. Based on the modulation scheme, SINR that
yields the target BER is chosen as the threshold. It enables to decide whether the usa
should be detected in PIC mode or SIC mode. i.e, those users having SINR greater
than the threshold can be detected using PIC since it will yield required performance
through PIC itself and the remaining users are detected through SIC means.
2.3 ITERATIVE INTERFERENCE CANCELLATION RECEIVERS
As direct implementation of a sliding window multi-user detector is
computationally complex for the given multipath CDMA channel, a low-complex
multi user detector is developed based on a novel nonlinear interference suppression
technique. This makes use of both soft interference cancellation and instantaneous
linear minimum mean-square error filtering. The properties of such a nonlinear
interference suppressor are examined, and an efficient recursive implementation is
derived. Simulation results demonstrate that the proposed low complexity iterative
receiver structure for interference suppression and decoding offers a superior
performance over the traditional non-iterative receiver structure. Moreover, at high
signal-to-noise ratio, the detrimental effects of MA1 and IS1 in the channel can almost
be overcome by iterative processing, and single-user performance can be approached.
-2.9 Block diagram of a three stage IC scheme
28
A method to improve the performance for a higher n u m k of users or higher
values of C~OSS- orr relation is to perfom a decorrelation prior to the first iteration. An
iterative cancellation consists of an Interference Cancellation (IC) based h4UD
followed by k single user decoders. Each constituent block itmtively provides soft
information to the others. Figure 2.9 shows a typical multistage interference
cancellation receiver.
2.3.1 Itentive Parallel Interference Cancellation Receiver
In this section, an iterative parallel interference cancellation receiver structure
is proposed (Figure 2.10) for decoding multi-user information data in a multipath MC
CDMA system. The receiver performs three successive soft output decisions through
an iterative process. In every iteration, extrinsic information is extracted from
detection and decoding stages and is then used as apriori information in the next
iteration, just as in turbo decoding.
-... ".".-..-." "." .... . .... "" ................... " .......
.--
FIg.2.10 Block d i m of a three stage PIC scheme
In the first multi-user detection iteration, the upriori information of data bits is
not available [159]. The IC stage delivers interference cancelled soft outputs to the
input of the decoders. After a fixed number of decoder iterations, the extrinsic
information of coded bits at the output of decoders is fed back to the input of the IC
detector as the apriori information for the next receiver iteration. In every new
iteration, the aprion information in the multiuser receiver becomes more reliable and
hence a greater amount of interference can be cancelled. The significant part of
interference cancellation is in the first iteration. It is in this perspective that many IC
based iterative receivers with a first linear stage have been proposed. Nevertheless, a
linear multiuser detector has the drawback of an extremely high computational
complexity. In this work an iterative PIC receiver where most interference
cancellation is done in the first receiver iterations is proposed i.e a convmtional
iterative receiver tries to cancel the MA1 from all the users only once at the end of
each decoding iteration. Computational complexity needed by the iterative PIC to
perform interference cancellation in every iteration is greater than the conventional
PIC. However it will be shown by simulation that the proposed iterative receiver
performance is better than the conventional one even with equal complexity.
2.3.2 Proposed Iterative Hybrid Interference Cancellation Receiver
In iterative hybrid interference cancellation the PIC part of HIC is made
iterative. Improvements in HIC can be realized by using more stages of the
cancellation unit. For practical implementations a three stage iteration is found to be
optimal. More stages of PIC would require more computational time and increased
complexity. Reasonable improvements in HIC can be achieved with three stages of
PIC in the HIC receiver. The iterative three-stage HIC receiver is shown in
Figure 2.11. The initial stages are that of PIC receivers. Users within a certain
threshold are cancelled in parallel fint. The same user's signal are further estimated
and cancelled three times to obtain a near m r free signal for the SIC stage. It can be
seen that near optimal performances are obtained with three stages of the cancellation
unit. It is not advantageous to make SIC iterative because it will consume a lot of time
and the system will become extremely slow. All these performance improvements are
achieved at the cost of computational complexity, increased hardware and time.
However if performance is the criterion all these will have to be sacrificed.
Fig 2.11 Block diagram of a three stage HIC scheme
2.4 SIMULATION RESULTS
A DS CDMA and MC CDMA transmitter (involving generation of data,
spreading sequence and subcarriers) has been simulated using MATLAB, with QPSK
modulation and 16 bit Walsh code spreaded data. A Rayleigh fading channel (with
parameters so as to match practical environment) is modelled in AWGN floor.
Subsequently various types of receivers are simulated as per the blocWflow diagram
given in Figures 2.5,2.6,2.8,2.10 and 2.1 1.
2.4.1 Performance of SIC, PIC and HIC for DS CDMA System
The error performance of the HIC receiver has been obtained for DS CDMA
system. For comparison the SIC and PIC receivers have also been simulated and their
enor performances obtained. To keep the simulation time practical, a processing gain of
16 has been chosen. The simulation has been carried out by assuming that there are 15
users operating simultaneously and each user transmits 10000 bits. The error
~erformance thus obtained for SIC, PIC and HIC is shown in Figure 2.12.
Fig.2.12 Performance of SIC, PIC and HIC for DS CDMA system
2.4.2 Performance of SIC, PIC and HIC for MC CDMA System
Figures 2.13 and 2.14 show the plot between signal to noise ratio and bit error
rate for a 16 bit Walsh code spreaded 5000 and 1OOO bits data of 15 users,
respectively. It is observed that the conventional receiver has the highest error rate
due to uncontrolled multiple access interference. The PIC receiver performs better
when compared to the conventional receiver, but has high error rates due to imperfect
cancellation particularly as the number of user increases. Even though the
computation time is large, the SIC technique provides the best possible error
performance. The HIC receiver, as seen from the plot, nearly matches the
~elformance of the SIC receiver with less computational time and it serves as a
compromise between these two techniques. Figures 2.15 and 2.16 depict the plot
between number of users and BER at 3 dB and 6 dB level respectively. It can be noted
that as the number of users increase, the error rate also increases. The performance of
the conventional receiver and the PIC receiver are poor when compared with the
performance of HIC, which nearly approaches to that of SIC.
2.43 Performance of Iterative PIC and HIC for MC CDMA System
Figure 2.17 highlights the performance of a three stage PIC receiver with IOOO
bits of data, 16 bit Walsh code spreading and 15 active users. It is seen that near
optimal performance (close to SIC) is achieved with a three stage of the PIC receiver.
However its realization is difficult because of the increased hardware complexity.
Hence an iterative HIC (with reduced hardware complexity as compared to iterative
PIC) is realized which yields a significant improvement in error performance, indeed
with reduced hardware complexity. Figure 2.18 shows the improvement in error
performance of iterative HIC receiver and Figure 2.19 depicts the comparison of error
performance of various interference cancellation receivers.
Fig.2.13 BER of SIC, PIC and HIC for MC CDMA system (5000 bits)
Fig.2.14 BER of SIC, PIC and HIC for MC CDMA system (1000 bits)
Fig.2.15 BER variations with no. of users (1000 bits at 3 dB Level)
Fig.2.16 BER variations with no. of users (1000 bits at 6 dB level)
Fig.2.17 BER of iterative PIC receiver
35
Fig.2.18 BER of iterative HIC receiver
Fig.2.19 Performance comparison of IC receivers
36
2.4.4 Complexity Analysis
Figure 2.20 brings out the computational complexity of the SIC receiver and
the HIC receiver. The number of correlations required in SIC increases exponentially
as the number of users increase. In case of HIC, the number of correlations required is
much less compared to SIC. The number of iterations for SIC is k fork users whereas
the number of iterations for hybrid system will vary and depend on channel
conditions. The number of signal cancellations is k-1 for SIC while it is reduced to
k-X in a HIC scheme, where X-l are the number of users cancelled in a SIC scheme
and in one iteration the remaining users are cancelled. This accounts for the greatest
reduction in computational complexity in a HIC scheme and the computational
complexity works out to k2/2 for the successive scheme while it is reduced to the
extent of (k-~)' /2 in case of HIC where X is almost W2 in most cases. Figure 2.21
shows the hardware complexity of SIC, PIC and HIC receiver.
b . d m
Fig.2.20 Comparison of computational complexity
Fig.2.21 Hardware complexity of HIC, PIC and SIC scheme
2.5 CONCLUSION
In this chapter, a DS CDMA and MC CDMA systems have been simulated.
Hybrid interference cancellation receiver has been designed and the performance of
the receiver obtained using simulations. The performance of the proposed receiver has
been compared with the other interference cancellation receivers. From the results
obtained, it is concluded that, the performance of the hybrid interference cancellation
receiver matches the successive interference cancellation scheme with much lesser
number of correlations and hence with less computational time. But the hardware
complexity of the HIC receiver is greater than that of the SIC receiver and lesser than
that of the PIC receiver. Hence a perfect trade off between the computation time and
receiver hardware complexity is achieved. Lmprovements in the performance of
hybrid scheme have been obtained based on iterative schemes. This scheme has
resulted in considerable improvements of the HIC receiver. Through simulation it is
identified that capacity of the MC CDMA system improves by around 20% due to the
Proposed interference cancellation receivers.