1

ECE 255

MOS Differential Pair with Active Loads

Mark Lundstrom School of ECE

Purdue University West Lafayette, IN USA

ECE 255: Fall 2019 Purdue University

Lundstrom: Fall 2019

2

Outline

1)  Quick Review 2)  MOS differential pair with active loads 3)  Simple analysis 4)  Rigorous small signal analysis 5)  Summary

Lundstrom: Fall 2019

3

MOS Op Amp

_ +

+υo

−

A3

differential input single-ended output

Lundstrom: Fall 2019

_ +

Ad 2_ +

Ad1

sensor

Why differential?

+υid

−

Differential pair: Small-signal results

4

IO

−VSS

+VDD

RD RD

υi1

M1 M2 υi2

υo1 υo2

υid =υi1 −υi2

υic = υi1 +υi2( ) 2

υod =υo2 −υo1

Adm =

υod

υid

Adm = +gmRD

Rin = ∞

Lundstrom: Fall 2019

differential in differential out

Differential pair: Small-signal results

5

−VSS

+VDD

RD1 RD2

υi1

M1 M2 υi2

υo1 υo2

υid =υi1 −υi2

υic = υi1 +υi2( ) 2

υod =υo2 −υo1

RSS IO

Acm =

υod

υic

= 0

Lundstrom: Fall 2019

common in differential out

Differential pair: Small-signal results

6

IO

−VSS

+VDD

RD RD

υi1

M1 M2 υi2

υo2

υid =υi1 −υi2

υic = υi1 +υi2( ) 2

υod =υo2 −υo1

Adm =

υo2

υid

Adm = +

gmRD

2

Rin = ∞

Lundstrom: Fall 2019

differential in single ended out

Differential pair: Small-signal results

7

−VSS

+VDD

RD1 RD2

υi1

M1 M2 υi2

υo2

υid =υi1 −υi2

υic = υi1 +υi2( ) 2

υod =υo2 −υo1

RSS IO

Lundstrom: Fall 2019

common in single ended out

Acm =

υo2

υic

≈ −RD

2RSS

Half circuit concept

8 −VSS

+VDD

RD1 RD2

υi1

M1 M2 υi2

υo2

RSS IO

Half circuit concept

9 Lundstrom: Fall 2019

RD

+υid 2 −υod 2

M1

gm υid 2( )

Virtual ground

Differential mode

RD

υ01

M1

2RSS

υic

Common mode

Recall: CS Active load

10

+

υi

−

+

υ0

−

VDD

Q1 R1

Q2

IREF

Q3

Aυo= −gm roN || roP( )

Basic Amplifier Model: Thevenin

11

+υi

−

+−

Rout

Aυoυi

ii

Rin =υi

iiυo = Aυo

υi

Aυo= υo

υi RL=∞

Open circuit voltage gain

Basic Amplifier Model: Norton

12

+υi

−

Rout

Gmυi

ii

Rin =υi

iiυo = GmRoutυi

Gm = ioυi RL=0

Short circuit transconductance

CS Active load: Output resistance

13

+

υi

−

VDD

Q1 R1

Q2

IREF

Q3

⇐ Rout = roN || roP( )

CS Active load: SC transconductance

14

+

υi

−

VDD

Q1 R1

Q2

IREF

Q3

Gm = ioυi

= −gm1

id1

∞

ioid1 = gm1υi

io = −id1 = −gm1υi

Norton amplifier model for CS

15

+υi

−

Rout

Gmυi

ii

Rin =υi

iiυo = GmRoutυi

Rout = roN || roP( )

Gm = ioυi

= −gm1

16

Outline

1)  Quick Review 2)  MOS differential pair with active loads 3)  Simple analysis 4)  Rigorous small signal analysis 5)  Summary

Lundstrom: Fall 2019

One way

17

IO

−VSS

+VDD

υi1

M1 M2 υi2

VDD

R1 IREF

M3 M4 M5

υo1 υo2

Must be done carefully

“Current mirror loaded differential pair”

18

IO

−VSS

+VDD

υG1M1 M2

M3 M4

υO

υG2

19

Outline

1)  Quick Review 2)  MOS differential pair with active loads 3)  Simple analysis 4)  Rigorous small signal analysis 5)  Summary

Lundstrom: Fall 2019

DC Analysis

20

IO

−VSS

+VDD

υG1M1 M2

M3 M4

υO

υG2

How does the current split?

Small signal analysis: Differential

21

+υid 2

M1 M2

M3 M4

υo

−υid 2 RL

≈ 0*

Small signal analysis: Differential

22

+υid 2

M1 M2

M3 M4

υo

−υid 2 id1 id1

id1 2id1 = gmυid

RL

υo = 2id1RL = gmυid RL

Adm = gmRL

id1

≈ 0

id1 = gmυid 2

Small signal (common mode)

23

υic

M1 M2

M3 M4

υo

RL υic

RSS

*

Small signal (common mode)

24

υic

M1 M2

M3 M4

υo

id1 id1

id1 0

RL

υo = 0υic

Acm = 0

υic

RSS

id1

Current mirror loaded differential pair

25

IO

−VSS

+VDD

υi1 M1 M2

M3 M4

υo

υi2

Adm = gmRL

Acm = 0

Lundstrom: Fall 2019

26

Outline

1)  Quick Review 2)  MOS differential pair with active loads 3)  Simple analysis 4)  Rigorous small signal analysis 5)  Summary

Lundstrom: Fall 2019

Small signal circuit

27

IO

−VSS

+VDD

υG1M1 M2

M3 M4

υO

υG2

Lundstrom: Fall 2019

Small signal circuit

28

+VDD

M3

Rth = ?⇒

*

Rth =1gm|| ro ≈

1gm

Draw the small signal circuit

29

IO

−VSS

+VDD

υG1M1 M2

M3 M4

υO

υG2

*

Small signal circuit

30

1gm

ro4

ro1 ro2

υo

gmυgs1 gmυgs2

RSS

+υgs1

−

+υgs2

−

gmυgs3

−υgs3

+

Roadmap for small signal analysis

31

IO

−VSS

+VDD

υi1

M1 M2

M3 M4 υo

υi2

1)  SC transconductance 2)  Output resistance

Lundstrom: Fall 2019

Short circuit transconductance

32

IO

−VSS

+VDD

+υid 2M1 M2

M3 M4

Lundstrom: Fall 2019

∞ io

υd 2 = 0 υd1 ≈ 0

−υid 2

Short circuit transconductance

33

1gm

ro4

ro1 ro2

υo

gmυgs1 gmυgs2

RSS

+υgs1

−

+υgs2

−

gmυgs3

−υgs3

+

υd 2 = 0 υd1 ≈ 0

Short circuit transconductance

34

+υid 2

M1 M2

M3 M4

υo

−υid 2 id1 id1

id1 2id1 = gmυid

io = 2id1 = gmυid

id1

≈ 0

Gm = gm

Output resistance

35

1gm

ro4

ro1 ro2gmυgs1 gmυgs2

RSS

+υgs1

−

+υgs2

−

gmυgs3

−υgs3

+ix

υx

⇐ Rout

Output resistance

36

IO

−VSS

+VDD

M1 M2

M3 M4

Lundstrom: Fall 2019

⇐ Rout

Rout = ro2 || ro4

Common mode gain

37

1gm

ro4

ro1 ro2

υo

gmυgs1 gmυgs2

RSS

+υgs1

−

+υgs2

−

gmυgs3

−υgs3

+

υic υic

Common mode gain

38

IO

−VSS

+VDD

M1 M2

M3 M4

Lundstrom: Fall 2019

υo

Acm ≈ 1

2gm3RSS

υic υic

Summary

39

IO

−VSS

+VDD

υ1

M1 M2

M3 M4 υO

Gm ≡ioυid

= gm

SC transconductance

Output resistance

Rout = ro2 || ro4

υ2

Lundstrom: Fall 2019

OC voltage gain

Aυo

= gm ron || rop( )CM voltage gain

Acm ≈ 1

2gm3RSS

Questions

Lundstrom: Fall 2019 40

1)  Quick Review 2)  MOS differential pair with active loads 3)  Simple analysis 4)  Rigorous small signal analysis 5)  Summary

41

Appendix: Rigorous small signal analysis

1)  Short circuit transconductance 2)  Output resistance

Lundstrom: Fall 2019

Short circuit current / transconductance

42

IO

−VSS

+VDD

M1 M2

M3 M4

−υid 2

ac ground

+υid 2

io

Short-circuit transconductance

Gm ≡

ioυid

Short-circuit transconductance

43

1gm

ro4

ro1 ro2gmυgs1 gmυgs2

RSS

+υgs1

−

+υgs2

−

gmυgs3

−υgs3

+ ioGND

almost GND

almost a virtual ground

Short-circuit transconductance (2)

44

1gm

ro4

ro1 ro2gmυgs1 gmυgs2+

υid 2−

+−υid 2−

gmυgs3

−υgs3

+ io

Lundstrom: Fall 2019

Short-circuit transconductance (3)

45

1gm

ro1gmυgs1 gmυgs2+υid 2−

+−υid 2−

gmυgs3

−υgs3

+ io

io = − gmυgs2 + gmυgs3( )

io = gm

υid

2− gmυgs3

Lundstrom: Fall 2019

Short-circuit transconductance (4)

46

1gm

ro1gmυgs1+υid 2−

−υgs3

+υgs3 = −gm

υid

21gm|| ro1

⎛⎝⎜

⎞⎠⎟≈ −υid

2

Lundstrom: Fall 2019

Short-circuit transconductance (5)

47

1gm

ro1gmυgs1 gmυgs2+υid 2−

+−υid 2−

gmυgs3

−

υgs3 = −υid

2+ io

io = gm

υid

2− gmυgs3

io = gm

υid

2− gm −

υid

2⎛⎝⎜

⎞⎠⎟

io = gmυid

Lundstrom: Fall 2019

Short circuit tranconductance

48

IO

−VSS

+VDD

M1 M2

M3 M4

−υid 2

ac ground

+υid 2

io = gmυid

Short-circuit transconductance

Gm ≡

ioυid

Gm = gm

Output resistance

49

IO

−VSS

+VDD

M1 M2

M3 M4

υx

ix

Output resistance (2)

50

M1 M2

M3 M4

id 2 id 2

ix

id 2

?

Output resistance (3)

51

M1 M2

id 2 id 2

ix

id 2

1gm

ro4gmυgs3

−υgs3

+

id 2

id 2

υx

υx ro4

id 2 = ?

Output resistance looking into drain 2

52

M1 M2

id 2 id 2

id 2

1gm

ro4gmυgs3

−υgs3

+

id 2

id 2 υx ro4

ix υx

Ro2 = ro2 + gmro2RS

Ro2 = ro2 + gmro2

1gm

Ro2 = 2ro2

id 2 =

υx

Ro2

Finding ix

53

M1 M2

id 2 id 2

ix

id 2

1gm

ro4gmυgs3

−υgs3

+

id 2

id 2

υx

υx ro4

id 2 + ir04

KCL

ix = 2id 2 +

υx

r04

Small signal analysis

54

ix = 2id 2 +

υx

r04

id 2 =

υx

Ro2

Ro2 = 2ro2

ix =

2υx

2ro2

+υx

r04

=υx

1ro2

+ 1ro4

⎛

⎝⎜⎞

⎠⎟

Rout = ro2 || ro4

Lundstrom: Fall 2019

Summary: CM loaded differential pair

55

IO

−VSS

+VDD

+υid 2

M1 M2

M3 M4 υO

Gm ≡

ioυid

= gm

Short-circuit transconductance

Output resistance

Rout = ro2 || ro4

−υid 2

Lundstrom: Fall 2019

SS output equivalent circuit of the amplifier

56

Gmυid Rout

+υo

−

Lundstrom: Fall 2019