Electrical Engineering – Electronic Systems group

Presenter: Kanishkan VadivelLab Support: Mohammed Emad

Lab3: DNN Implementation on Enbedded ASIP

Outline• Introduction to ASIP• Lab3 – Overview• Guidelines for Submission

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Motivation for ASIP

ASIP – Application Specific Instruction-set Processor

• Problem

• General Purpose Processor – too slow for some applications, and not energy efficient

• ASIC – Lacks flexibility

• ASIP – Compromise between flexibility and performance

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Flexibility

Ene

rgy

Effi

cien

cy

ASIC

DSPGPP

Performance/AreaASIP

ASIP Introduction• Processor tuned for specific application

• Custom Instruction-set, compute nodes, and datapaths

• Compiler support• Example: Transport Triggered Architecture

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Compute nodes

Datapath

Basband chip(source: Synopsys)

Goals and Learning Objective• Goal: “Design and implement ASIP on FPGA for LeNet-5”

• Optimize the design (HW and SW) for maximum performance (runtime)

• Synthesis and implement your design on Pynq FPGA board• Learning Objectives

• Practical view point of ASIP design flow

• Trade-offs in ASIP design for DNN (e.g. Performance vs Flexibility)

• Hands-on experience on end-to-end design flow (from high-level software to Accelerator interfaced to SoC)

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LeNet - Architecture

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• Trained with MINST dataset

• Network (C code) and weights are provided as starting point

MINST Dataset

TTA-based Co-design Environment (TCE)

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Submission• Timeline:

• Opens on 1st Oct 2019 (today) – OnCourse

• Deadline: 1st Nov 2019 (23:59)

• Submission: OnCourse (report in pdf format + design files)

• Report format: IEEE double-column (at max 5-pages)• Questions: Use “Q&A Forum” on OnCourse• Grading: Report + Oral exam at end of the course (exact dates will be

communicated later)• Starting point: “Lab3 – Assignment” document in OnCourse

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Selecting your Assignment

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GPU

ASIP

Note: Enrollment Limit is 15 students for both assignment.!

OnCourse