1 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
LatticeECP4 FPGA Family
Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
November 2011
Lattice Semiconductor 5555 Northeast Moore Ct.
Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000
www.latticesemi.com
http://www.latticesemi.com/
2 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Introduction
The new and innovative LatticeECP4 FPGA family provides premium features in low
cost, low power programmable devices for mainstream applications, including versatile
6G SERDES for high-speed data transmission, built-in MACO Communications Engines
for efficient protocol processing, 7X more powerful DSP Blocks for wireless and video
applications, and a large number of Giga-scale serial I/Os for building high port density
communications equipment. The versatile FPGA family also features1066 Mbps DDR3
memory interfaces, high density on-chip memory and up to 250K logic elements (LUTs).
This whitepaper examines some of the innovative building blocks in LatticeECP4
FPGAs and how they empower customers to develop cost- and power-sensitive
wireline, wireless, video, industrial, and computing applications.
Figure 1 – Innovative Building Blocks in the Low Cost, Low Power LatticeECP4 FPGA
3 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
LatticeECP4 Architectural Overview
The LatticeECP4 FPGAs have been architected to be low cost, low power mid-range
devices with a broad range of communication, logic, and digital signal processing
capabilities. The architectural diagram in Figure 2 illustrates the key building blocks in
the LatticeECP4 FPGAs. The flexible logic array contains up to 250,000 4-input lookup
tables (LUT4s) with abundant signal routing and clocking resources for fast system
performance. The programmable devices also include rows of Embedded Block RAMs
(EBR) (10.6 Mbits) for high speed storage and access to local data.
Figure 2 – Architectural Overview of LatticeECP4 FPGAs
4 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
The next-generation LatticeECP4 FPGAs incorporate a number of high performance
innovations to facilitate transfer of bulk communication and video data to and from the
FPGA chip. These include high-quality 6Gbps SERDES/PCS, up to 22 MACO
Communications Engines, Giga-scale LVDS I/Os with self-clock-recovery and high-
speed DDR3 memory interfaces (1066 Mbps). These building blocks are discussed in
detail in the next section of this whitepaper
The new FPGA family also includes rows of Digital Signal Processing (DSP) Blocks that
can be cascaded together to solve complex wireless and video signal processing
problems. A number of unique innovations in the LatticeECP4 DSP Blocks, which
quadruple their signal processing throughput, are also discussed in the next section.
High Performance Innovations
This section discusses Lattice innovations in four key building blocks that facilitate high
speed communication and high throughput digital signal processing on programmable
platforms.
High Quality 6G SERDES
The LatticeECP4 FPGAs contain up to 16 high quality, standards-compliant 6 Gbps
SERDES channels. The jitter tolerant SERDES yield clear eye diagrams as illustrated in
Figure 3 below. The high dynamic range SERDES channels can be operated at speeds
from 155 Mbps to 6 Gbps. Lattice offers 6G SERDES in both low cost wire-bonded and
high performance flip chip packages, giving customers the option to deploy the
LatticeECP4 FPGAs in chip to chip as well as long reach backplane applications. Each
SERDES channel consumes less than 175mW of power at 6 Gbps, enabling the lowest
power implementation of high speed Serial Protocols. The built-in pre-emphasis and
equalization circuitry ensure low BER (bit error rate) and a high quality eye diagram as
shown in Figure 3.
5 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Figure 3 – Clear Eye Diagram of 6G SERDES
The SERDES hard IP block also implements Physical Coding Sub-layer (PCS) for
reliable transmission and reception of data. Each PCS logic channel contains dedicated
transmit and receive circuitry for high-speed, full-duplex serial data transfer up to 6
Gbps. The PCS logic in each channel can be configured to support an array of popular
data protocols (Figure 4) – 10 Gigabit Ethernet, Gigabit Ethernet, SGMII, XAUI, RXAUI,
PCI Express 2.1, PIPE, SRIO 2.1, CPRI, OBSAI, SD-SDI and HD-SDI. In addition, the
protocol-based logic can be fully or partially bypassed in a number of configurations to
allow users flexibility in designing their own high- speed data interfaces.
6 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Figure 4 – Multi-Rate, Multi-Protocol LatticeECP4 SERDES
The salient features of the LatticeECP4 SERDES/PCS Blocks are:
Up to 16 Channels of Full-duplex Serial Data per Device
150 Mbps to 6 Gbps Data Rate per Channel
Low Power: 175mW per Channel @ 6 Gbps
Built-In Pre-Emphasis and Equalization for Superior BER
Clean SERDES Eye Diagram with Low Jitter
Quad-based Architecture with the Ability to Mix and Match Different Protocols
and Multiple Data Rates within a Quad
Embedded Physical Coding Sub-layer (PCS) Logic for Reliable Communications
Industry Standard CEI-6G Compatible
7 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
The configurable SERDES/PCS Blocks can be seamlessly interconnected with
readymade MACO Communications Engines for efficient layer 2 communication
protocol processing. The 10-times efficient MACO Communications Engines are
discussed in the next section.
10X More Efficient MACO Communications Engines
The powerful MACO (Multi-Access Cost Optimized) Communications Engines are hard-
wired Intellectual Property (IP) blocks that implement popular communication protocols
using only 10% of the silicon resources and power compared to similar implementations
in other FPGA fabrics. These Communications Engines can be connected to either 6G
SERDES/PCS Blocks or 1.25G serial differential I/Os (sysIOs).
The LatticeECP4 Communications Engines include solutions for PCI Express 2.1,
multiple 10 Gigabit Ethernet MACs, Gigabit Ethernet MAC, and Tri-speed Ethernet
MACs, as well as Serial Rapid I/O (SRIO) 2.1 (Figure 5). The LatticeECP4 is the only
mid-range FPGA with a hardened Serial RapidIO 2.1 interface for building the latest
generation 3G/4G wireless systems. In addition, the Lattice devices incorporate the
industry's highest density hard IP blocks for efficient communication. The LatticeECP4
FPGAs can have up to 22 Communications Engines, whereas competitive "mid-range"
FPGAs have only PCI Express and/or a few Ethernet MAC IP blocks.
8 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Figure 5 – 10X Efficient MACO Communications Engines
The silicon-proven MACO Communications Engines have been designed and
characterized to meet the rigorous data and control plane timing requirements of each
protocol. These engines provide industry-compliant OSI Layer-2 (link layer) functionality
for each protocol as well as some additional OSI Layer-1 (physical layer) functionality.
The configurable MACO Engines can be customized by embedding proprietary code in
the surrounding FPGA logic fabric. The LatticeECP4 FPGAs provide a generic
Application Layer interface between the MACO Engines and the surrounding logic
fabric. Designers can also access network control and statistics vectors within the
MACO Engines.
Key benefits of MACO Communications Engines are:
Up to 22 hard-wired yet configurable Communications Engines that consume
only 10% of silicon resources and power
9 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Larger devices contain all the Communications Engines found within the smaller
ones, plus additional Engines
Easy to interconnect with SERDES/PCS Blocks and Logic Fabric using the
SystemPlanner Design Tool
The versatile MACO Communications Engines are seamlessly integrated with low jitter
6G SERDES/PCS Blocks to offer complete high bandwidth network interfaces. Lattice
Diamond 1.4 design software offers an easy-to-use SystemPlanner Tool to help users
efficiently integrate MACO Communications Engines with SERDES/PCS Blocks and the
surrounding logic fabric. For additional information about how MACO Communications
Engines can be connected with SERDES/PCS Blocks and FPGA Logic Fabric, please
review the Whitepaper – “LatticeECP4 MACO Communications Engines: Efficient
Network Solutions”. The combination of SERDES/PCS, Communications Engines and
programmable logic fabric is ideal for completing complex serial protocol-based designs
with lower cost, power and footprint, while accelerating time to market.
7X More Powerful DSP Blocks
The LatticeECP4 family features powerful digital signal processing (DSP) blocks with
unique innovations that offer 7x the performance of competitive FPGAs. These
proprietary innovations enable customers to implement complex, multi-antenna wireless
systems (4x4 MIMO at 40 MHz) and high performance video processing algorithms in
low cost, low power FPGA platforms.
The fully featured LatticeECP4 DSP Blocks (Figure 6 include 18x18 multipliers, 54-bit
cascadable ALUs, and wide adder-trees. Unique "Booster Logic" allows LatticeECP4
DSP blocks to run at twice the speed of the logic fabric. In addition, the LatticeECP4
DSP architecture leverages the symmetry of common filters to process twice as many
http://www.latticesemi.com/dynamic/view_document.cfm?document_id=43592http://www.latticesemi.com/dynamic/view_document.cfm?document_id=43592
10 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
signals. The combination of these two new innovations increases the throughput of
LatticeECP4 DSPs 7X compared to the previous generation LatticeECP3 FPGAs.
The flexible 18x18 multipliers can be split into 9x9 or combined into 36x36 to perfectly
match customers’ application requirements. Moreover, up to 576 multipliers can be
cascaded together to build complex filters for wireless Remote Radio Heads (RRH),
MIMO-based RF antenna solutions and video processing applications.
Figure 6 – 7X Powerful DSP Blocks in LatticeECP4 FPGAs
Unique strengths of the LatticeECP4 DSP Blocks include:
11 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Up to 576 multipliers (18x18)
Booster Logic and Pre-adders for 4X efficiency
Effectively the same throughput as 2304 LatticeECP3 symmetric multipliers
Effectively the same throughput as 1152 LatticeECP3 asymmetric multipliers
9x9, 18x18, 36x36, and 18x36 Modes
54-bit cascadable ALU
Two additional whitepapers from Lattice Semiconductor discuss the in-depth capabilities
of the fourth generation LatticeECP4 DSP Architecture and its use in Wireless
Applications. These are:
1. LatticeECP4 DSP Slice Architecture
2. LatticeECP4 DSP Wireless Applications
High Speed I/Os with Embedded Soft CDRs
The LatticeECP4 FPGAs offer a wide range of system I/Os to connect the FPGA to
other devices within a system. These range from single-ended, differential, to serial I/Os
with embedded clock data recovery (CDR) circuits, and high-speed memory interfaces
(DDR, DDR2, and DDR3). The single-ended and differential I/Os can run at speeds up
to 1.25Gbps, which is 50% faster than the previous generation LatticeECP3 family. The
high-speed memory (DDR3) interfaces are 33% faster and can run at speeds up to
1066 Mbps.
Another innovation in LatticeECP4 FPGAs is up to 40 embedded Clock Data Recovery
(CDR) Circuits, which are implemented in Programmable I/O Cells (PICs). The built-in
CDR circuits can be combined with differential I/Os (LVDS) to implement Giga-scale
serial interfaces (GIGA sysIOs), which do not require separate reference clocks. In
addition, CDR circuits can be configured and controlled via the soft logic in the FPGA
http://www.latticesemi.com/dynamic/view_document.cfm?document_id=43590http://www.latticesemi.com/dynamic/view_document.cfm?document_id=43591
12 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Fabric to adjust the timing and minimize BER for clear eye diagrams. LatticeECP4
programmable CDR circuits are often referred to as Soft CDRs.
The GIGA sysIOs with adjustable Soft CDRs can be used to implement popular Gigabit
Ethernet and SGMII interfaces. The ability to implement Gigabit Ethernet interfaces
using general purpose differential I/Os conserves the 6G SERDES for 2.5G or higher
bandwidth interfaces and . The GIGA serial I/Os can also be directly connected to built-
in Ethernet MACO Communications Engines. The availability of 40 serial GIGA sysIOs,
16 SERDES, and large number of Ethernet MAC Engines enables customers to build
high port density communication equipment using the low cost, low power LattifceECP4
FPGAs.
Figure 7 – Configurable Clock Data Recovery Circuit (Soft CDRs)
Figure 7 illustrates the functional block diagram of a LatticeECP4 Soft CDR circuit,
where the phase relationship of the receive data is monitored against a recovered clock.
Using soft IP specifically designed to dynamically monitor and control the Clock
Alignment logic, designers can establish and maintain a valid receive data window. To
13 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
learn more about the capabilities of pre-engineered source synchronous I/Os in
LatticeECP4 FPGAs, please review the whitepaper – “LatticeECP4 High Speed I/O”.
Target Applications
The next generation LatticeECP4 FPGAs with high-speed data interfaces, premium
Communications Engines and powerful DSP Blocks have been optimized for a wide
range of wireline and wireless communication and video processing applications. The
unique capabilities of LatticeECP4 FPGAs for these applications are discussed below:
Wireless Access
The LatticeECP4 FPGAs have a number of unique features to help customers design
multimode Remote Radio Heads (RRH) and 4G base stations. The 7x more powerful
DSP Blocks facilitate linearization of signals from multiple antennas. The LatticeECP4 is
the only FPGA that offers low-latency variation CPRI and SRIO 2.1 interfaces for
wireless applications. The SRIO 2.1 interface is implemented in the 10x more efficient
MACO Communications Engine.
Wireline Access
The large portfolio of MACO Communications Engines, high quality SERDES, and
GIGA sysIOs with embedded CDR circuits make the LatticeECP4 an ideal platform for
building state of the art Wireless Backhaul, Wireline Access, Switches & Routers, and
Storage & Computing systems. The LatticeECP4 FPGAs have up to 40 embedded CDR
circuits, which can be used to implement Gigabit Ethernet and SGMII interfaces using
numerous GIGA sysIO pins. The GIGA sysIOs with embedded CDRs and 6G
SERDES/PCS can be used to build high port density communication platforms.
http://www.latticesemi.com/dynamic/view_document.cfm?document_id=43593
14 Low Cost, Low Power FPGAs with Premium Features
A Lattice Semiconductor White Paper
Video Edge
The LatticeECP4 FPGAs have an optimum combination of resources for mainstream
video transmission, codecs, analytics, and processing applications. The low jitter 6G
SERDES and built-in MACO Communications Engines allow high-fidelity capture of
video data and transmission over long distances. The powerful DSP Blocks lead to cost-
efficient implementation of complex video processing algorithms. The high-speed DDR3
memory interface and differential I/O interface enable simultaneous processing of
multiple video channels. These building blocks in LatticeECP4 FPGAs enable
customers to quickly design Industrial Video Cameras, Surveillance Cameras,
Broadcast, Display, Medical Imaging, and Automotive Entertainment systems.
Summary
The new LatticeECP4 FPGA family has been architected to offer customers leading
edge communication, logic, and signal processing resources in low cost, low power
packages. This whitepaper examined in-depth four such building blocks. The availability
of these high performance capabilities on a programmable platform empowers
customers to target high volume, cost sensitive communication, video, computing and
industrial markets.
