LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1 · The triple-rate serial digital interface (SDI)...

LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1.0User Guide

UG823 June 22, 2011

Virtex-6 FPGA Triple-Rate SDI User Guide www.xilinx.com UG823 June 22, 2011

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Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

06/22/11 1.0 Initial Xilinx release. This document was released previously as UG791.

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Virtex-6 FPGA Triple-Rate SDI User Guide www.xilinx.com 3UG823 June 22, 2011

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 1: IntroductionAbout the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Supported Tools and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Virtex-6 FPGA Triple-Rate SDI Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: OverviewSD-SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13HD-SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133G-SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Video Payload ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Ancillary Data Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Complete Triple-Rate SDI Interface Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 3: Core ArchitectureCore Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Virtex-6 FPGA Triple-Rate SDI Core Top-Level Module . . . . . . . . . . . . . . . . . . . . . 19Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34DRP Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chapter 4: Triple-Rate SDI Receiver OperationTriple-Rate SDI Receiver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Bit Rate and Transport Format Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Operation of the Triple-Rate SDI Receiver in the Various SDI Modes . . . . . . . . 39

Table of Contents


4 www.xilinx.com Virtex-6 FPGA Triple-Rate SDI User GuideUG823 June 22, 2011

Triple-Rate SDI Receiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40SD-SDI RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40HD-SDI RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423G-SDI Level A RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433G-SDI Level B RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Electrical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Other Triple-Rate SDI RX Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Dual Link HD-SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Processing Embedded Audio and Other Ancillary Data . . . . . . . . . . . . . . . . . . . . . . . . 45SMPTE 352 Video Payload ID Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45SD-SDI EDH Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46SD-SDI Data Recovery Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48SD-SDI Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48RXEQMIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Chapter 5: Triple-Rate SDI Transmitter OperationTriple-Rate SDI Transmitter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Operation of the Triple-Rate SDI Transmitter in the SDI Modes . . . . . . . . . . . . . 53

SD-SDI Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54HD-SDI Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553G-SDI Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Level A Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Level B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Dual Link HD-SDI Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Summary of Triple-Rate TX Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Triple-Rate TX Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ST 352 Packet Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Line Number Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60CRC Generation and Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60EDH Generation and Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Ancillary Data Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Reference Clocks and Reference Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Electrical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Chapter 6: Implementing the CoreTiming Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Other Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63SD-SDI DRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64GTX Transceiver Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64



Chapter 1: Introduction

Chapter 2: OverviewFigure 2-1: Overview of Triple-Rate SDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 3: Core ArchitectureFigure 3-1: Triple-Rate SDI RX/TX Interface Detailed Block Diagram . . . . . . . . . . . . . . . 18

Chapter 4: Triple-Rate SDI Receiver OperationFigure 4-1: SD-SDI RX Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 4-2: Oscilloscope Capture of SD-SDI Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 4-3: HD-SDI RX Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 4-4: 3G-SDI Level A RX Timing (1080p 50 Hz or 60 Hz) . . . . . . . . . . . . . . . . . . . . . 43Figure 4-5: 3G-SDI Level B RX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 4-6: Using the GTX Transmitter to Generate the SD-SDI Recovered Clock . . . . 50Figure 4-7: Recovered SD-SDI Clock from GTX Transmitter . . . . . . . . . . . . . . . . . . . . . . . 51Figure 4-8: Example RXEQMIX RX Jitter Tolerance Test Results . . . . . . . . . . . . . . . . . . . 52

Chapter 5: Triple-Rate SDI Transmitter OperationFigure 5-1: SD-SDI TX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 5-2: HD-SDI TX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 5-3: 3G-SDI Level A TX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 5-4: 3G-SDI Level B TX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 6: Implementing the Core

Schedule of Figures






Chapter 2: Overview

Chapter 3: Core ArchitectureTable 3-1: Virtex-6 FPGA Triple-Rate SDI Core Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 4: Triple-Rate SDI Receiver OperationTable 4-1: rx_t_family Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 4-2: rx_t_rate Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 4-3: Encoding of rx_edh_errcnt_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 4-4: Encoding of rx_edh_anc_flags, rx_edh_ap_flags, and rx_edh_ff_flags Ports 47Table 4-5: Encoding of rx_edh_packet_flags Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Chapter 5: Triple-Rate SDI Transmitter OperationTable 5-1: Triple-Rate SDI TX Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58


Schedule of Tables





Preface

About This Guide

This user guide describes the LogiCORE™ IP Virtex®-6 FPGA Triple-Rate SDI core. This core implements triple-rate serial digital interface (SDI) receivers and transmitters in Virtex-6 devices. It supports SD-SDI, HD-SDI, and 3G-SDI (level A, level B-DL, and level B-DS) and dual-link HD-SDI standards.

Guide ContentsThis manual contains the following chapters:

• Chapter 1, Introduction

• Chapter 2, Overview

• Chapter 3, Core Architecture

• Chapter 4, Triple-Rate SDI Receiver Operation

• Chapter 5, Triple-Rate SDI Transmitter Operation

• Chapter 6, Implementing the Core

Additional ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website at:

http://www.xilinx.com/support.

ReferencesFor more information, see these documents at http://www.xilinx.com/support:

• DS848: LogiCORE IP Virtex-6 FPGA Triple-Rate SDI Data Sheet

• UG366: Virtex-6 FPGA GTX Transceivers User Guide

• XAPP1014: Audio/Video Connectivity Solutions for Virtex-5 FPGAs

• XAPP1075: Implementing Triple-Rate SDI with Virtex-6 FPGA GTX Transceivers

• XAPP1076: Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers

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Preface: About This Guide

List of AcronymsThe following table defines acronyms used in this document.

Acronym Definition

ANC Ancillary

AP Active Picture

ASSP Application-Specific Standard Product

CDR Clock Data Recovery

CML Current Mode Logic

CRC Cyclic Redundancy Check

DRU Data Recovery Unit

EAV End of Active Video

EDH Error Detection and Handling

FF Full Field

HANC Horizontal Ancillary

HD High Definition

HDL Hardware Description Language

LVDS Low-Voltage Differential Signalling

MMCM Mixed-Mode Clock Manager

RX Receiver

SAV Start of Active Video

SD Standard Definition

SDI Serial Digital Interface

SMPTE Society of Motion Picture and Television Engineers

TRS Timing Reference Signal

TX Transmitter

VPID Video Payload Identifier



Chapter 1

Introduction

The triple-rate serial digital interface (SDI) supports the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards. The SDI interface is widely used in professional broadcast video equipment. SDI interfaces are used in broadcast studios and video production centers to carry uncompressed digital video along with embedded ancillary data, such as multiple audio channels.

About the CoreThe LogiCORE™ IP Virtex®-6 FPGA Triple-Rate SDI core implements triple-rate SDI receivers and transmitters in Virtex-6 devices. It supports SD-SDI, HD-SDI, and 3G-SDI (level A, level B-DL, and level B-DS) and dual-link HD-SDI standards. The Virtex-6 FPGA Triple-Rate SDI core is compatible with the GTX transceivers in Virtex-6 devices. SDI interface solutions for other Xilinx® FPGAs can be found at www.xilinx.com.

The Virtex-6 FPGA Triple-Rate SDI core is a CORE Generator™ IP software core. It does not require a license. It is provided in source code form in both Verilog and VHDL.

Supported Tools and System RequirementsFor a list of system requirements, see the ISE Design Suite 13: Release Notes Guide at the web page 13.2 Release Notes/Known Issues.

ToolsThe tools and their respective versions for the 13.2 release are:

• ISE® software 13.2

• Mentor Graphics ModelSim 6.6d

Technical SupportFor technical support, go to www.xilinx.com/support. Questions are routed to a team with expertise using the Virtex-6 FPGA Triple-Rate SDI core.

FeedbackXilinx welcomes comments and suggestions about the Virtex-6 FPGA Triple-Rate SDI core and the accompanying documentation.

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Virtex-6 FPGA Triple-Rate SDI CoreFor comments or suggestions about the core, submit a WebCase at www.xilinx.com/support/clearexpress/websupport.htm. Be sure to include this information:

• Core name

• Core version number

• Explanation of your comments

DocumentationFor comments or suggestions about the core documentation, submit a WebCase at www.xilinx.com/support/clearexpress/websupport.htm. Be sure to include this information:

• Document title

• Document number

• Page number(s) to which your comments refer

• Explanation of your comments

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Chapter 2

Overview

The LogiCORE™ IP Virtex®-6 FPGA Triple-Rate SDI core implements three main SMPTE interface standards:

• SD-SDI (SMPTE ST 259): SDTV Digital Signal/Data - Serial Digital Interface

• HD-SDI (SMPTE ST 292): 1.5 Gb/s Signal/Data Serial Interface

• 3G-SDI (SMPTE ST 424): 3 Gb/s Signal/Data Serial Interface

In addition, two triple-rate SDI receivers or transmitters can be combined to implement an SMPTE ST 372 dual link 1.5 Gb/s digital interface.

SD-SDIThe Virtex-6 FPGA Triple-Rate SDI core supports the 270 Mb/s bit rate (level C) of the SD-SDI standard. This bit rate is too slow for the RX clock data recovery (CDR) circuit in the GTX receiver to receive, directly, so the GTX receiver is used to oversample the 270 Mb/s data stream, and a data recovery unit (DRU), implemented in the Virtex-6 FPGA Triple-Rate SDI core, is used to recover the data with a high degree of jitter tolerance. This DRU supports only 270 Mb/s SD-SDI. However, it is possible to use a more general-purpose DRU to receive any SD-SDI bit rate. Customers needing to do this should contact Xilinx technical support for more information.

The Virtex-6 FPGA Triple-Rate SDI core fully supports the SMPTE RP 165 Error Detection and Handling (EDH) standard for the receive and transmit sections.

HD-SDIAlthough the HD-SDI standard is called a 1.5 Gb/s interface, the bit rates supported by HD-SDI are 1.485 Gb/s and 1.485/1.001 Gb/s. The Virtex-6 FPGA Triple-Rate SDI core fully supports both bit rates. The Triple-Rate SDI core also fully supports generation (TX side) and checking (RX side) of CRC values for each video line and the insertion (TX side) and capture (RX side) of line number values for each line.

3G-SDIThe 3G-SDI standard is called a 3 Gb/s interface, but the bit rates are 2.97 Gb/s and 2.97/1.001 Gb/s. The Virtex-6 FPGA Triple-Rate SDI core fully supports both of these bit rates. 3G-SDI supports several different mapping levels, described in the SMPTE ST 425 standard. These levels are called A, B-DL, and B-DS. The Triple-Rate SDI core supports all three levels. As with the HD-SDI standard, the Triple-Rate SDI core supports CRC generation and checking and line number insertion and capture for 3G-SDI.



Chapter 2: Overview

Video Payload IDThe Virtex-6 FPGA Triple-Rate SDI core implements an SMPTE ST 352 compliant video payload ID (VPID) ancillary data packet insertion capability for the transmitter that works in all SDI modes (SD-SDI, HD-SDI, 3G-SDI, and dual link HD-SDI). The receive side also detects and captures the four data bytes of ST 352 VPID packets.

Ancillary Data SupportThe Virtex-6 FPGA Triple-Rate SDI core allows the application to implement ancillary data packet insertion prior to transmission. While the core does not provide ancillary data packet insertion capability, it has the necessary datapaths to allow ancillary data packet insertion to be implemented by the application. On the receive side, all embedded ancillary data is preserved by the Triple-Rate SDI core’s receiver section and is present in the SDI data streams output from the core. Applications can process the received SDI data streams to process the ancillary data as needed.

Complete Triple-Rate SDI Interface SolutionA complete triple-rate SDI interface is comprised of:

• A GTX transceiver

• The LogiCORE IP Virtex-6 FPGA Triple-Rate SDI core

• An industry-standard SDI cable driver (for TX) and SDI cable equalizer (for RX)

• GTX reference clock source(s)

Figure 2-1 shows a high-level block diagram of an SDI receive/transmit interface using the Virtex-6 FPGA Triple-Rate SDI core. The Triple-Rate SDI core implements one triple-rate SDI receiver and one triple-rate SDI transmitter. If only a receiver or only a transmitter is needed by the application, the input ports for the unused half of the core can be tied to ground, and the output ports can be left unconnected. The synthesis tool optimizes the unused portion of the core out of the application.

When both the receiver and transmitter sections of the Triple-Rate SDI core are used, the receiver and transmitter are completely independent. They can operate in different SDI modes and bit rates (receiving 3G-SDI at 2.97/1.001 Gb/s while transmitting SD-SDI at 270 Mb/s or HD-SDI at either bit rate, for example).

The Virtex-6 FPGA Triple-Rate SDI core always supports all three SDI modes (SD-SDI, HD-SDI, and 3G-SDI). If only a subset of these modes is required by an application, the full Triple-Rate SDI core is still used.



Complete Triple-Rate SDI Interface Solution

Notes relevant to Figure 2-1:

1. The SDI cable equalizer and cable driver are external to the FPGA.

2. The optional ancillary (ANC) packet insertion function is not included with the Virtex-6 FPGA Triple-Rate SDI core.

X-Ref Target - Figure 2-1

Figure 2-1: Overview of Triple-Rate SDI Interface



Chapter 2: Overview



Chapter 3

Core Architecture

Core Block DiagramFigure 3-1 shows a detailed top-level block diagram of a complete triple-rate SDI receive/transmit interface implemented with the LogiCORE™ IP Virtex®-6 FPGA Triple-Rate SDI core.



Chapter 3: Core Architecture


Figure 3-1: Triple-Rate SDI RX/TX Interface Detailed Block Diagram



Virtex-6 FPGA Triple-Rate SDI Core Top-Level Module

Virtex-6 FPGA Triple-Rate SDI Core Top-Level ModuleThe Virtex-6 FPGA Triple-Rate SDI core top-level module implements three main functions:

• Triple-rate SDI receiver

• Triple-rate SDI transmitter

• GTX transceiver control

The GTX transceiver control function provides the necessary resets and other control for the GTX transceiver to initialize the transceiver and to dynamically change the GTX transceiver attributes to change the SDI mode in which the receiver and transmitter are operating.

Table 3-1 describes the ports of the Triple-Rate SDI core's top-level module.

Table 3-1: Virtex-6 FPGA Triple-Rate SDI Core Ports

Port Name I/O Width Description

Receive Ports

rx_usrclk In 1

This clock input is connected to the global or regional clock that drives the RXUSRCLK2 clock input of the GTX receiver. The source of this clock is usually the RXRECCLK output of the GTX receiver. The clock frequency must be 148.5 MHz (or 148.5/1.001 MHz) for 3G-SDI and SD-SDI modes. It must be 74.25 MHz (or 74.25/1.001 MHz) for HD-SDI mode.

rx_rst In 1

This synchronous reset input usually can be tied to ground because a reset is not required. After FPGA configuration, this module is in a fully operational mode and does not require a reset. Both rx_ce_sd and rx_din_rdy_3G must be High when rx_rst is High to completely reset the receiver.

rx_frame_en In 1

This input enables the SDI framer function. When this input is High, the framer automatically readjusts the output word alignment to match the alignment of each timing reference signal (TRS), EAV or SAV. Normally, this input is always High. However, if controlled properly, this input can be used to implement TRS alignment filtering. For example, if the nsp output is connected to the rx_frame_en input, the framer ignores a single misaligned TRS, keeping the existing word alignment until the new word alignment is confirmed by a second matching TRS. It is important to turn off any TRS filtering during the synchronous switching lines by driving the rx_frame_en input High on the synchronous switching lines.




rx_mode_en In 3

This port has unary bits to enable reception of each of the three SDI modes:

• Bit 0 enables HD-SDI mode• Bit 1 enables SD-SDI mode• Bit 2 enables 3G-SDI mode

When a bit is High, the corresponding SDI mode is enabled. When a bit is Low, the receiver does not attempt to detect incoming SDI signals for that mode. Disabling unused SDI modes using these bits decreases the amount of time it takes for the receiver to lock to the incoming signal when it changes modes.

rx_mode Out 2

This output port indicates the current SDI mode of the receiver:

• 00 = HD-SDI• 01 = SD-SDI• 10 = 3G-SDI

When the receiver is not locked, the rx_mode port changes values as the receiver searches for the correct SDI mode. During this time, the rx_mode_locked output is Low. When the receiver detects the correct SDI mode, the rx_mode_locked output goes High.

rx_mode_HD

rx_mode_SD

rx_mode_3G

Out 1

These three output ports are decoded versions of the rx_mode port. They are provided for convenience. Unlike the rx_mode port, which changes continuously as the receiver seeks to identify and lock to the incoming signal, these outputs are all forced Low when the receiver is not locked. The output matching the current SDI mode of the receiver is High when rx_mode_locked is High.

rx_mode_locked Out 1

When this output is Low, the receiver is actively searching for the SDI mode that matches the input data stream. During this time, the rx_mode output port changes frequently. When the receiver locks to the correct SDI mode, the rx_mode_locked output goes High.

Table 3-1: Virtex-6 FPGA Triple-Rate SDI Core Ports (Cont’d)





rx_bit_rate Out 1

This output port indicates which bit rate is being received in HD-SDI and 3G-SDI modes. This output is only valid when rx_mode_locked is High.

• HD-SDI mode: • rx_bit_rate = 0: Bit rate = 1.485 Gb/s• rx_bit_rate = 1: Bit rate = 1.485/1.001 Gb/s

• 3G-SDI mode:• rx_bit_rate = 0: Bit rate = 2.97 Gb/s• rx_bit_rate = 1: Bit rate = 2.97/1.001 Gb/s

rx_t_locked Out 1This output is High when the transport detection function in the receiver has identified the transport mode of the SDI signal.

rx_t_family Out 4

This output indicates which family of video signals is being used as the transport on the SDI interface. This output is only valid when rx_t_locked is High. This port does not necessarily identify the video format of the picture being transported. It only identifies the transport characteristics. See Table 4-1, page 38 for the encoding of this port.

rx_t_rate Out 4

This output indicates the frame rate of the transport. This is not necessarily the same as the frame rate of the actual picture. See Table 4-2, page 39 for the encoding of this port. This output is only valid when rx_t_locked is High.

rx_t_scan Out 1

This output indicates whether the transport is interlaced (Low) or progressive (High). This is not necessarily the same as the scan mode of the actual picture. This output is only valid when rx_t_locked is High.

rx_level_b_3G Out 1

In 3G-SDI mode, this output is driven High when the input signal is level B and driven Low when the input signal is level A. This output is only valid when rx_mode_3G is High.

rx_ce_sd Out 1

This output is a clock enable for SD-SDI mode. It is asserted, on average, one cycle out of every 5.5 cycles of rx_usrclk in SD-SDI mode. The SD-SDI data stream on the rx_ds1a port and the RX video timing signals (rx_trs, rx_eav, and rx_sav) are only valid when rx_ce_sd is High in SD-SDI mode. In other SDI modes, rx_ce_sd is always High.






rx_nsp Out 1

When this output is High, it indicates that the framer has detected a TRS at a new word alignment. If rx_frame_en is High, this output is only asserted briefly. If rx_frame_en is Low, this output remains High until the framer is allowed to readjust to the new TRS alignment (by asserting rx_frame_en High during the occurrence of a TRS).

rx_line_a Out 11

The current line number captured from the LN words of the Y data stream is output on this port. This output is valid in HD-SDI and 3G-SDI modes, but not in SD-SDI mode. In 3G-SDI level B mode, the output value is the line number from the Y data stream of link A or HD-SDI signal 1. For any case where the interface line number is not the same as the picture line number, such as for 1080p 60 Hz carried on 3G-SDI level B or dual link HD-SDI, the output value is the interface line number, not the picture line number.

rx_a_vpid Out 32

All four user data bytes of the SMPTE 352 packet from data stream 1 are output on this port in this format: most-significant byte to least-significant byte: byte4, byte3, byte2, byte1. This output port is valid only when rx_a_vpid_valid is High. This port is potentially valid in any SDI mode, if there are SMPTE 352 packets embedded in the SDI signal. In 3G-SDI level A mode, the output data is the VPID data captured from data stream 1 (luma). In 3G-SDI level B mode, the output data is the VPID data captured from data stream 1 of link A (dual link streams,) or HD-SDI signal 1 (dual HD-SDI signals).

rx_a_vpid_valid Out 1 This output is High when rx_a_vpid is valid.

rx_b_vpid Out 32

All four user data bytes of the SMPTE 352 packet from data stream 2 are output on this port in this format: most-significant byte to least-significant byte: byte4, byte3, byte2, byte1. This output is valid only in 3G-SDI mode and only when rx_b_vpid_valid is High. In 3G-SDI level A mode, the output data is the VPID data captured from data stream 2 (chroma). In 3G-SDI level B mode, the output data is the VPID data captured from data stream 1 of link B (dual link streams) or HD-SDI signal 2 (dual HD-SDI signals).

rx_b_vpid_valid Out 1 This output is High when rx_b_vpid is valid.






rx_crc_err_a Out 1

This output is asserted High for one sample period when a CRC error is detected on the previous video line. For 3G-SDI level B mode, this output indicates CRC errors on data stream 1 only. There is a second output called rx_crc_err_b that indicates CRC errors on data stream 2 for 3G-SDI level B mode. This output is not valid in SD-SDI mode.

rx_ds1a Out 10

The recovered data stream 1 is output on this port. The contents of this data stream are dependent on the SDI mode:

• SD-SDI: Multiplexed Y/C data stream• HD-SDI: Y data stream• 3G-SDI level A: Data stream 1• 3G-SDI level B-DL: Data stream 1 of link A• 3G-SDI level B-DS: Y data stream of HD-SDI

signal 1

rx_ds2a Out 10

The recovered data stream 2 is output on this port. The contents of this data stream are dependent on the SDI mode:

• SD-SDI: Not used• HD-SDI: C data stream• 3G-SDI level A: Data stream 2• 3G-SDI level B-DL: Data stream 2 of link A • 3G-SDI level B-DS: C data stream of HD-SDI

signal 1

rx_eav Out 1This output is asserted High for one sample time when the XYZ word of an EAV is present on the data stream output ports.

rx_sav Out 1This output is asserted High for one sample time when the XYZ word of an SAV is present on the data stream output ports.

rx_trs Out 1This output is asserted High for four consecutive sample times when the four words of an EAV or SAV are output on the data stream ports.

rx_line_b Out 11

This output port is only valid in 3G-SDI level B mode. It outputs the line number for the Y data stream of link B or HD-SDI signal 2. For any case where the interface line number is not the same as the picture line number, the line number output on this port is the interface line number, not the picture line number.






rx_dout_rdy_3G Out 1

In 3G-SDI level B mode, the output data rate is 74.25 MHz, but the rx_usrclk frequency is 148.5 MHz. The rx_dout_rdy_3G output is asserted at a 74.25 MHz rate in 3G-SDI level B mode. This output is always High in all other modes, allowing it to be used as a clock enable to downstream modules.

rx_ds1b Out 10

This output is only used in 3G-SDI level B mode. The data stream output on this port is:

• 3G-SDI level B-DL: Data stream 1 of link B• 3G-SDI level B-DS: Y data stream of HD-SDI

signal 2

rx_ds2b Out 10

This output is only used in 3G-SDI level B mode. The data stream output on this port is:

• 3G-SDI level B-DL: Data stream 2 of link B• 3G-SDI level B-DS: C data stream of HD-SDI

signal 2

rx_crc_err_b Out 1

This is the CRC error indicator for link B or HD-SDI signal 2. The rx_crc_err_b output is asserted High for a single clock cycle when a CRC error is detected. This signal is only valid in 3G-SDI level B-DS and B-DL modes.

rx_edh_errcnt_en In 16This input controls which EDH error conditions increment the rx_edh_errcnt counter. See Table 4-3, page 46 for more details.

rx_edh_clr_errcnt In 1

When High, this input clears the rx_ed_errcnt counter. This input port must be High during the same clock cycle when rx_ce_sd is also High to clear the error counter.

rx_edh_ap Out 1This output is asserted High when the active picture CRC calculated for the previous field does not match the AP CRC value in the EDH packet.

rx_edh_ff Out 1This output is asserted High when the full field CRC calculated for the previous field does not match the FF CRC value in the EDH packet.

rx_edh_anc Out 1This output is asserted High when an ancillary data packet checksum error is detected.

rx_edh_ap_flags Out 5The active picture error flag bits from the most recently received EDH packet are output on this port. See Table 4-4, page 47 for more information.

rx_edh_ff_flags Out 5The full field error flag bits from the most recently received EDH packet are output on this port. See Table 4-4, page 47 for more information.






rx_edh_anc_flags Out 5The ancillary error flag bits from the most recently received EDH packet are output on this port. See Table 4-4, page 47 for more information.

rx_edh_packet_flags Out 4This port outputs four error flags related to the most recently received EDH packet. See Table 4-5, page 48 for more information.

rx_edh_errcnt Out 16

This port is the SD-SDI EDH error counter. It increments once per field when any of the error conditions enabled by the rx_edh_err_en port occurs during that field.

rx_recclk_txdata Out 20

This output port can be connected to a GTX TXDATA port to use the GTX transmitter to synthesize a 270 MHz recovered clock in SD-SDI mode. This feature is optional and is not required for operation of the triple-rate SDI receiver.

Transmit Ports

tx_usrclk In 1

This clock input must be driven by the same clock that drives the TXUSRCLK2 port of the GTX transmitter. It must have a frequency of 74.25 MHz or 74.25/1.001 MHz for HD-SDI, 148.5 MHz or 148.5/1.001 MHz for 3G-SDI, and 148.5 MHz for SD-SDI modes.

tx_ce In 3

The clock enable must be asserted at a 27 MHz rate for SD-SDI mode (with a mandatory 5/6/5/6 clock cycle cadence). For all other SDI modes, the clock enable is always High. Three identical copies of the clock enable signal must be provided on the three bits of this port.

tx_din_rdy In 1

For SD-SDI, HD-SDI, and level A 3G-SDI modes, this input must be kept High at all times. For level B 3G-SDI mode, this input must be asserted every other clock cycle.

tx_rst In 1

This synchronous reset input resets the transmit section when High. To fully reset the transmitter, both tx_ce and tx_din_rdy must be High when tx_rst is High.

tx_mode In 2

This input port selects the transmitter SDI mode:

• 00 = HD-SDI• 01 = SD-SDI• 10 = 3G-SDI• 11 = Invalid






tx_rate_change_done Out 1

This output indicates when the transmitter has completed the transition from one SDI mode to another. When a change on tx_mode is recognized, tx_rate_change_done goes Low and stays Low until the core has completed changing the SDI mode in which the GTX transceiver is operating. When this output is High, the transmitter is operating normally.

tx_level_b_3G In 1

In 3G-SDI mode, this input determines whether the module is configured for level A (level = Low) or for level B (level = High). In 3G-SDI mode, this input must be properly controlled to produce legal 3G-SDI data streams.

tx_insert_crc In 1

When this input is High, the transmitter generates and inserts CRC values on each video line in HD-SDI and 3G-SDI modes. When this input is Low, CRC values are not generated and inserted. This input is ignored in SD-SDI mode.

tx_insert_ln In 1

When this input is High, the transmitter inserts line numbers after the EAV in each video line. The line number must be supplied on the tx_line_a and tx_line_b input ports. This input is ignored in SD-SDI mode.

tx_insert_edh In 1

When this input is High, the transmitter generates and inserts EDH packets in every field in SD-SDI mode. When this input is Low, EDH packets are not inserted. This input is ignored in HD-SDI and 3G-SDI modes.

tx_insert_vpid In 1

When this input is High, ST 352 packets are inserted into the data streams, otherwise the packets are not inserted. ST 352 packets are mandatory in 3G-SDI and dual link HD-SDI modes and optional in HD-SDI and SD-SDI modes.

tx_overwrite_vpid In 1

If this input is High, ST 352 packets already present in the data streams are overwritten. If this input is Low, existing ST 352 packets are not overwritten. When transporting ST 372 dual link data streams on a 3G-SDI level B interface, existing ST 352 packets in the data streams must be updated to indicate that the interface is 3G-SDI rather than HD-SDI mode. This module updates these packets only when overwrite is High. So, unless the ST 352 packets are being updated externally to the triple-rate SDI core, this input must be High when transmitting in 3G-SDI level B-DL mode.






tx_video_a_y_in In 10

This is the data stream A Y input. The data on this port depends on the SDI mode:

• SD-SDI: The multiplexed Y/C data stream enters the module on this port.

• HD-SDI: The Y data stream enters the module on this port.

• 3G-SDI level A: Data stream 1, as defined by SMPTE 425, enters the module on this port.

• Dual link HD-SDI or 3G-SDI level B-DL: The Y data stream of link A enters the module on this port.

• 3G-SDI level B-DS: The Y data stream of HD-SDI signal 1 enters the module on this port.

tx_video_a_c_in In 10

This is the data stream A C input. The data on this port depends on the SDI mode:

• SD-SDI: Unused.• HD-SDI and 3G-SDI level A: The C data stream

enters the module on this port.• Dual link HD-SDI or 3G-SDI level B-DL: The C

data stream of link A enters the module on this port.

• 3G-SDI level B-DS: The C data stream of HD-SDI signal 1 enters the module on this port.

tx_video_b_y_in In 10

This is the data stream B Y input: The data stream on this port depends on the SDI mode:

• Dual link HD-SDI or 3G-SDI level B-DL: The Y data stream of link B enters the module on this port.

• 3G-SDI level B-DS: The Y data stream of HD-SDI signal 2 enters the module on this port.

• For other SDI modes, this input port is unused.

tx_video_b_c_in In 10

This is the data stream B C input: The data stream on this port depends on the SDI mode:

• Dual link HD-SDI or 3G-SDI level B-DL: The C data stream of link B enters the module on this port.








tx_line_a In 11

The current line number must be provided to the module through this port if either ST 352 VPID packet insertion is enabled (tx_insert_vpid = High) or if HD-SDI and 3G-SDI line number insertion is enabled (tx_insert_ln = High).

SD-SDI only uses 10-bit line numbers, so bit 10 of the port must be 0 in SD-SDI mode. In SD-SDI mode, this input is only used for ST 352 VPID packet insertion. If tx_insert_vpid is Low, this input port is ignored in SD-SDI mode.

The line number must be valid at least one clock cycle before the start of the HANC space (by the XYZ word of the EAV) and must remain valid during the entire HANC interval.

This input is the only line number input used for SD-SDI, HD-SDI, and 3G-SDI level A modes. For 3G-SDI level B mode, a second line number input port, tx_line_b, is also provided.

For video formats where the picture line number is different from the transport line number, the value supplied on this port must be the transport line number.

tx_line_b In 11

This second line number input port is used only for 3G-SDI level B mode. This additional line number port allows the two separate HD-SDI signals to be vertically unsynchronized in level B-DS mode. When using either 3G-SDI level B-DL or B-DS, this port must be given a valid line number input. This input port has the same timing and requirements described for tx_line_a.

tx_vpid_byte1 In 8This value is inserted as the first user data word of the ST 352 packet. It must be valid during the entire HANC interval.

tx_vpid_byte2 In 8This value is inserted as the second user data word of the ST 352 packet. It must be valid during the entire HANC interval.

tx_vpid_byte3 In 8This value is inserted as the third user data word of the ST 352 packet. It must be valid during the entire HANC interval.

tx_vpid_byte4a In 8

This value is inserted as the fourth user data word of the ST 352 packet. This word is used for the ST 352 packets inserted into SD-SDI, HD-SDI, and 3G-SDI level A data streams. For 3G-SDI level B and dual link HD-SDI modes, this value is used for the ST 352 packet inserted into Y channel of link A only. This input must be valid during the entire HANC interval.






tx_vpid_byte4b In 8

This value is inserted as the fourth user data word of ST 352 packets inserted in the Y channel of link B for 3G-SDI level B and dual link HD-SDI modes only. This input value is not used for SD-SDI, HD-SDI, or 3G-SDI level A modes. This input must be valid during the entire HANC interval.

tx_vpid_line_f1 In 11

The ST 352 packet is inserted in the HANC space of the line number specified by this input port. For interlaced video, this input port specifies a line number in field 1. For progressive video, this specifies the only line in the frame where the packet is inserted. The input value must be valid during the entire HANC interval. If tx_insert_vpid is Low, this input is ignored.

tx_vpid_line_f2 In 11

For interlaced video, an ST 352 packet is inserted on the line number in field 2 indicated by this value. For progressive video, this input port must be disabled by holding the tx_vpid_line_f2_en port Low. The input value must be valid during the entire HANC interval. This input is ignored if either tx_insert_vpid or tx_vpid_line_f2_en is Low.

tx_vpid_line_f2_en In 1

This input controls whether or not ST 352 packets are inserted on the line indicated by line_f2. For interlaced video, this input must be High. For progressive video, this input must be Low. For progressive video transported on an interlaced transport, such as 1080p 60 Hz transported by either 3G-SDI level B-DL or dual link HD-SDI, ST 352 packets must be inserted into both fields of the interlaced transport, so this input must be High. This input must be valid during the entire HANC interval. This input is ignored if tx_insert_vpid is Low.

tx_ds1a_out Out 10

This is the link A data stream 1 output. The data stream output on this port contains ST 352 packets if tx_insert_vpid is High. If the application needs to insert ancillary data packets, they should be inserted into the data stream output on this port. The resulting data stream then should be supplied to the tx_ds1a_in port.

The data on this port depends on the SDI mode:

• SD-SDI: Multiplexed Y/C data stream.• HD-SDI: Y data stream.• 3G-SDI level A: Data stream 1.• Dual link HD-SDI or 3G-SDI level B-DL: Y data

stream of link A.• 3G-SDI level B-DS: Y data stream of HD-SDI

signal 1.






tx_ds2a_out Out 10

This is the link A data stream 2 output. The data stream output on this port contains ST 352 packets if tx_insert_vpid is High. If the application needs to insert ancillary data packets, they should be inserted into the data stream output on this port. The resulting data stream then should be supplied to the tx_ds2a_in port.


• SD-SDI: Unused.• HD-SDI: C data stream.• 3G-SDI level A: Data stream 2.• Dual link HD-SDI or 3G-SDI level B-DL: C data

stream of link A.• 3G-SDI level B-DS: C data stream of HD-SDI

signal 1.

tx_ds1b_out Out 10

This is the link B data stream 1 output. The data stream output on this port contains ST 352 packets if tx_insert_vpid is High. If the application needs to insert ancillary data packets, they should be inserted into the data stream output on this port. The resulting data stream then should be supplied to the tx_ds1b_in port.


• Dual link HD-SDI or 3G-SDI level B-DL: Y data stream of link B.

• 3G-SDI level B-DS: Y data stream of HD-SDI signal 2.


tx_ds2b_out Out 10

This is the data stream B C input: The data stream on this port depends on the SDI mode:

• Dual link HD-SDI or 3G-SDI level B-DL: the C data stream of link B enters the module on this port.








tx_use_dsin In 1

This input controls the source of the data streams sent by the transmitter. When this input is High, the sources of the transmitted data streams are the tx_ds1a_in, tx_ds2a_in, tx_ds1b_in, and tx_ds2b_in input ports. When this input is Low, the source of the transmitted data streams are internal to the core, coming directly from the video payload ID insertion function. When the application needs to insert ancillary data, the tx_use_dsin port is driven High to allow the application to modify the data streams and provide the modified data streams to the transmitter on the tx_dsxx_in ports. When no ancillary data insertion is required, the tx_use_dsin input is driven Low, and the tx_dsxx_in ports are ignored.

tx_ds1a_in In 10

This is the link A data stream 1 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode:

• SD-SDI: Multiplexed Y/C data stream.• HD-SDI: Y data stream.• 3G-SDI level A: Data stream 1.• Dual link HD-SDI or 3G-SDI level B-DL: Y data

stream of link A.• 3G-SDI level B-DS: Y data stream of HD-SDI

signal 1.

tx_ds2a_in In 10

This is the link A data stream 2 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode:

• SD-SDI: Unused.• HD-SDI and 3G-SDI level A: The C data stream

enters the module on this port.• Dual link HD-SDI or 3G-SDI level B-DL: C data

stream of link A.• 3G-SDI level B-DS: C data stream of HD-SDI

signal 1.






tx_ds1b_in In 10

This is the link B data stream 1 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode:

• Dual link HD-SDI or 3G-SDI level B-DL: Y data stream of link B.

• 3G-SDI level B-DS: Y data stream of HD-SDI signal 2.


tx_ds2b_in In 10

This is the link B data stream 2 input. This port is ignored if tx_use_dsin is Low. If tx_use_dsin is High, this port supplied a data stream to be transmitted. The data stream supplied on this port depends on the SDI mode:

• Dual link HD-SDI or 3G-SDI level B-DL: C data stream of link B.

• 3G-SDI level B-DS: C data stream of HD-SDI signal 2.


tx_ce_align_err Out 1

This output indicates problems with the 5/6/5/6 clock cycle cadence on the tx_ce clock enable in SD-SDI mode. In SD-SDI mode, the tx_ce signal must follow a regular 5/6/5/6 clock cycle cadence. If it does not, the SD-SDI bitstream is formed incorrectly. The tx_ce_align_err signal goes High if the cadence is incorrect. This port is only valid in SD-SDI mode.

tx_slew Out 1

This output port can drive the slew rate control pin of the external SDI cable driver to correctly switch it between slow slew rate for SD-SDI and high slew rate for HD-SDI and 3G-SDI.

GTX Transceiver Ports

gtx_rxresetdone In 1 Connect this port to the RXRESETDONE port of the GTX transceiver.

gtx_rxbufstatus2 In 1 Connect this port to bit 2 of the RXBUFSTATUS_OUT port of the GTX transceiver.

gtx_rxratedone In 1Connect this port to the RXRATEDONE_OUT port of the GTX transceiver.

gtx_rxcdrreset Out 1Connect this port to the RXCDRRESET_IN port of the GTX transceiver.

gtx_rxbufreset Out 1Connect this port to the RXBUFRESET_IN port of the GTX transceiver.

gtx_rxrate Out 2Connect this port to the RXRATE_IN port of the GTX transceiver.






gtx_rxdata In 20Connect this port to the RXDATA_OUT port of the GTX transceiver.

gtx_txreset_in In 1

Asserting this input High causes the gtx_txreset port to be asserted High, resetting the PCS portion of the GTX transmitter. This input should be kept Low for normal operation.

gtx_txresetdone In 1Connect this port to the TXRESETDONE_OUT port of the GTX transceiver.

gtx_txbufstatus1 In 1Connect this port to bit 1 of the TXBUFSTATUS_OUT port of the GTX transceiver.

gtx_txplllkdet In 1Connect this port to the TXPLLLKDET_OUT port of the GTX transceiver.

gtx_txreset Out 1Connect this port to the TXRESET_IN port of the GTX transceiver.

gtx_txdata Out 20Connect this port to the TXDATA_IN port of the GTX transceiver.

gtx_gtxtest Out 13Connect this port to the GTXTEST_IN port of the GTX transceiver.

gtx_drpclk In 1

This clock input must be driven by the same clock that drives the DCLK port of the GTX transceiver. This clock must meet the DRP clock frequency requirements listed in DS152, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics. Because the drpclk is also used internally by the receiver SDI bit rate detector, the drpclk frequency must be a fixed-frequency clock. It must not change frequencies when the SDI bit rate changes. Also, the frequency of this clock must match the value of the DRPCLK_FREQ parameter/generic of the Triple-Rate SDI core.

gtx_drpdo In 16Connect this port to the DRPDO_OUT port of the GTX transceiver.

gtx_drdy In 1Connect this port to the DRDY_OUT port of the GTX transceiver.

gtx_daddr Out 8Connect this port to the DADDR_IN port of the GTX transceiver.

gtx_di Out 16Connect this port to the DI_IN port of the GTX transceiver.

gtx_den Out 1Connect this port to the DEN_IN port of the GTX transceiver.

gtx_dwe Out 1Connect this port to the DWE_IN port of the GTX transceiver.



http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf




Reference ClocksA single GTX receiver reference clock frequency is required for the receive side of the Triple-Rate core to receive 270 Mb/s SD-SDI, both HD-SDI bit rates, and both 3G-SDI bit rates. This frequency must be between 74.1758 MHz and 74.25 MHz or between 148.3516 MHz and 148.5 MHz.

The GTX transmitter also requires a reference clock. Depending on the application, this can be the same reference clock as the GTX receiver reference clock, but usually it is separate. The GTX transmitter always transmits at an exact multiple of the GTX transmitter reference clock frequency. So, to support the two bit rates of HD-SDI and 3G-SDI, two different reference clock frequencies are required. These frequencies are either 74.25/1.001 MHz and 74.25 MHz or 148.5/1.001 MHz and 148.5 MHz. To transmit SD-SDI, the GTX transmitter reference clock frequency must be 74.25 MHz or 148.5 MHz.

When implementing multiple SDI interfaces in one FPGA, the same RX reference clock source is usually provided to all of GTX transceivers implementing SDI receiver interfaces. Because a single reference clock frequency allows reception of any of the supported SDI bit rates, all SDI interfaces clocked by a common RX reference clock frequency are fully independent and each can receive different SDI bit rates. When implementing multiple transmitters, each GTX transceiver can require its own, individual GTX transmitter reference clock to allow it to be fully independent of the other SDI transmitters in the FPGA. However, some applications, especially genlocked applications, often can use just a single TX reference clock, as well.

The reference clock frequencies used in an application are specified in the Virtex-6 FPGA GTX Transceiver Wizard. When the hd sdi protocol template is chosen, the line rate is automatically set to 1.485 Gb/s. The user can set the reference clock frequency to either 74.25 MHz or 148.5 MHz. Choosing either of these frequencies still allows the slower 74.25/1.001 and 148.5/1.001 MHz reference clock frequencies to be used.

DRP ClockThe DRP clock is used to clock transfers on the DRP interface between the GTX transceiver and the Virtex-6 FPGA Triple-Rate SDI core. The frequency of this clock must, therefore, meet the frequency requirements specified for the GTX transceiver’s DCLK as specified in DS152, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics.

The Triple-Rate SDI core also uses the DRP clock for two other purposes. First, the Triple-Rate SDI core uses the DRP clock as a reference clock frequency for the receive bit rate detector. The number of pulses of RXRECCLK are counted for a given number of cycles of the DRP clock, and the results are used to determine which bit rate is being received. Furthermore, the bit rate detector also determines if RXRECCLK is running at a

rx_mode_test In 2This port is used during verification tests of the Triple-Rate SDI core. Always wire both bits of this port Low.

test In 3This port is used during verification tests of the Triple-Rate SDI core. Always wire all bits of this port Low.





DRP Clock

frequency that is within normal ranges. If it is not, then the Triple-Rate SDI core periodically asserts the CDRRESET_IN port of the GTX transceiver.

Second, the Triple-Rate SDI core uses the DRP clock as a free-running clock to time and control important initialization and reset sequences for the GTX transmitter. These sequences cause the TXOUTCLK of the GTX transmitter to stop, thus the Triple-Rate SDI core cannot use the tx_usrclk signal, usually driven by TXOUTCLK, to control these initialization and reset sequences. It must use an independent free-running clock, so the DRP clock is used.

Both applications require that the Triple-Rate SDI core know the frequency of the DRP clock. A parameter called DRPCLK_FREQ is used to tell the Triple-Rate SDI core the frequency of the DRP clock in Hz. It is essential that this parameter accurately reflects the actual frequency of the DRP clock to within about ±100 ppm. The CORE Generator™ wizard for the Triple-Rate SDI core allows the user to specify the frequency of the DRP clock and sets the DRPCLK_FREQ parameter automatically.

The frequency of the DRP clock does not have to be related to any video frequency or to the frequency of rx_usrclk or tx_usrclk. To get an acceptable resolution for the bit rate detector, it is recommended that the frequency of the DRP clock be at least 10 MHz. So, any clock frequency between 10 MHz and the highest supported GTX DCLK frequency is allowed for the DRP clock. One global DRP clock can be used for all Virtex-6 FPGA Triple-Rate SDI cores in the same FPGA.






Chapter 4

Triple-Rate SDI Receiver Operation

Triple-Rate SDI Receiver OverviewThe triple-rate SDI receiver has these features:

• A single reference clock frequency is required to receive the five supported bit rates:

• 270 Mb/s SD-SDI

• 1.485 Gb/s HD-SDI

• 1.485/1.001 Gb/s HD-SDI

• 2.97 Gb/s 3G-SDI

• 2.97/1.001 Gb/s 3G-SDI

The other SD-SDI bit rates can also be received using the same reference clock frequency. However, this requires modifications to the triple-rate SDI receiver reference design.

• The receiver has a bit rate detector that determines whether the SDI bit rate is 1.485 Gb/s or 1.485/1.001 Gb/s in HD-SDI mode, or 2.97 Gb/s and 2.97/1.001 Gb/s in 3G-SDI mode. An output signal from the receiver indicates which bit rate is being received.

• The receiver automatically detects the SDI standard of the input signal (3G-SDI, HD-SDI, or SD-SDI) and reports the current SDI mode on an output port.

• The receiver detects and reports the video transport format (for example, 1080p 30 Hz or 1080i 50 Hz) for HD-SDI and 3G-SDI modes.

• The receiver supports 3G-SDI level A and level B formats, and automatically detects whether 3G-SDI data streams are level A or B. The 3G-SDI level is reported on an output port.

• The receiver performs CRC error checking for HD-SDI and 3G-SDI modes.

• Optional EDH error checking for the SD-SDI format is available. The optional EDH processor also includes an SD-SDI flywheel, an SD-SDI locked detector, and a video format (NTSC or PAL) detector.

• Line numbers are captured and output from the triple-rate SDI receiver. For the 3G-SDI level B format, line numbers are captured for each of the two HD-SDI streams carried on the 3G-SDI interface.

• SMPTE ST 352 video payload ID packets are captured for all SDI modes. The captured ST 352 packet data is available on output ports for one or two data streams (for those formats that require ST 352 packets in both streams).

• The receiver datapath interfaces with a 20-bit GTX receiver RXDATA port to minimize global clocking resources. A single global or regional clock is required for the receiver, which is driven by the RXRECCLK of the GTX receiver. No mixed-mode clock



Chapter 4: Triple-Rate SDI Receiver Operation

managers (MMCMs) are required. (A separate DRP clock is required, but this clock can be shared by all GTX transceivers.)

• All ancillary data embedded in the SDI data streams is preserved and output from the receiver on the video data stream outputs.

The GTX receiver takes in the serial bitstream from an external SDI cable equalizer. It automatically determines whether the SDI signal is HD-SDI, 3G-SDI, or SD-SDI by sequentially trying to lock to the incoming signal in each of these modes until the receiver recognizes that good data is received. During this search process, the rx_mode_locked output is Low. When the receiver determines it has locked to the signal, the rx_mode_locked output goes High, and the rx_mode and rx_mode_HD, rx_mode_3G, and rx_mode_SD outputs indicate in which SDI mode the receiver is operating.

Bit Rate and Transport Format DetectionThe triple-rate SDI receiver has an automatic transport format detector. This function examines the timing of the video signals in the SDI data streams and determines which video format they are. The operation of this function is independent of and not dependent on ST 352 video payload ID (VPID) packets. This function determines the transport format, not the picture format. Usually these are the same, but not always. For example, when 1080p 60 Hz video is transported on 3G-SDI level B-DL, the video transport is actually 1080i 60 Hz—the transport is interlaced, but the picture is progressive.

The rx_t_family output port provides a 4-bit code that indicates to which video format family the transport timing corresponds. Table 4-1 shows the encoding of this output port. The transport detection unit also determines whether transport is interlaced or progressive and reports this information on the rx_t_scan output port.

The transport detector also determines the bit rate of the SDI signal and the frame rate of the transport signal. The rx_bit_rate output is valid in HD-SDI and 3G-SDI modes and indicates whether the incoming bit rate is 1.485 Gb/s or 1.485/1.001 Gb/s in HD-SDI mode or 2.97 Gb/s or 2.97/1.001 Gb/s in 3G-SDI mode. The rx_t_rate port indicates the frame of the transport signal as shown in Table 4-2. The encoding of the frame rate matches the encoding used in the picture rate field of SMPTE ST 352 VPID packets; however, the rx_t_rate shows the transport frame rate, not the picture rate. The rx_t_rate port value is always the frame rate, even for interlaced transports.

Table 4-1: rx_t_family Encoding

rx_t_family Transport Video Format Active Pixels

0000 SMPTE ST 274 1920 x 1080

0001 SMPTE ST 296 1280 x 720

0010 SMPTE 2048-2 2048 x 1080

0011 SMPTE 295 1920 x 1080

1000 NTSC 720 x 486

1001 PAL 720 x 576

1111 Unknown

Others Reserved



Operation of the Triple-Rate SDI Receiver in the Various SDI Modes

The transport format detector can take up to two video frames to identify the transport format after the receiver locks to the SDI signal. It takes even longer for the rx_t_rate port to be correct. The rx_t_rate value is determined by a combination of the transport timing and the rx_bit_rate signal. The rx_bit_rate signal is determined by comparing the frequency of rx_usrclk to the frequency of drpclk. It takes approximately 0.1 seconds, after the SDI receiver is locked to the SDI signal, before the rx_bit_rate and rx_t_rate signals are accurate. Because the transport format detector reacts faster than the bit rate detector, the rx_t_rate port might initially change to a value of 60 Hz, for example, and then within 0.1 seconds change to a value of 59.94 Hz as the bit rate detector determines that the SDI bit rate is 1.485/1.001 Gb/s instead of 1.485 Gb/s.

The bit rate detection function that generates the rx_bit_rate signal also serves to verify that the frequency of rx_usrclk is within expected norms. If the bit rate detector determines that the rx_usrclk frequency is outside of the expected normal values, it asserts the gtx_cdrreset signal to reset the CDR block of the GTX receiver. This operation depends on the frequency of the reference clock (drpclk) matching the DRPCLK_FREQ generic/parameter. If the frequency of drpclk does not match the DRPCLK_FREQ value, the bit rate detector does not function correctly and frequently resets the CDR.

Operation of the Triple-Rate SDI Receiver in the Various SDI ModesThe triple-rate SDI receiver automatically determines the standard of the incoming SDI mode (SD-SDI, HD-SDI, 3G-SDI level A, or 3G-SDI level B) by sequentially trying to lock to each SDI mode until it finds the correct SDI mode. When locked to the correct SDI mode, the receiver configures itself for correct operation in that mode. The recovered clock frequency and the number and data rate of the output data streams depend on the SDI mode.

Table 4-2: rx_t_rate Encoding

rx_t_rate Frame Rate

0000 None

0010 23.98 Hz

0011 24 Hz

0100 47.95 Hz

0101 25 Hz

0110 29.97 Hz

0111 30 Hz

1000 48 Hz

1001 50 Hz

1010 59.94 Hz

1011 60 Hz

Others Reserved




Triple-Rate SDI Receiver ClockingThe GTX receiver’s CDR block requires a reference clock, which can be either 74.25 MHz or 74.25/1.001 MHz. Some integer multiples of these frequencies are also supported. In particular, 148.5 MHz and 148.5/1.001 MHz are also commonly used. Only a single reference clock frequency is required to support SD-SDI at 270 Mb/s, HD-SDI at both bit rates, and 3G-SDI at both bit rates. The frequency of the reference clock should not change. Any change in the reference clock frequency requires that the GTX receiver, including the RX PMA PLL, be reset.

The GTX receiver recovers a clock in 3G-SDI and HD-SDI modes, but not in SD-SDI mode. The recovered clock from the GTX transceiver is output on the RXRECCLK port. The frequency of the recovered clock depends on the current SDI mode of the receiver. In HD-SDI mode, it is 74.25 MHz or 74.25/1.001 MHz. In 3G-SDI mode, it is 148.5 MHz or 148.5/1.001 MHz. In SD-SDI mode, the CDR block is locked to the reference clock, and RXRECCLK is either 148.5 MHz or 148.5/1.001 MHz, depending on the frequency of the reference clock.

The RXRECCLK output of the GTX receiver should be buffered by a global or regional clock buffer. The output of this clock buffer must drive the RXUSRCLK2 input of the GTX receiver and the rx_usrclk input of the Virtex-6 FPGA Triple-Rate SDI core. It can also be used to drive any additional downstream modules that need to be clocked by the recovered clock.

Internally, most of the logic in the triple-rate SDI receiver runs at the recovered clock frequency for HD-SDI and 3G-SDI modes (some portions run at half the recovered clock frequency in 3G-SDI level B mode). For SD-SDI mode, the internal data rate is 27 MHz. Clock enables are used in the triple-rate SDI receiver to run the various sections at the proper rates when the data rate is different from the clock frequency.

The Triple-Rate SDI core supplies one SD-SDI clock enable on the rx_ce_sd output port. This clock enable can be used, in conjunction with the recovered clock, to clock logic downstream from the Triple-Rate SDI core at the 27 MHz SD-SDI data rate.

The rx_ce_sd signal is High in all modes except SD-SDI. In SD-SDI mode, this is a 27 MHz clock enable. See SD-SDI RX Operation for more details.

The Triple-Rate SDI core also outputs an rx_dout_rdy_3G data ready signal. In 3G-SDI level B mode, rx_dout_rdy_3G toggles at half the recovered clock frequency because the output data rate is 74.25 MHz, while the clock frequency is 148.5 MHz. In all modes except 3G-SDI level B, rx_dout_rdy_3G is always High.

The rx_ce_sd clock enable signal can be used as a clock enable to those datapaths that only operate at the SD-SDI data rate. The rx_dout_rdy_3G signal can be used as a clock enable to those datapaths that operate in HD-SDI and 3G-SDI modes, but not in SD-SDI mode. If a datapath must operate correctly in all three SDI modes, it should use a clock enable that is the AND of the rx_ce_sd signal and the rx_dout_rdy_3G signal.

SD-SDI RX OperationWhen the triple-rate SDI receiver is operating in SD-SDI mode, the frequency of the GTX RXRECCLK is 148.5 MHz or 148.5/1.001 MHz, depending on the reference clock frequency. The recovered SD-SDI data stream is output on the rx_ds1a port with the Y and C components interleaved at a 27 MHz data rate. The timing signals rx_trs, rx_eav, and rx_sav are valid.




In SD-SDI mode, RXRECCLK is not a recovered clock because the GTX receiver is locked to the reference clock and asynchronously samples the input bitstream. RXRECCLK is an integer multiple of the reference clock supplied to the GTX receiver.

A data recovery unit (DRU) in the triple-rate SDI receiver recovers the actual data stream from the oversampled data. The DRU asserts a data ready signal when it has a 10-bit data word ready. The Virtex-6 FPGA Triple-Rate SDI core outputs this data ready signal on the rx_ce_sd output. On average, this output is asserted every 5.5 clock cycles by using a 5/6/5/6 clock cycle cadence. The output cadence is occasionally altered when the DRU needs to catch up to the actual data rate. This occurs because the GTX transceiver reference clock is a local clock, and is asynchronous to the actual timing of the incoming SD-SDI bitstream. High amounts of jitter on the SD-SDI can also cause the cadence to vary.

Figure 4-1 shows the timing of the SD video and timing signals output by the triple_sdi_rx_20b_v6gtx module. The outputs only change on the rising edge of rx_usrclk, when rx_ce_sd is High. The timing of the EAV sequence is shown in Figure 4-1. The rx_sav output signal has the same timing as the rx_eav signal, except that it is asserted during SAV sequences.

Figure 4-2 is a screen capture from an oscilloscope showing the 27 MHz rx_ce_sd output of the Virtex-6 FPGA Triple-Rate SDI core. The oscilloscope is triggered on the rising edge of rx_ce_sd at the center of the screen. The oscilloscope is in infinite persistence mode, and the waveform was allowed to accumulate for several minutes. The waveform is colored with red indicating the most common position of the signal and blue indicating the least common. The incoming SD-SDI signal used to create this screen capture was asynchronous to the local reference clock used by the SDI receiver.


Figure 4-1: SD-SDI RX Timing Diagram

rx_usrclk(148.5 MHz)

rx_ce_sd

rx_ds1a

rx_trs

rx_eav

3FFY’(719) 000 XYZ CB’(361)

6 Clocks

UG823_c4_01_032411

6 Clocks 5 Clocks5 Clocks




The rx_ce_sd pulses on either side of the center pulse are always five or six clock cycles away from the center pulse because of the 5/6/5/6 cadence of the rx_ce_sd signal. The clock referred to in the previous sentence is the reference clock to the GTX receiver, a local clock asynchronous to the input SD-SDI signal. In SD-SDI mode because the CDR block of the GTX receiver is locked to this reference clock, the RXRECCLK output of the GTX receiver used to clock the DRU and produce the rx_ce_sd signal is frequency-locked to this same reference clock.

The two pulses at the far right and far left of the trace are nominally 11 clock cycles from the center pulse because of the 5/6/5/6 cadence. The nominal position is marked by the yellow and red pulse. For the far-right pulse, the dashed yellow vertical cursor marks the position that is 11 clock cycles from the rising edge of the center pulse. The nominal location of the central yellow/red pulses are surrounded on either side by blue pulses, indicating that, occasionally, the DRU needs to make the period of the rx_ce_sd cycle either 10 clock cycles or 12 clock cycles long to compensate for the frequency differences between the local reference clock and the incoming SD-SDI bit rate.

HD-SDI RX OperationWhen the triple-rate SDI receiver is operating in HD-SDI mode, RXRECCLK is a true recovered clock, and runs at 74.25 MHz or 74.25/1.001 MHz, depending on the HD-SDI bit rate. The Y and C data streams of the HD-SDI signal are output on the rx_ds1a and rx_ds2a ports, respectively, along with the timing signals rx_trs, rx_eav, and rx_sav. The line number is output on the rx_line_a port. In HD-SDI mode, the line number changes during the CRC0 word. Figure 4-3 shows the timing of the HD-SDI outputs.


Figure 4-2: Oscilloscope Capture of SD-SDI Clock Enable

UG823_c4_02_032411




3G-SDI Level A RX OperationWhen the triple-rate SDI receiver is operating in 3G-SDI level A mode, the frequency of RXRECCLK is 148.5 MHz or 148.5/1.001 MHz, depending on the 3G-SDI bit rate.

Figure 4-4 shows the output timing of the triple-rate SDI receiver when receiving a 1080p 50, 59.94, or 60 Hz signal in 3G-SDI level A mode. These video formats do not require further unpacking of the data streams, because rx_ds1a carries the luma component, and rx_ds2a carries the multiplexed chroma components.

Other video formats, such as 4:4:4 10-bit or 12-bit, have identical timing to that shown in Figure 4-4, but the video samples are packed as specified by the SMPTE 425 so that it takes two consecutive words on each data stream to carry a single video sample. The Virtex-6 FPGA Triple-Rate SDI core does not unpack these other video formats, but outputs the two data streams exactly as described in the 3G-SDI level A data stream mapping sections of SMPTE 425.


Figure 4-3: HD-SDI RX Timing Diagram


rx_ds1a

rx_ds2a

rx_trs

rx_eav

rx_line_a

UG823_c4_03_032411

3FFY’(n) Y’(n+1) Y’(n+10) Y’(n+11)000 XYZ LN0 LN1 CRC0 CRC1

3FFCB’(n) CR’(n) CB’(n+10) CR’(n+10)000

line(n) line(n+1)

XYZ LN0 LN1 CRC0 CRC1


Figure 4-4: 3G-SDI Level A RX Timing (1080p 50 Hz or 60 Hz)


rx_dout_rdy_3G

rx_ds1a

rx_ds2a

rx_trs

rx_eav

rx_line_a

UG823_c4_04_032411

3FFY’(1918) Y’(1919) Y’(1928) Y’(1929)000 XYZ LN0 LN1 CRC0 CRC1

line(n) line(n+1)

3FFCB’(1918) CR’(1918) CB’(1928) CR’(1928)000 XYZ LN0 LN1 CRC0 CRC1




3G-SDI Level B RX OperationWhen the triple-rate SDI receiver is operating in 3G-SDI level B mode, the frequency of RXRECCLK is 148.5 MHz or 148.5/1.001 MHz, depending on the 3G-SDI bit rate. However, in this mode, there are four 10-bit data streams output by the triple-rate SDI receiver. The data rate of these data streams is half the frequency of RXRECCLK; therefore, the rx_dout_rdy_3G signal is asserted every other clock cycle, and acts as a clock enable.

Both line number output ports are active. When the level B signal is transporting SMPTE 372 dual link data streams (level B-DL), the values on both rx_line_a and rx_line_b are identical and indicate the interface line number, not the picture line number. When the level B signal is transporting two independent HD-SDI signals, the two line number values are not necessarily the same, depending on whether the two HD-SDI signals are frame-locked or not. The rx_line_a and rx_line_b ports, not shown in Figure 4-5, change at the same relative position as they do for 3G-SDI level A and HD-SDI, as the CRC0 word is output on the data streams.

When the 3G-SDI level B signal carries SMPTE 372 dual link data streams, the link A data streams are output on rx_ds1a and rx_ds2a, and the link B data streams are output on rx_ds1b and rx_ds2b. These four links carry video mapped as required by SMPTE 372. The triple-rate SDI receiver does not unpack the data streams into video, but outputs them as SMPTE 372 data streams.

When the 3G-SDI level B signal carries two independent HD-SDI streams (level B-DS), the first HD-SDI stream is output with the luma component on rx_ds1a and the multiplexed chroma components on rx_ds2a. The second HD-SDI stream is output with the luma component on rx_ds1b and the multiplexed chroma component on rx_ds2b. These two HD-SDI streams are horizontally synchronized such that their EAVs and SAVs always line up exactly, therefore there is only a single set of rx_eav, rx_sav, and rx_trs timing signals.

Figure 4-5 shows the output timing of the triple-rate SDI receiver when receiving a 3G-SDI level B signal.


Figure 4-5: 3G-SDI Level B RX Timing


Link A

Link B

rx_dout_rdy_3G

rx_ds1a

rx_ds2a

rx_ds1b

rx_ds2b

rx_trs

rx_eav

UG823_c4_05_032411

3FFY’(1918) Y’(1919) 000 XYZ LN0

3FFCB’(1918) CR’(1918) 000 XYZ LN0

3FFY’(1918) Y’(1919) 000 XYZ LN0

3FFCB’(1918) CR’(1918) 000 XYZ LN0



Electrical Interface

Electrical InterfaceThe GTX receiver must be connected to the SDI connector through an SDI cable equalizer. The equalizer serves two purposes. It equalizes the SDI signal to compensate for signal distortion and attenuation, and it converts the single-ended 75Ω SDI signal to a differential signal compatible with the GTX receiver input. Any industry-standard SDI cable equalizer can be used, such as those from National Semiconductor and Gennum.

Most, if not all, SDI cable equalizers currently available do not have a common mode output voltage directly compatible with the GTX transceiver inputs. Therefore AC coupling is required to shift the common mode voltage of the signal as it enters the GTX receiver. The GTX receiver has built-in AC coupling, but these internal capacitors are not adequate to support the long run lengths of the SDI signals. The internal AC coupling must be bypassed and external AC coupling capacitors must be used. The value of these external capacitors is usually about 4.7 µF. Nothing else needs to be done to set the common mode voltage, because the GTX receiver provides a correct termination voltage to set the common mode voltage on its inputs. The user must follow the recommendations of the cable equalizer manufacturer for interfacing the cable equalizer to the BNC cable.

When a GTX transceiver wrapper is created using the hd sdi protocol template, the wrapper is configured correctly to bypass the internal AC coupling capacitors and to properly terminate the receiver inputs for use with external AC coupling capacitors.

Other Triple-Rate SDI RX Design Considerations

Dual Link HD-SDITo implement a dual link HD-SDI receiver, two triple-rate SDI receivers are paired together with one receiving link A and the other receiving link B. Typically, the received data streams for the two links are skewed, so the application must remove the skew. The data streams can then be unpacked into video streams, if desired.

Deskewing the data streams involves watching the EAV or SAV signals from each link, and delaying the data streams of the link whose EAV becomes asserted first by an appropriate amount to match the timing of the other link. The Virtex®-6 FPGA SRLC32E elements make perfect delay devices for implementing this deskew function. Prior to 2011, the SMPTE ST 372 specification stated that the maximum skew between the two links at the output of the transmitters must not exceed 40 ns. However, it is common in the industry for dual link HD-SDI transmitters to have much more skew between the two links than this. The ST 372 specification now states that the skew between the links can be as high as 500 ns.

Processing Embedded Audio and Other Ancillary DataThe output data streams from the triple-rate SDI receiver always have all ancillary data, including embedded audio packets, intact. Modules designed to process ancillary data can be connected to the data streams, clock enables, and other timing signals output by the triple-rate SDI receiver.

SMPTE 352 Video Payload ID PacketsThe triple-rate SDI receiver module captures SMPTE 352 packets present in the data streams for all SDI modes. For SD-SDI and HD-SDI modes, the four data bytes of the SMPTE 352 packet are output on the rx_a_vpid port. The rx_a_vpid_valid port indicates




when valid SMPTE 352 packets have been captured. This output has some hysteresis so that SMPTE 352 packets can be missing from a few fields or frames before the valid signal is negated. During the time that the valid output is asserted and new SMPTE 352 packets are not found, the data from the last valid SMPTE 352 packet received is output on the rx_a_vpid port.

The 3G-SDI standard requires SMPTE 352 packets in both data streams. The triple-rate SDI receiver captures the SMPTE 352 packets from both streams, outputting the data from the packet in data stream 1 on rx_a_vpid, and the data from the packet in data stream 2 on rx_b_vpid. The module also supplies individual rx_a_vpid_valid and rx_b_vpid_valid outputs.

SD-SDI EDH Error DetectionThe triple-rate SDI receiver contains an EDH processor that checks the SD-SDI signal for errors. This EDH processor does not update EDH packets in the SD-SDI stream. It simply reports any errors found and also captures the error flags from each EDH packet.

The EDH processor has a 16-bit counter that counts the number of fields with errors. The current error count is output on the rx_edh_errcnt port. The counter can be cleared by asserting rx_edh_clr_errcnt High. The user can specify which types of errors are counted by this counter using the rx_edh_errcnt_en input port. This port has 16 unary bits that enable and disable 16 different error types. Any bit that is High enables the corresponding error. When this type of error is detected, the error counter increments. Any bit that is Low disables the corresponding error. Table 4-3 shows the encoding of the bits on the rx_edh_errcnt_en port.

Table 4-3: Encoding of rx_edh_errcnt_en

Bit # Error

0 ANC EDH error

1 ANC EDA error

2 ANC IDH error

3 ANC IDA error

4 ANC UES error

5 FF EDH error

6 FF EDA error

7 FF IDH error

8 FF IDA error

9 FF UES error

10 AP EDH error

11 AP EDA error

12 AP IDH error

13 AP IDA error

14 AP UES error

15 EDH packet checksum error




The ANC error conditions occur when there are errors in the ancillary data packets. The FF error conditions occur when there are errors in the full field. The AP error conditions occur when there are errors in the active portion of the picture. The EDH packet checksum error indicates a checksum error was found within the EDH packet itself.

Each ANC, FF, and AP error condition set has five individual error flags. All flags are asserted High to indicate an error condition.

• EDH error: This error condition occurs when the EDH processor detects a CRC error (checksum error for ANC packets) in a field.

• EDA error: This error condition occurs when the EDA or EDH flags of the received EDH packet are asserted.

• IDH error: This error condition is not supported.

• IDA error: This error condition occurs when the IDA or IDH flags of the received EDH packet are asserted.

• UES error: This error condition occurs when the UES flag in the received EDH packet is asserted.

The actively computed EDH errors for the ANC, AP, and FF are also output on the rx_edh_anc, rx_edh_ap, and rx_edh_ff ports, respectively. Thus, the rx_edh_anc port is asserted whenever a checksum error is detected in an ancillary data packet. The rx_edh_ap port is asserted when the calculated active picture CRC does not match the AP CRC in the EDH packet. The rx_edh_ff port is asserted when the calculated full field CRC does not match the FF CRC in the EDH packet.

The EDH processor also outputs the ANC, AP, and FF flags from the EDH packet on the rx_edh_anc_flags, rx_edh_ap_flags, and rx_edh_ff_flags ports, respectively. These output ports are exact copies of the flags found in the last received EDH packet. Thus they differ from the actively computed error conditions shown above. For example, the EDH flag (bit 0) of the rx_edh_ap_flags port indicates that the AP EDH flag is set in the last received EDH packet. However, the rx_edh_ap port indicates that the active picture CRC calculated locally by the EDH processor does not match the AP CRC value in the EDH packet. The rx_edh_anc_flags, rx_edh_ap_flags, and rx_edh_ff_flags ports are each five bits wide; the encoding is shown in Table 4-4.

The EDH processor also produces four error flags related to the format and contents of the EDH packet itself. These error flags are output on the rx_edh_packet_flags port. The encoding of this port is shown in Table 4-5.

Table 4-4: Encoding of rx_edh_anc_flags, rx_edh_ap_flags, and rx_edh_ff_flags Ports

Bit # Flag

0 EDH

1 EDA

2 IDH

3 IDA

4 UES




SD-SDI Data Recovery UnitThe triple-rate SDI receiver uses a DRU to recover the SD-SDI data. This DRU is based on the digital PLL data recovery design described in XAPP875, Dynamically Programmable DRU for High-Speed Serial I/O, but has been optimized for SD-SDI. This SD-SDI DRU has been optimized for use with 11x oversampled 270 Mb/s data. By optimizing the DRU specifically for SD-SDI, it is much smaller than the general-purpose implementation of the DRU. The SD-SDI DRU has also been optimized, so that the reference clock used for SD-SDI reception can be either 74.25 MHz (or 148.5 MHz) or 74.25/1.001 MHz (or 148.5/1.001 MHz). It performs equally well with either reference clock frequency.

It is also possible to use the full (non-optimized) version of this DRU to receive SD-SDI bit rates other than 270 Mb/s. The full version of the DRU (as described in Dynamically Programmable DRU for High-Speed Serial I/O) can perform non-integer oversampling. Therefore, with the 2.97 Gb/s sampling rate of the GTX receiver, the DRU can be set for 8.25x oversampling to receive SD-SDI at 360 Mb/s, or 5.5x oversampling, for 540 Mb/s. An SDI receiver that supports additional SD-SDI bit rates also requires modifications of the triple_sdi_rx_autorate module to make it sequentially search through these additional SD-SDI bit rates when locking to the incoming SDI signal. Such an application is beyond the scope of this document.

SD-SDI Clock RecoveryIn SD-SDI mode, the triple-rate SDI receiver does not recover a clock in the typical sense that a CDR unit does. The DRU generates a 27 MHz clock enable that is output on the rx_ce_sd port. The frequency of this clock enable represents the actual frequency of the recovered video.

For some video applications, particularly those that do not need to retransmit the recovered video over an SDI interface and do not need to interface with components external to the FPGA, the rx_ce_sd signal is often sufficient as a recovered clock. Typically, this signal is used as a clock enable to downstream modules that are clocked with the RXRECCLK from the GTX receiver. Also, the rx_ce_sd signal itself can be used as a 27 MHz clock if timing constraints are properly designed to allow for the large amount of low frequency cycle-to-cycle jitter on this signal.

If the received video data is to be retransmitted as an SD-SDI signal using a GTX transmitter, a low-jitter recovered clock is required. The recovered clock must have low enough jitter so that it can be used as a reference clock for the GTX transmitter’s PMA PLL. The frequency of the recovered clock must be 74.25 MHz or 148.5 MHz so that the GTX transmitter can use 11x oversampling to transmit the 270 Mb/s SD-SDI data. This requires the use of an external, low-bandwidth PLL. The bandwidth of the MMCM in the Virtex-6 device is too high to adequately filter out the large amounts of low-frequency jitter present on the rx_ce_sd signal from the SDI receiver. National Semiconductor LMH1982 and Silicon Labs Si5324 devices can both perform this function. Both of these devices can take

Table 4-5: Encoding of rx_edh_packet_flags Port

Bit # Error

0 EDH packet is missing

1 Parity error in user data words of EDH packet

2 Checksum error in EDH packet

3 Format error in EDH packet - such as invalid data count




in the rx_ce_sd signal as a 27 MHz reference clock and multiply it up to either 74.25 MHz or 148.5 MHz, while also filtering out the jitter. The resulting clock is suitable for use as a reference clock for the GTX transmitter.

Another alternative is to use an external genlock PLL and lock it to the video sync signals from the recovered video. The output of the genlock PLL can be used as an SD-SDI recovered clock.

A recovered clock is sometimes required to drive external video ASSP devices. In SD-SDI mode, such a clock probably needs to have a frequency of 27 MHz and have lower jitter than is present on the rx_ce_sd signal. It does not need to have very low jitter as is the case when producing a GTX transmitter reference clock. The techniques previously discussed can be used, but it might be preferable to generate such a recovered clock entirely in the FPGA without requiring external components. The jitter on the rx_ce_sd signal is too high to allow it to be used directly as a reference clock input to the Virtex-6 FPGA MMCM; however, there is a way to do this using a spare GTX transmitter as shown in Figure 4-6.

The rx_recclk_txdata output port of the Virtex-6 FPGA Triple-Rate SDI core is connected to the TXDATA port of the GTX transmitter. The GTX transmitter must use exactly the same reference clock as the GTX receiver that is receiving the SDI input signal. If the GTX transmitter is in the same transceiver with the GTX receiver that is used as the SDI receiver, power can be saved by using only the RX PMA PLL in this transceiver to supply the line-rate clock to both the transmitter and receiver sections of the GTX transceiver. The TXUSRCLK2 port of the GTX transmitter must be connected to the same clock that is driving the RXUSRCLK2 port of the GTX receiver and the rx_usrclk port of the Triple-Rate SDI core. The GTX transmitter must be configured for a line rate of 2.97 Gb/s with no encoding and with a 20-bit TXDATA port.

When configured in this manner, the serial output of the GTX transmitter is a 270 MHz clock frequency-locked to the incoming SD-SDI signal. That is, it is a true recovered clock for SD-SDI mode. The GTX transmitter serial output pins can be connected to a global or regional clock LVDS input of the Virtex-6 device, with appropriate care to properly terminate the CML outputs and translate them to LVDS. The 270 MHz clock then can be used in whatever manner is required in the FPGA. For example, it can be divided by 10 to get a 27 MHz recovered clock to drive internal or external video datapaths. The signal has low enough jitter that it can be used as a reference clock to an MMCM.

In Figure 4-6, the GTX transmitter and receiver are assumed to be in the same transceiver, and the GTX transmitter is configured to use the clock generated by the RX PMA PLL. The Virtex-6 FPGA Triple-Rate SDI core configures the GTX transmitter, through the DRP port, to be in 3G-SDI mode with a line rate of 2.97 Gb/s, because the Triple-Rate SDI core's tx_mode input port is hardwired for 3G-SDI mode.

The GTX transmitter that is generating the recovered 270 MHz clock does not have to be in the same transceiver as the GTX receiver that is receiving the SDI signal. If it is not in the same transceiver, it must use the same reference clock as the GTX receiver that is receiving the SDI signal. The Triple-Rate SDI core does not needed to configure the GTX transmitter. The GTX Transceiver Wizard can create a GTX transceiver wrapper with only a transmitter configured specifically with a 2.97 Gb/s line rate.

The DRU inside the Triple-Rate SDI core generates the data on the rx_recclk_txdata port in such a way that the GTX transmitter outputs a 270 MHz clock. It moves the edges of the clock around by plus or minus one bit time of the 2.97 Gb/s line rate to modify the frequency of the output signal to exactly match with the bit rate of the input SD-SDI signal. The cycle-to-cycle jitter on the 270 MHz clock generated by the GTX transmitter is therefore ±337 ps plus whatever jitter is inherent in the GTX transmitter output signal (1 bit time at 2.97 Gb/s is 337 ps). This is shown in Figure 4-7. The top trace is the 270 MHz clock




generated by the GTX transmitter. The scope was triggered on the rising edge of the recovered clock at the center of the screen. The ±337 ps cycle-to-cycle jitter can be seen by looking at the rising edges of the cycles on either side of the trigger point; these rising edges each have three discrete rising points.

The bottom trace in Figure 4-7 is the SD-SDI signal output by the SDI transmitter operating in pass-through mode. That is, this SD-SDI transmitter is retransmitting the SD-SDI input signal received by the SDI receiver. In this demonstration, the SD-SDI recovered clock used as the reference clock for the SDI transmitter generating the output signal shown in the bottom trace is produced by an Si5324 device locked to the rx_ce_sd signal. Therefore, the top and bottom traces are 270 MHz signals; the top one is a recovered clock generated by a GTX transmitter, and the bottom one is an SD-SDI output signal from a different GTX transmitter whose reference clock is generated by an Si5324 locked to the rx_ce_sd signal. These two signals are, therefore, generated by two different SD-SDI clock recovery schemes, but are both recovering clocks from the same input SD-SDI signal. As shown in Figure 4-7, these two clock recovery schemes generate signals that are frequency-locked to each other, although there is some low-frequency phase jitter between these two signals.

Figure 4-6 is a simplified block diagram and does not show all of the various status, control, and DRP signals going between the GTX transceiver and the Triple-Rate SDI core. These must all be connected as shown in Figure 3-1, page 18.


Figure 4-6: Using the GTX Transmitter to Generate the SD-SDI Recovered Clock

ReferenceClock

RX & TX Reference Clock

SDI In

External SDI

Cable EQ

RXPRXN

IBUFDS_GTXE1 RXRECCLK

BUFG or BUFR

RXUSRCLK2

SDI RX Outputs

RXDATA

GTXTransceiver

v_triple_sdi_v1_0

20

rx_usrclk

gtx_rxdata

22'b10

TXUSRCLK2

recclk_txdata20

TXPTXN

IBUFDS

270 MHz Recovered SD-SDI Clock

These connections are external to the FPGA.

tx_mode

tx_usrclk

TXDATA

UG823_06_032411




RXEQMIXThe GTX receiver contains two built-in equalizer functions. These equalizers are designed to equalize circuit board traces and not SDI coaxial cable lengths of 100+ meters. An external SDI cable equalizer is always required. However, the built-in equalizers in the GTX receiver can be useful for improving the integrity of the signal from the output of the SDI cable equalizer after it has traveled across the board to the input of the GTX receiver. Equally important, improper GTX receiver equalizer settings can greatly degrade the receiver jitter tolerance. Thus, the GTX receiver equalizer settings must always be set correctly to optimize the operation of an SDI receiver, and not negatively impact its performance.

The decision feedback equalizer can be completely disabled. When disabled, it does not affect the operation of the GTX receiver. However, the continuous time equalizer in the GTX receiver is always active and must be set properly. This equalizer can be controlled by the RXEQMIX port of the GTX transceiver wrapper, or it can be hardcoded to a specific value using a GTX transceiver attribute generated by the Virtex-6 FPGA GTX Transceiver Wizard when the GTX transceiver wrapper file is created. The RXEQMIX port is useful for prototyping the SDI interface and determining the best RXEQMIX setting. When the optimum setting is determined, the RXEQMIX port can be eliminated from the wrapper, and the equalizer setting hardcoded using the wizard.

Determining the best RXEQMIX setting is a trial-and-error process. For the Xilinx® ML605 board and FMC broadcast mezzanine card, HD-SDI RX jitter tolerance tests with the HD-SDI pathological patterns were conducted for each of the eight possible RXEQMIX settings to determine the best RXEQMIX setting for this particular platform. The results of


Figure 4-7: Recovered SD-SDI Clock from GTX Transmitter

UG823_c4_07_032411




these tests are shown in Figure 4-8. In this case, an RXEQMIX setting of 100 was selected as the optimum setting. The results show that a setting of 011 is the worst setting with a negative effect on the receiver jitter tolerance. It is recommended that tests of RXEQMIX be done with the SDI pathological patterns because these stress the equalizer more.


Figure 4-8: Example RXEQMIX RX Jitter Tolerance Test Results

0 0.5 1 1.5 2

Jitter Frequency (Log Scale 10 kHz to 10 MHz)

2.5 3

RXEQMIX = 000RXEQMIX = 001RXEQMIX = 010RXEQMIX = 011RXEQMIX = 100RXEQMIX = 101RXEQMIX = 110RXEQMIX = 111

3.50

0.2

0.4

0.6

Jitte

r A

mpl

itude

(U

I)

0.8

1.0

1.2

UG823_c4_08_032411



Chapter 5

Triple-Rate SDI Transmitter Operation

Triple-Rate SDI Transmitter OverviewThe triple-rate SDI transmitter has these features:

• Only two reference clock frequencies are required to support all SDI modes:

• 148.5 MHz (or 74.25 MHz) for SD-SDI at 270 Mb/s, HD-SDI at 1.485 Gb/s, and 3G-SDI at 2.97 Gb/s.

• 148.5/1.001 MHz (or 74.25/1.001 MHz) for HD-SDI at 1.485/1.001 Gb/s and 3G-SDI at 2.97/1.001 Gb/s.

• Directly supports 3G-SDI level A transmission of 1080p 50 Hz, 59.94 Hz, and 60 Hz video.

• Transmits preformatted dual link HD-SDI streams via either dual link HD-SDI or 3G-SDI level B-DL formats.

• Supports all 3G-SDI level A compatible video formats with the addition of a 3G-SDI level A mapping module (not supplied).

• Directly supports transmission of two independent HD-SDI streams in the 3G-SDI level B-DS mode.

• Generates and updates EDH packets for the SD-SDI mode.

• Generates and inserts CRC values for HD-SDI and 3G-SDI modes.

• Inserts line number words for HD-SDI and 3G-SDI modes.

• Can generate and insert ST 352M video payload ID (VPID) packets in all SDI modes.

• Interfaces with a 20-bit GTX transceiver TXDATA port to minimize global clocking resources. Only a single global clock is required for the transmitter. No MMCMs are required.

The triple-rate SDI transmitter performs two main functions. The first is insertion of ST 352 VPID packets. The second function encompasses all of the formatting that needs to be done to generate a data stream to send to the TXDATA port of a GTX transmitter.

Operation of the Triple-Rate SDI Transmitter in the SDI ModesThe SDI mode (SD-SDI, HD-SDI, 3G-SDI level A or 3G-SDI level B) of the triple-rate SDI transmitter is determined by the mode and level inputs of the transmitter datapath modules. The clock frequency requirements and the number of data streams expected by the triple-rate SDI transmitter datapath depend on the SDI mode.



Chapter 5: Triple-Rate SDI Transmitter Operation

SD-SDI Transmitter OperationWhen operating in SD-SDI mode, the TXOUTCLK signal from the GTX transmitter has a frequency of 148.5 MHz, because the transmitter runs at 11 times the 270 Mb/s bit rate. The interleaved Y/C data stream is connected to the tx_a_y_in port of the Virtex®-6 FPGA Triple-Rate SDI core. The tx_ce clock enable input of the Triple-Rate SDI core must be asserted at a 27 MHz rate, as shown in Figure 5-1. Thus they must be asserted with a 5/6/5/6 clock cycle cadence. Any other cadence of the tx_ce signal causes the SD-SDI bit replication logic to underflow or overflow. The tx_din_rdy port must always be held High in SD-SDI mode.

The tx_ce port of the Triple-Rate SDI core is three bits wide. All three bits must be driven with duplicate copies of the clock enable signal. Three separate bits are provided for loading purposes. They can all be tied together and driven by one signal; however, if the loading is so high that it is difficult to meet timing, then separate duplicate copies of the clock enable should be generated and connected to each bit of the tx_ce port.


1. All inputs except tx_ce have an entire sample time in which to become stable. Data is only sampled on the inputs on the rising edge of tx_usrclk when tx_ce is High. The sample time is the time between rising edges of tx_usrclk when tx_ce is High. As shown in Figure 5-1, the tx_ce signal must always have a 5/6/5/6 clock cycle cadence. Any other cadence underflows or overflows the SDI bit replication logic. Although Figure 5-1 shows that the first word of the EAV is a 5-clock cycle sample, no such relationship is required. The first word of the EAV could instead be a 6-clock cycle sample.

2. In SD-SDI mode, the line number value on the tx_line_a input port is only used to insert ST 352 packets. If ST 352 packet insertion is disabled (tx_insert_vpid is Low), line numbers are not required on the tx_line_a port in SD-SDI mode. When used, the line number on tx_line_a must be stable starting with the XYZ word of the EAV, and must remain valid through the entire HANC interval. The VPID data bytes also have the same timing requirements as tx_line_a.

The triple-rate SDI transmitter inserts EDH packets if insert_edh is High, and then scrambles the data and replicates each scrambled bit 11 times. The scrambled and replicated data is output on the gtx_txdata port at 148.5 MHz. The GTX transmitter serializes the data for transmission over the serial interface.


Figure 5-1: SD-SDI TX Timing

tx_usrclk (148.5 MHz)

tx_ce

tx_din_rdy

tx_a_y_in

tx_line_a

VPID bytes

3FFY’(719) 000 XYZ

EAV

Line Number

VPID UserData Words

CB’(361)

UG823_c5_01_032411

6 Clocks6 Clocks 5 Clocks5 Clocks



Operation of the Triple-Rate SDI Transmitter in the SDI Modes

HD-SDI Transmitter OperationWhen operating in HD-SDI mode, the frequency of the TXOUTCLK from the GTX transmitter is 74.25 MHz or 74.25/1.001 MHz. The tx_ce and tx_din_rdy input ports must always be High. Figure 5-2 shows the timing of the input signals for HD-SDI mode.

Data enters the Virtex-6 FPGA Triple-Rate SDI core as two 10-bit data streams with the Y data stream on the tx_a_y_in port and the C data stream on the tx_a_c_in port. The input data rate is 74.25 MHz or 74.25/1.001 MHz. If the tx_insert_vpid input is High, ST 352 packets are inserted.

The Triple-Rate SDI core inserts line numbers into both data streams immediately after the EAV, if tx_insert_ln is High. It calculates and inserts CRC values immediately after the line numbers if tx_insert_crc is High. It scrambles the data streams and outputs one 20-bit data stream running at 74.25 MHz or 74.25/1.001 MHz on the gtx_txdata output port. The GTX transmitter serializes the data for transmissions over the serial interface.

Line numbers must be supplied on the tx_line_a port if either SMPTE 352 packet insertion or line number insertion is enabled.


1. In HD-SDI mode, the line number value on the tx_line_a input port must be stable starting with the XYZ word of the EAV, and must remain valid through the entire HANC interval.

2. The VPID input bytes must be stable beginning with the XYZ word of the EAV, and must remain stable during the entire HANC interval on lines where SMPTE 352 packets are inserted.

3G-SDI Transmitter OperationWhen operating in 3G-SDI mode, the transmitter can operate in level A mode or level B mode, as selected by the tx_level_b_3G input (level A = Low, level B = High).


Figure 5-2: HD-SDI TX Timing

EAV

Line Number

VPID User Data Words

tx_ce

tx_din_rdy

tx_a_y_in

tx_a_c_in

tx_line_a

VPID bytes

UG823_c4_02_032411

Y’(n) Y’(n+1) 3FF 000 XYZ Y’(n+6) Y’(n+7) Y’(n+8) Y’(n+9) Y’(n+10) Y’(n+11)

CB’(n) CR’(n) 3FF 000 XYZ CB’(n+6) CR’(n+6) CB’(n+8) CR’(n+8) CB’(n+10) CR’(n+10)

tx_usrclk(74.25 MHz)




Level A Mode

In 3G-SDI level A mode, the Virtex-6 FPGA Triple-Rate SDI core requires two 10-bit data streams on the tx_a_y_in (data stream 1) and tx_a_c_in (data stream 2) input ports. The clock frequency is 148.5 MHz or 148.5/1.001 MHz. The tx_ce and tx_din_rdy inputs must always be High. For 1080p 50 Hz, 59.94 Hz, and 60 Hz, the Y component data stream is input on the tx_a_y_in port, and the C component data stream is input on the tx_a_y_in port. For all other video formats, the video must be mapped to the two SDI data streams before they go into the Triple-Rate SDI core.

Figure 5-3 shows the timing of the inputs signals for 3G-SDI level A mode.


1. In 3G-SDI level A mode, the line number value on the tx_line_a input port must be stable starting with the XYZ word of the EAV, and must remain valid through the entire HANC interval.

2. The VPID input bytes must be stable beginning with the XYZ word of the EAV, and must remain stable during the entire HANC interval on lines where SMPTE 352 packets are inserted.

The Triple-Rate SDI core inserts SMPTE 352 packets into both data streams, before outputting the data streams on the tx_ds1a_out and tx_ds2a_out output ports or, if tx_user_dsin_is Low, routing these data streams to the rest of the transmitter. The triple-rate SDI transmitter inserts the line number on the tx_line_a port into both data streams immediately after the EAV, if tx_insert_ln is High. It calculates and inserts CRC values immediately after the line numbers, if tx_insert_crc is High. It scrambles the data streams and outputs one 20-bit data stream running at 148.5 MHz on the tx_txdata output port. The GTX transmitter serializes the data for transmission over the serial interface.

Line numbers are required on the tx_line_a port if either ST 352 packet insertion or line number insertion is enabled.


Figure 5-3: 3G-SDI Level A TX Timing

EAV

Line Number


tx_ce

tx_din_rdy

tx_a_y_in

tx_a_c_in

tx_line_a

VPID bytes

UG823_c5_03_032411

Y’(n) Y’(n+1) 3FF 000 XYZ Y’(n+6) Y’(n+7) Y’(n+8) Y’(n+9) Y’(n+10) Y’(n+11)

CB’(n) CR’(n) 3FF 000 XYZ CB’(n+6) CR’(n+6) CB’(n+8) CR’(n+8) CB’(n+10) CR’(n+10)




Operation of the Triple-Rate SDI Transmitter in the SDI Modes

Level B Mode

Operation of the triple-rate SDI transmitter is the same for 3G-SDI level B-DL and level B-DS. When running in 3G-SDI level B mode, the Virtex-6 FPGA Triple-Rate SDI core requires four 10-bit data streams on its tx_a_y_in (Y channel of link A), tx_a_c_in (C channel of link A), tx_b_y_in (Y channel of link B), and tx_b_c_in (C channel of link B) ports. These four data streams must be ST 372 dual link HD-SDI data streams for level B-DL, or two independent HD-SDI streams that are to be combined onto a single 3G-SDI signal for level B-DS. The clock frequency is 148.5 MHz or 148.5/1.001 MHz, therefore the transmitter must be clocked every other clock cycle in 3G-SDI level B mode, as shown in Figure 5-4. The tx_ce signal cannot be used to cause the triple-rate SDI transmitter to clock every other clock cycle in 3G-SDI mode. The tx_ce signal is only used for SD-SDI mode. For 3G-SDI mode, tx_din_rdy must be used. Thus, in 3G-SDI B mode, the correct way to control the data rate of the triple-rate SDI transmitter is to keep tx_ce High and toggle the tx_din_rdy signal every other clock cycle as shown in Figure 5-4.


1. In 3G-SDI mode, the line number values on the tx_line_a and tx_line_b input ports must be stable starting with the XYZ word of the EAV, and must remain valid through the entire HANC interval.

2. The VPID input bytes must be stable beginning with the XYZ word of the EAV, and must remain stable during the entire HANC interval on lines where ST 352 packets are inserted.

The triple-rate SDI transmitter inserts ST 352 VPID packets in the Y data streams of both link A and link B. The four data streams are output on the tx_ds1a_out, tx_ds2a_out, tx_ds1b_out, and tx_ds2b_out ports or routed directly to the rest of the transmitter if tx_use_din is Low.


Figure 5-4: 3G-SDI Level B TX Timing

EAV

Line Number


tx_ce

tx_din_rdy

tx_a_y_in

tx_a_c_in

tx_b_y_in

tx_b_c_in

tx_line_a/tx_line_b

VPID bytes

UG823_c5_04_032411

Y’(n) Y’(n+1) 3FF 000 XYZ Y’(n+6)

CB’(n) CR’(n) 3FF 000 XYZ CB’(n+6)

Y’(n) Y’(n+1) 3FF 000 XYZ Y’(n+6)

CB’(n) CR’(n) 3FF 000 XYZ CB’(n+6)





If tx_insert_ln is High, the transmitter inserts line numbers into all four data streams. If tx_insert_crc is High, it calculates and inserts CRC values immediately after the line numbers in all four data streams. The data streams are then interleaved to produce a single 20-bit data stream running at 148.5 MHz or 148.5/1.001 MHz on the gtx_txdata output port. The GTX transmitter serializes the data for transmission over the serial interface.

If ST 352 packets are to be inserted, line numbers are required on both the tx_line_a (for link A) and tx_line_b (for link B) input ports. ST 352 packets are mandatory for 3G-SDI mode. If line number insertion is enabled, line numbers are also required on the tx_line_a and tx_line_b ports. Two different line number ports are provided to support 3G-SDI level B-DS where the two independent HD-SDI signals being carried on the 3G-SDI interface might not be vertically synchronized. For 3G-SDI level B-DL mode tx_line_a and tx_line_b must be driven with identical line numbers. For video formats where the picture line number and the transport line number are not the same, the line numbers must always be transport line numbers.

Dual Link HD-SDI Transmitter OperationThe Virtex-6 FPGA Triple-Rate SDI core does not contain the formatting logic to map the various video formats into ST 372 dual link HD-SDI streams. However, formatted ST 372 dual link HD-SDI streams can be transmitted by a pair of triple-rate SDI transmitters. One transmitter implements the A link while the second implements the B line. Both transmitters operate in HD-SDI mode. The first transmitter takes in the Y and C data streams of link A on its tx_a_y_in and tx_a_c_in ports, respectively. The second transmitter takes in the Y and C data streams of link B on its tx_a_y_in and tx_a_c_in ports (not its tx_b_y_in and tx_b_c_in ports).

Both transmitters must run at exactly the same bit rate, so they must be given the same GTX transmitter reference clock.

Summary of Triple-Rate TX ModesThe input data rates and connections for all SDI modes are summarized in Table 5-1.

Table 5-1: Triple-Rate SDI TX Modes

SDI Modetx_level_b_

3GTXOUTCLK tx_ce tx_din_rdy Input Data Rate tx_a_y_in tx_a_c_in tx_b_y_in tx_b_c_in

HD-SDI and Dual Link HD-SDI

X74.25 MHz or

74.25/1.001 MHzHigh High

74.25 MHz or 74.25/1.001 MHz

Y C

SD-SDI X 148.5 MHz5/6/5/6 Cadence

High 27 MHz Y/C

3G-SDI A 0148.5 MHz or

148.5/1.001 MHzHigh High

148.5 MHz or 148.5/1.001 MHz

Data Stream 1

Data Stream 2

3G-SDI B 1148.5 MHz or

148.5/1.001 MHzHigh

Asserted every other clock cycle

74.25 MHz or 74.25/1.001 MHz

Link A Y Link A C Link B Y Link B C



Triple-Rate TX Details

Triple-Rate TX DetailsThis section provides some additional details about the operation of the triple-rate SDI transmitter.

ST 352 Packet InsertionThe Virtex-6 FPGA Triple-Rate SDI core can insert ST 352 VPID packets into SD-SDI, HD-SDI, dual link HD-SDI, and 3G-SDI (both level A and level B) streams. The dual link HD-SDI and 3G-SDI standards require ST 352 packets in the data streams. The packets are optional in SD-SDI and HD-SDI data streams.

The ST 352 packet insertion function takes the user data words of the ST 352 packet from the VPID input ports: tx_vpid_byte1, tx_vpid_byte2, tx_vpid_byte3, tx_vpid_byte4a, and tx_vpid_byte4b. The tx_vpid_byte4b port is only used in 3G-SDI mode to allow unique identification between the two data streams carried on the 3G-SDI interface.

ST 352 packets are inserted on one designated video line in each frame if the transport is progressive, and one designated video line in each field if the transport is interlaced. The designated video lines that carry ST 352 packets vary depending on the SDI mode and the video format as described in the SMPTE ST 352 standard. The ST 352 packet is inserted at the beginning of the HANC space of the line specified by the tx_line_f1 input port for progressive video or for the first field of interlaced video. For interlaced video, an ST 352 packet is also inserted on the line specified by the tx_line_f2 input port. The tx_line_f2_en input determines whether packets are inserted in the line specified by tx_line_f2. The tx_line_f2_en input must be Low for a progressive transport and High for an interlaced transport.

The tx_line_f2_en input must be controlled correctly. This input must be High for interlaced video and Low for progressive video. However, this input must be controlled based on whether the transport is interlaced or progressive, not the picture. The 1080p 50 Hz and 60 Hz 4:2:2 10-bit video formats, when carried by dual link HD-SDI or 3G-SDI level B (but not 3G-SDI level A), are transported in an interlaced manner, even though the picture is progressive. The same is true for progressive segmented frame transport. It is essential that the ST 352 packets are inserted into both fields of the transport data streams for these formats. Some receiving equipment fails to lock properly if the ST 352 packets are only present in one field rather than in both fields of interlaced transports.

Dual link HD-SDI data streams coming from a dual link SDI receiver can already have ST 352 packets in the Y data streams of each link, because ST 372 mandates these packets. If the packets are present, the first user data word should be 0x87, indicating that the data streams are carried on a dual link HD-SDI interface. If these dual link data streams are to be retransmitted on a 3G-SDI level B-DL interface, the first user data word of the packet must be replaced with a value of 0x8A, indicating an ST 372 signal carried on a 3G-SDI level B-DL interface. Therefore the ST 352 packets must be modified when sending the dual link HD-SDI streams on a 3G-SDI level B-DL interface. Only the first byte of the VPID data must be modified. The values of the other bytes do not need to change. However, they must be captured first and applied to the VPID byte inputs triple-rate SDI transmitter so that they are re-inserted when the packet is overwritten (as part of the process of updating the packet). This is because the inserter overwrites the entire packet, not just the first user data word.

In 3G-SDI level B-DS mode, two independent HD-SDI signals are carried by the 3G-SDI level B interface. These two HD-SDI signals can be vertically unsynchronized (not frame-locked). If this is the case, then ST 352 packets are inserted independently on the two HD-SDI signals carried by the 3G-SDI level B-DS interface. The tx_line_b input port on the




Virtex-6 FPGA Triple-Rate SDI core allows two separate line numbers to be provided for level B, one for each HD-SDI signal. Because there is only one set of VPID data inputs to the insertion module, the ST 352 packets, with the exception of byte 4, are identical. Thus the two HD-SDI streams must carry identical video formats. This is normally the case because of the restrictions in 3G-SDI level B-DS mode requiring the two HD-SDI streams to have the same format. If an application requires insertion of different VPID packets into the two HD-SDI signals carried by a 3G-SDI level B signal, the ST 352 packets must be generated and inserted into the data streams prior to entering the triple-rate SDI transmitter, and the tx_insert_vpid input must be Low.

Line Number InsertionBoth 3G-SDI and HD-SDI modes require that line numbers are present in the two words that follow each EAV. If the tx_insert_ln input is High, the triple-rate SDI transmitter inserts those line numbers appropriately for HD-SDI and both levels of 3G-SDI (inserting them into all four data streams for level B 3G-SDI). The line numbers inserted are provided to the triple-rate SDI transmitter on the tx_line_a and tx_line_b inputs. In some cases, it might not be necessary or desirable to overwrite line numbers already present in the data streams. In that case, the tx_insert_ln input can be driven Low, and no line numbers are inserted. If the tx_insert_ln input is hardwired Low in the source code, the line number insertion logic is optimized out of the design by the synthesis tool.

For dual link HD-SDI data streams carried either by dual link HD-SDI or 3G-SDI level B interfaces, if the video format is 1080p 50 Hz, 59.94 Hz, or 60 Hz, the line numbers are required to be transport line numbers, not video line numbers.

For HD-SDI, dual link HD-SDI, and 3G-SDI level A formats, only the line number on tx_line_a is used. For 3G-SDI level B, the line number on tx_line_a is inserted into the Y and C data streams of link A, and the line number on tx_line_b is inserted into the Y and C data streams of link B (again, only if tx_insert_ln is asserted).

CRC Generation and InsertionBoth 3G-SDI and HD-SDI modes require that CRC values are present in the two words that follow the line numbers after the EAV. If the tx_insert_crc input is High, the triple-rate SDI transmitter calculates and inserts CRC values for each line for HD-SDI, and both levels of 3G-SDI (inserting them into all four data streams for level B 3G-SDI). In some cases, it might not be necessary or desirable to overwrite the CRC values already present in the data stream. In that case, the tx_insert_crc input can be driven Low, and no CRC values are inserted. If the tx_insert_crc input is hardwired Low, the CRC generation and insertion logic is optimized out of the design by the synthesis tool.

EDH Generation and InsertionEDH packets are optional, but usually present, in SD-SDI. They are never used for HD-SDI and 3G-SDI modes. The EDH packets contain CRC values that can be used to detect errors in the SD-SDI data stream. When running in SD-SDI mode, the triple-rate SDI transmitter generates and inserts EDH packets when tx_insert_edh is High. If tx_insert_edh is hardwired Low, the synthesis tool optimizes the EDH generator out of the design. The EDH processor has a flywheel function that generates and inserts EAV and SAV sequences for the SD-SDI data stream. When locked to the timing of the SD-SDI data stream, the flywheel continues to generate and insert valid EAV and SAV sequences in the transmitted data stream, even if the input data stream stops. This flywheel function is a necessary part of the EDH processor and cannot be disabled when EDH packets are being generated and



Triple-Rate TX Details

inserted (tx_insert_edh is High). This flywheel only works in SD-SDI mode. There is no equivalent flywheel for 3G-SDI or HD-SDI modes.

Ancillary Data InsertionIt is often necessary to embed ancillary data into the SDI data streams before transmission. This is best performed after the ST 352 packets have been inserted but before any other formatting occurs. Thus, ancillary data insertion is normally performed between the two main functions of the triple-rate SDI transmitter. The Virtex-6 FPGA Triple-Rate SDI core allows this by providing raw data stream outputs after ST 352 packet insertion is completed and accepting data streams in from an ancillary data inserter. Use of these datapaths for ancillary data insertion is, however, optional and the data streams from the ST 352 packet inserter can be routed internally to the rest of the SDI transmitter. This is controlled by the tx_use_dsin port. When this port is High, the core is configured for operation with a user-supplied ancillary data inserter. The data streams containing the ST 352 packets are output on the tx_dsxx_out ports to feed to the ancillary data inserter. The data streams from the ancillary data inserter must be connected to the Triple-Rate SDI core’s tx_dsxx_in ports. The number of tx_dsxx_out and tx_dsxx_in ports that are active varies depending on the SDI mode and level. When the tx_use_dsin port is Low, the data streams from the ST 352 inserter are routed internally and directly to the rest of the transmitter section. The rx_dsxx_in ports are not used.

Reference Clocks and Reference Clock SwitchingThe GTX transmitters require two different reference clock frequencies to transmit all of the SDI bit rates. These reference clock frequencies are typically 74.25 MHz and 74.25/1.001 MHz (or two times these two frequencies). It is important to always use 74.25 MHz or 148.5 MHz, and never 74.25/1.001 MHz or 148.5/1.001 MHz, when transmitting SD-SDI.

There are two ways to switch between the two required reference clock frequencies. The first is to provide a single external reference clock to the GTX transmitter and change the frequency of the reference clock externally. A more flexible approach is to provide both reference clock frequencies to the GTX transmitter and use the TX PMA PLL reference clock multiplexer to dynamically switch between these two reference clock frequencies. The TXPLLREFSELDY input port on the GTX transceiver wrapper dynamically controls the reference clock multiplexer.

The GTX transmitter must always be reset after the reference clock frequency is changed. This ensures that the PMA PLL locks correctly to the new reference clock frequency. Regardless of whether the reference clock is changed externally or by changing the reference clock multiplexer, the GTXTXRESET input of the GTX transmitter must be briefly asserted High to reset the GTX transmitter after the reference clock frequency has changed. Unlike many other resets associated with the GTX transmitter, this reset is not automatically handled by the Virtex-6 FPGA Triple-Rate SDI core because it does not know when the reference clock frequency changes. The application must pulse the GTXTXRESET port of the GTX transmitter whenever the frequency of the TX reference clock changes.

Each Virtex-6 FPGA GTX Quad has two external reference clock inputs. It can also receive two reference clocks from the Quad above and two from the Quad below. This provides very flexible reference clock routing. There are, on average, only half as many external reference clock inputs as there are GTX transmitters. Therefore it is not possible to provide a dedicated external reference clock input for every GTX transmitter in the device.




This is not an issue in most SDI applications. Typically, the transmitter reference clocks come from a genlock PLL. Only one pair of reference clocks is needed for all of the SDI transmitters in the Virtex-6 device. For complete flexibility in such a genlocked system, it is recommended that the genlock PLL produce two reference clock frequencies: 74.25 MHz and 74.25/1.001 MHz (or 148.5 MHz and 148.5/1.001 MHz). These two reference clock frequencies can be connected to the FPGA’s dedicated serial transceiver reference clock inputs and routed to all of the GTX Quads used to implement SDI interfaces. This provides both reference clock frequencies to each GTX transmitter so that each transmitter can be independently set to transmit any of the supported SDI bit rates. In larger devices, an external reference clock cannot drive all GTX Quads in a device, and the reference clocks might need to enter the FPGA on multiple transceiver reference clock input pins to enable routing to all of the SDI GTX Quads. See UG366, Virtex-6 FPGA GTX Transceivers User Guide for detailed reference clock routing information.

If the TX reference clock source only supplies one reference clock frequency and not both, there can be significant SDI transmitter restrictions. If the reference clock frequency is 74.25 MHz, the transmitter can transmit SD-SDI at 270 Mb/s, HD-SDI at 1.485 Gb/s, and 3G-SDI at 2.97 Gb/s. However, if the reference clock frequency supplied by the genlock PLL is 74.25/1.001 MHz, the transmitter can only transmit HD-SDI at 1.485/1.001 Gb/s and 3G-SDI at 2.97/1.001 Gb/s. It cannot transmit SD-SDI because SD-SDI requires a 74.25 MHz reference clock.

Some SDI applications require a separate reference clock for each SDI transmitter. Because there are only half as many external reference clock inputs as there are GTX transmitters in the device, it might not be possible to use each GTX transmitter in this case. Unused external reference clock inputs from adjacent Quads can help supply additional reference clocks, but if all of the external reference clock inputs are used, then only half of the GTX transmitters can be supplied with unique reference clocks.

Use of the GREFCLK and PERFCLK reference clocks are not recommended for SDI transmitter applications because of jitter concerns. If necessary, GREFCLK or PERFCLK can be used to supply a reference clock to SDI receivers because the additional jitter on the reference clock has less impact on the performance of the CDR than it does on the transmitter output jitter.

Electrical InterfaceThe GTX transmitter outputs are differential CML signals with an 800 mV common mode voltage. These signals are not directly compatible with the SDI electrical requirements. An SDI cable driver is required to interface the GTX transmitter output to the SDI connector. Most, if not all, SDI cable drivers currently available do not support an input common mode voltage of 800 mV. AC coupling is usually required between the GTX transmitter outputs and the SDI cable driver inputs. The value of these AC coupling capacitors is typically 4.7 µF.

The GTX TX driver is highly configurable. The amplitude swing, pre-emphasis, and post-emphasis values can be dynamically changed via ports on the GTX transceiver wrapper or set to fixed values by the GTX Transceiver Wizard.

The recommendations of the cable driver manufacturer must be followed for interfacing the output of the cable driver to the BNC cable.



Chapter 6

Implementing the Core

Timing ConstraintsThe timing constraints for the LogiCORE™ IP Virtex®-6 FPGA Triple-Rate SDI core are simple. Period constraints need to be supplied for the three input clocks: drpclk, tx_usrclk, and rx_usrclk. The maximum frequency for both tx_usrclk and rx_usrclk is 148.5 MHz. The drpclk frequency is application dependent. In the following example code, three period constraints are sufficient to constrain the core. In this example, it is assumed that there are multiple GTX transceivers used to implement SDI interfaces and that the txoutclk and rxrecclk signals are prefixed with gtxsdi0, gtxsdi1, and so forth. A “?” wildcard is used to constrain all matching clock signals.

## The GTX TXOUTCLKs of all SDI transmitters run at about 150 MHz max# NET gtxsdi?_txoutclk TNM_NET = sdi_txoutclk;TIMESPEC TS_sdi_txoutclk = PERIOD sdi_txoutclk 150 MHz HIGH 50 % INPUT_JITTER 100 ps;

## The GTX RXRECCLKs of all SDI receivers run at about 150 MHz max#NET gtxsdi?_rxrecclk TNM_NET = sdi_rxrecclk;TIMESPEC TS_sdi_rxrecclk = PERIOD sdi_rxrecclk 150 MHz HIGH 50 % INPUT_JITTER 100 ps;

## 27 MHz DRP clock (Example only: set this to the actual frequency of the DRP clock!)#NET clk_fmc_27M_in TNM_NET = drpclk;TIMESPEC TS_drpclk = PERIOD drpclk 27 MHz HIGH 50 % INPUT_JITTER 100 ps;

Other ConstraintsIt is recommended that the safe_implementation option in Xilinx® Synthesis Technology (XST) HDL properties be set to Yes. The RXRECCLK and TXOUTCLK of the GTX transceiver can become erratic when reference clocks or input bitstreams are suddenly changed. This can cause timing issues for the logic in the Virtex-6 FPGA Triple-Rate SDI core driven by these clocks. Critically, it can cause issues with finite state machines, especially if XST is allowed to optimize invalid state recovery out of the state machine. By setting the safe_implementation option to Yes, the invalid state recovery of the state machines is retained.




SD-SDI DRUThe DRU used to recover the SD-SDI data is supplied as a pre-compiled NGC file and not in source-code form. In Verilog implementations, the wrapper file called dru.v defines the ports of the DRU. This wrapper file must be included in the project. In VHDL implementations, no dru.vhd file is required because the dru component declaration defines the ports of the DRU. The dru/dru.ngc file contains the actual implementation of the DRU and is automatically included into the project when the CORE Generator™ tool generates the Triple-Rate SDI core.

At this time, the dru.ngc file cannot be simulated. To facilitate simulation, a simple DRU model for simulation is supplied with the Triple-Rate SDI core. The simulation model is found in the dru/dru_sim.v and dru/dru_sim.vhd files. When building a Verilog simulation model, the dru_sim.v file should be included in the project instead of the dru.v file. For VHDL simulation, the dru_sim.vhd file should be included in the project. Do not use the dru_sim files for the actual implementation of the design because these dru_sim models do not provide tolerance for jitter on the SD-SDI signal.

GTX Transceiver WrapperThe GTX transceiver is added to the application by running the GTX Transceiver Wizard in the CORE Generator tool to create a GTX transceiver wrapper. This wizard has a protocol template called hd sdi. When this protocol template is chosen, the GTX Transceiver Wizard generates a GTX transceiver wrapper that is fully compatible with the Triple-Rate SDI core. The user then instantiates the GTX transceiver wrapper and the Virtex-6 FPGA Triple-Rate SDI core in the application and connects them together to implement the SDI interface.


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