November 2008Revision: EB24_01.4

LatticeSC™ PCI Express x1 Evaluation Board

User’s Guide

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Introduction

This user’s guide describes the LatticeSC PCI Express x1 Evaluation Board featuring the LatticeSC LFSCM3GA25device in a 900 fpBGA package. The stand-alone evaluation PCB provides a functional platform for developmentand rapid prototyping of applications that require high-speed SERDES interfaces to PCI Express protocols.

The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to testand measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. Thenominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.

The board has several debugging and analyzing features for complete evaluation of the LatticeSC device. Thisuser’s guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the Lat-ticeSC FPGA.

Figure 1. LatticeSC PCI Express x1 Evaluation Board

Features

• Four SERDES high-speed channels interfaced to SMA test points and clock connections SERDES interface to x1 PCI Express edge fingers

• RJ-45 interface for Ethernet

• QDR2 and RLDRAMII memory devices

• SFP Transceiver cage and associated interface

• SATA-like connections to SERDES channels

• Power connections and power sources

• ispVM

®

programming support

• On-board and external reference clock sources– Interchangeable clock oscillators– On-board reference clock management

• ORCAstra Demonstration Software interface via standard ispVM JTAG connection

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

• RS-232 Communications Port

• Logic analyzer connection

• Liquid Crystal Display interface connection

• User-defined input and output points

• SMA connectors included for high-speed clock or data interfacing

• Performance monitoring via test headers, LEDs and switches

The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluationboard, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of theboard. Figure 2 shows the functional partitioning of the board.

Figure 2. LatticeSC PCI Express x1 Evaluation Board Block Diagram

Additional Resources

For additional information and resources related to this board, including updated documentation and softwaredemos, please see the Lattice web site at: www.latticesemi.com/boards, and navigate to the appropriate page forthis board.

Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their endapplication by consulting documentation provided by Lattice. Differences in component selection and/or PCB layoutin the user's application may significantly affect circuit performance and reliability.

SC15/SC25900 fpBGA

FlxMac

RIGHT

LEFT

FlxMac

BO

TT

OM

X1 PCIeFingers

1Gbe-SFP

NationalPHY

RJ-45

RS-232

2x5 COM

10/100/1000

QDR2

FlashOsc

SGMII

SATA-Host

JTAGOrcastra

magnetics

Power Regulation

12V Edge Fingers

12V WallWart

Terminal Block

x1 PCI Express Driver Platform Board

for LatticSC 900 fpBGA Devices

ConfigStatus & Control

Backpanel Slot

Backpanel Slot

PCI Clk

PLL*1.25

SATA-Target

TestpointsLEDs

Switches

Osc

Clock Control

I2C

EEPROM

Maxim6692

PTEMP

SERDESLoop

SERDESSMAs

Osc

REFCLK-RIGHT

REFCLK-LEFT100MHz

DifferentialTraceLoops

RLDRAM2

LVDSSMAs

18-bit

18-bit

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 3. LatticeSC PCI Express x1 Evaluation Board, Top View

LatticeSC Device

This board features a LatticeSC FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeSCdevices in the 900-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the Lat-ticeSC Family Data Sheet on the Lattice web site at www.latticesemi.com.

Note: The connections referenced in this document refer to the LFSCM3GA25EP1-XXF900 device. Available I/Osand associated sysIO™ banks may differ for other densities within this device family.

Applying Power to the Board

The LatticeSC PCI Express x1 Evaluation Board is ready to power on. The board can be supplied with power froman AC wall-type transformer power supply shipped with the board or it can be supplied from a bench top supply viaterminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a hostboard.

To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cordto J6 and plug the wall transformer into an AC wall outlet.

Power Supplies

(see Appendix A, Figure 6)

The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped toaccept a main supply via the TB1 connection. This connection is provided to use with a bench top supply adjustedto provide a nominal 12V DC.

All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDsto indicate power GOOD status of the intermediate supplies

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Table 1. Board Power Supply Fuses (see Appendix A, Figure 6)

Table 2. Board Power Supply Indicators (see Appendix A, Figure 6)

Table 3. Board Supply Disconnects (see Appendix A, Figure 7)

PCI Express Power Interface

Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide powerfrom a PCI Express host board.

VCC Core Selection

(see Appendix A, Figure 6)

The VCC core can be selected on the board to be either 1.0V or 1.2V using J7.

A jumper shunt placed between pin 1 and pin 2 will connect 1.0V. A jumper shunt between pin 2 and pin 3 will con-nect 1.2V.

Programming/FPGA Configuration

(see Appendix A, Figure 5)

A programming header is provided on the evaluation board, providing access to the LatticeSC JTAG port.

Important Note:

The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAGpins. Failure to follow these procedures can in result in damage to the LatticeSC FPGA device and render theboard inoperable.

An ispDOWNLOAD

®

Cable is included with this board and also with each ispLEVER

®

design tool shipment. Cablesmay also be purchased separately from Lattice.

F1 1.0V/1.2V Core Fuse

F2 1.5V Fuse

F3 3.3V Fuse

F4 1.2V Fuse

F5 2.5V Fuse

F6 1.8V Fuse

D6 2.5V Source Good Indicator

D7 3.3V Source Good Indicator

D8 1.0V/1.2V VCC Core Source Good Indicator

D9 1.5V Source Good Indicator

D10 1.8V Source Good Indicator

D11 1.2V Source Good Indicator

D12 12V Input Good Indicator

TB1

Screw Terminal for 12V DC

Pin 1 (Square PCB Pad) = 12V DC

Pin 2 = Ground

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

ispVM Download Interface

J3 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and controlthe device. Connections to the cable typically consist of Pin[1:2:3:6:7:8]. The other pins are considered optionaland are not required to be connected for standard operation.

Table 4. ispVM JTAG Connector (see Appendix A, Figure 5)

Download ProceduresRequirements

• PC with ispVM System v.16.0 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). The latest ispVM System software can be downloaded from the Lattice web site at www.latticesemi.com/ispvm.

Note: An option to install these drivers is included as part of the ispVM System setup.

• ispDOWNLOAD Cable

JTAG Download

The LatticeSC device can be configured easily via its JTAG port. The device is SRAM-based; it must remain pow-ered on to retain its configuration when programmed in this fashion.

1. Connect the ispDOWNLOAD cable to the appropriate header. J3 is used for the 1x10 cable. Connections to J3 use only pins[1-3][6-8].

2. Connect the LatticeSC PCI Express x1 evaluation board to the appropriate power sources and power up board.

3. Start the ispVM System software.

Pin 1 VCC

Pin 2 TDO

Pin 3 TDI

Pin 4 PROGRAMN

1

Pin 5 NC

Pin 6 TMS

Pin 7 GND

Pin 8 TCK

Pin 9 DONE

1

Pin 10 INITN

1

1. Optional pins.

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

4. Press the

SCAN

button located in the toolbar. The LatticeSC device is automatically detected.

5. Double-click the device to open the device information dialog. In the device information dialog, click the

Browse

button located under

Data File

. Locate the desired bitstream file (.bit). Click

OK

to both dialog boxes.

6. Click the green

GO

button. This will begin the download process into the device. Upon successful download, the device will be operational.

Configuration Status Indicators

(see Appendix A, Figure 5)

These LEDs indicate the status of configuration to the FPGA.

• D2 (RED) illuminated: This indicates that the programming was aborted or reinitialized driving the INITN output low.

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

• D5 (GREEN) is illuminated: This indicates the successful completion of configuration by releasing the open col-lector DONE output pin.

• D1 (GREEN) will flash indicating TDI activity.

• D4 (RED) illuminated: This indicates that PROGRAMN is low.

• D3 (RED) illuminated: This indicates that GSRN is low.

PROGRAMN and GSRN

(see Appendix A, Figure 5)

These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2).Depressing the button drives a logic level “0” to the device.

Bank1 VCCIO

(see Appendix A, Figure 6)

VCCIO1 can be selected on the board to be either 3.3V or 2.5V using J5.

A jumper shunt placed between pin 1 and pin 2 will connect 2.5V. A jumper shunt between pin 2 and pin 3 will con-nect 3.3V.

On-Board Flash Memory

(see Appendix A, Figure 5)

Two memory devices (U2 and U3) are on-board for non-volatile configuration memory storage. These two devicesoccupy the same Flash slot on the board. U2 can be populated with an 8M or smaller 8-pin SOIC device. U3 can beused in place of U2 with a 16-pin TSSOP 64M Flash device. This is the factory supplied Flash memory configura-tion. U4 is always supplied as an 8M Flash device. SW1 is used to control the selection of the Flash memory to beaccessed.

Refer to Lattice technical note TN1100,

SPI Serial Flash Programming Using ispJTAG™ on LatticeSC FPGAs

forrecommended procedures and software usage. To use both SPI Flash devices to program the LatticeSC device,the user must write to the Flash devices individually. This is accomplished by setting SW1 accordingly. Writing toFlash #1(U2 OR U3), close 3 and 5 switch positions (ON) and open all others. Writing to Flash #2(U4), close 2 and4 switch positions (ON) and open all others. For reading from the Flash devices individually, use the same switchsettings as described for writing. For reading from both Flash devices in cascading format, close switch positions(1, 3, 4, 5, 8).

FPGA Clock Management

(see Appendix A, Figures 10 and 11)

The evaluation board includes various features for generating and managing on-board clocks. The clocks are gen-erated from either input provided from SMAs (see Table 5) or from crystal oscillators (Y1 and Y4). Y1 and Y4 aresocketed for interchangeability. Y2 and Y5 are 321.25MHz surface-mounted oscillators. The Y3 oscillator is fannedout around U1 for reference clocks with a fan-out buffer IC.

Y1 and Y4 can be a 4-pin DIP type oscillator like Connor-Winfield XO-400 series.

Clock oscillators are selected per quad. Y1 and Y2 can source a clock to the Right SERDES Quads. Y4 and Y5 cansource a clock to the Left SERDES Quad. The user needs to select the appropriate oscillator by placing jumpershunts on J20 and/or J22 for the Left reference clock source or J25 and/or J28 for the Right reference clock source.The selection of these clock sources is dependent on the selection pins of the clock multiplexers. The mux selectpins are driven from the FPGA and will need to be driven according to the needs of the user design. The followingtable defines the selection of the clock sources.

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Table 5. Clock Source Selection (see Appendix A, Figures 5 and 10)

When using FPGA control, 3.3V VCCIO must be used in bank 1. Refer to Bank1 VCCIO section of this document.

Table 6. Clock Input SMA (see Appendix A, Figure 10)

The clocks sources are fanned-out across the board to several destinations. These clocks are all differential andmust be used accordingly. These include SERDES reference clocks, PLL, and primary clock inputs.

Table 7. Clock Distribution (see Appendix A, Figure 11)

The clocks are also driven to SMA connections for driving off-board.

Table 8. Clock Output SMAs (see Appendix A, Figure 11)

SERDES Reference Clock

The 50-ohm terminated SMA connectors are provided the supply reference clocks directly to the LatticeSC devicefrom the clock management device. This device will drive clocks to both SERDES quads via 100-ohm LVDS signal-ing. On-board clock oscillators mentioned in the previous sections can be chosen to drive the same SERDES refer-ence clocks. Also the board can be provisioned to source the clock from the PCI Express edge-fingers directly toFPGA input pins.

Both of these input clock sources are routed through clock management devices allowing for clock source selectionfrom a SMA input connector. This is accomplished by using the MUX selector driven by the FPGA output.

BGA-A19 BGA-A20 Right Clock Source Left Clock Source

L L SMA SMA

H H Oscillator Oscillator

Pin is low when open/float. FPGA general purpose I/O must be driven to control the mux selection.

SMA Signal

J29 SMA Reference + Input to Left Quad

J30 SMA Reference - Input to Left Quad

J23 SMA Reference + Input to Right Quad

J24 SMA Reference - Input to Right Quad

Clock Net BGA Clock Destination

FPGA_REFCLKP_L P8 PCLKT7_2

FPGA_REFCLKN_L R8 PCLKC7_2

FPGA_REFCLKP_R AD26 LRC_PLLB_T

FPGA_REFCLKN_R AC25 LRC_PLLB_C

A_REFCLKP_L B1 SERDES[360]

A_REFCLKN_L C1 SERDES[360]

A_REFCLKP_R B30 SERDES[3e0]

A_REFCLKN_R C30 SERDES[3e0]

Net Name SMA SMA

EXTCLOCK_L J31 J32

EXTCLOCK_R J33 J34

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

SERDES Channels

SMA Connections

(see Appendix A, Figure 5)

DC coupled top-mounted SMA connectors connect to the two SERDES TX and RX channels. These pins aredirectly coupled to the designated SMA connector creating a path for both input and output differential data.

Table 9. SERDES Connectors (see Appendix A, Figure 8)

SERDES SFP Transceiver Interface

(see Appendix A, Figure 8)

A small form-factor pluggable (SFP) transceiver cage is included for evaluation of SFP specific protocols. The PCBincludes the appropriate power and high-speed circuitry needed for the SFP standard transceiver.

Table 10. SFP Connections to SERDES Pins (see Appendix A, Figure 5)

Table 11. SFP Control and Status Connections to FPGA

SERDES SATA Channels

(see Appendix A, Figure 8)

AC-coupled connections are included to attach SATA type cables to SERDES channels for board-to-board or loop-back purposes. The connectors are configured using the 7-pin SATA specifications.

SMA Channel Name900-BallfpBGA SMA Channel Name

900-BallfpBGA

J13 A_HDINP1_LEFT B6 J10 A_HDOUTP1_LEFT A6

J15 A_HDINN1_LEFT B5 J12 A_HDOUTN1_LEFT A5

J9 A_HDINP2_LEFT B7 J14 A_HDOUTP2_LEFT A7

J11 A_HDINN2_LEFT B8 J16 A_HDOUTN2_LEFT A8

SFP RX Channel Name900-BallfpBGA SFP TX Channel Name

900-BallfpBGA

RD+ A_HDINP0_RIGHT B28 TD+ A_HDOUTP0_RIGHT A28

RD- A_HDINN0_RIGHT B27 TD- A_HDOUTN0_RIGHT A27

SFP Pin900-BallfpBGA SFP Pin

900-BallfpBGA

TxFault A15 ModeDef0 E15

TxDis C13 ModeDef1 D15

LOS G15 ModeDef3 C14

RateSel F15

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Table 12. SERDES to SATA Connections

SERDES PCI Express Channels

(see Appendix A, Figure 8)

This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-fingers (CN1) to fit directly into an x1 host receptacle. Power can be supplied directly from the PCI Express host viathe edge-finger connections.

Table 13. SERDES to PCI Express Connections

FPGA Test Pins

(see Appendix A, Figure 15)

General purpose FPGA pins are available for user applications. FPGA pins are connected to SW4 DIP switch. Thisswitch is used for static settings to FPGA input pins. The pins must be set to LVCMOS18 buffer types and are exter-nally pulled up when the switch is open and driven low when the switch is set to “ON” or closed.

General purpose outputs are connected to LEDs for observing output status of pins. The FPGA output buffersshould be LVCMOS18 and will illuminate the LED when driving a “1” and the LED will be off when driving a “0” orwhen not used.

Table 14. FPGA Test Pins (see Appendix A, Figure 15)

CN1 Pin SERDES Pin900-BallfpBGA CN2 Pin SERDES Pin

900-BallfpBGA

1 __ GND 1 __ GND

2 A_HDOUTP1_R A25 2 A_HDINP2_R B24

3 A_HDOUTN1_R A26 3 A_HDINN2_R B23

4 __ GND 4 __ GND

5 A_HDINP1_R B25 5 A_HDOUTP2_R A24

6 A_HDINN1_R B26 6 A_HDOUTN2_R A23

7 __ GND 7 __ GND

PCI Express Pin

PCI Express Signal SCM Device Pin

900-BallfpBGA

B14 PETp0 A_HDINP0_L B3

B15 PETn0 A_HDINN0_L B4

A16 PERp0 A_HDOUTP0_L A3

A17 PERn0 A_HDOUTN0_L A4

A13 Refclk+ FPGA URC_A PLL Input+ D28

A14 Refclk- FPGA URC_A PLL Input+ E28

Switch BGA Netname LED 900-Ball fpBGA NetName LED Color

SW4A G28 Switch1 D15 H26 LED1 Red

SW4B F28 Switch2 D16 G26 LED2 Yellow

SW4C L25 Switch3 D17 D29 LED3 Green

SW4D L26 Switch4 D18 D30 LED4 Blue

SW4E E29 Switch5 D19 K25 LED5 Red

SW4F E30 Switch6 D20 K26 LED6 Yellow

SW4G J28 Switch7 D21 H30 LED7 Green

SW4H H28 Switch8 D22 K30 LED8 Blue

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Test SMA Connections

General-purpose FPGA pins are available via SMA test connections. These connections are designed to permitevaluations of several types of FPGA I/O buffers. The use of several termination schemes permits easy interfacesfor the type of buffer.

Table 15. Test SMA Connections for FPGA Pins (see Appendix A, Figure 16)

High Speed Test Point

DP2

(see Appendix A, Figure 15 and 16)

General-purpose FPGA pins are available via a differential test pad. These connections allow a high-impedanceprobe to measure the performance of a coupled-differential output buffer pair.

Table 16. Differential I/O Test Point

Logic Analysis Connection

LA1

(see Appendix A, Figure 15 and 16)

Agilent single-ended probes designed for connection to the supplies Tyco/AMP’s 2-767004-2 MICTOR connectorcan be easily attached for signal bus analysis. Connections to general-purpose I/O pins are provided to the boardready 38-pin MICTOR connector.

SMA Designation Name

SCM25Signal

900-Ball fpBGA

Termination Description

Termination Resistor(s)

J37 LVDS_INP PR52A AB28 None —

J39 LVDS_INN PR52B AC28 None —

J38 LVDS_OUTP0 PR35A M29 100-ohm Differential R275

J40 LVDS_OUTN0 PR35B N30 100-ohm Differential R275

Probe True

Probe Compliment

100-ohm Differential Resistor

AF30 AG30 R274

Table 17. Logic Analyzer Connections

MICTOR Pin Signal 900-Ball fpBGA MICTOR Pin Signal 900-Ball fpBGA

5 LA_CLK1 AJ1 6 LA_CLK2 AF4

7 LA_0 AG3 8 LA_16 AH13

9 LA_1 AH2 10 LA_17 AK8

11 LA_2 AD8 12 LA_18 AK9

13 LA_3 AF7 14 LA_19 AH14

15 LA_4 AJ7 16 LA_20 AG14

17 LA_5 AJ8 18 LA_21 AK10

19 LA_6 AH10 20 LA_22 AK11

21 LA_7 AH11 22 LA_23 AH15

23 LA_8 AF13 24 LA_24 AG15

25 LA_9 AE14 26 LA_25 AH12

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

RS-232 Interface

J36

(see Appendix A, Figures 5 and 16)

A simple 2x5 Header provides a connection to create a RS-232 serial communications port. The connectionincludes the proper level shift needed to connect to a serial port of a PC. The RX and TX pins are connected to theFPGA.

Table 18. RS-232 TX/RX

LCD Interface

J41

(see Appendix A, Figures 5 and 16)

A 2x8 Header provides a connection to 16-character x 2 line LCD modules such as Varitronix VDM16265. A ribboncable connection will allow attachment to the connector. The board includes two variable resistors for LCD adjust-ments. VR1 adjusts the backlight and VR2 provides contrast adjustment. A user design must be included in theFPGA to drive this feature.

I

2

C Interface

(see Appendix A, Figures 5 and 16)

I

2

C interface is supplied between the FPGA and two ICs. This interface is used to access a Maxim temperaturesensing device as well as a EEPROM. The temperature-sensing device is also connected back to the FPGA via thePTEMP pins to monitor device temperature.

Table 19. I

2

C Interface

Ethernet Interface

(see Appendix A, Figures 5 and 13)

Interconnection to Base 10/100/1000 Ethernet protocols is supported via a RJ-45 connection (J35). This connec-tion is electrically interfaced to the FPGA through a tri-speed PHY device. Use of this interface requires a MAC

27 LA_10 AK6 28 LA_26 AJ13

29 LA_11 AK7 30 LA_27 AD15

31 LA_12 AF14 32 LA_28 AE15

33 LA_13 AF15 34 LA_29 AK12

35 LA_14 AJ11 36 LA_30 AK13

37 LA_15 AG13 38 LA_31 AJ14

Signal 900-Ball fpBGA Buffer Type

RS232-RXD F13 LVCMOS25

RS232-TXD F12 LVCMOS25

Signal 900-Ball fpBGA Buffer Type

SCL B11 LVCMOS25 or LVTTL33

SDA B12 LVCMOS25 or LVTTL33

Table 17. Logic Analyzer Connections (Continued)

MICTOR Pin Signal 900-Ball fpBGA MICTOR Pin Signal 900-Ball fpBGA

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

design to be included in the FPGA. The board includes two status LEDs to indicate Base 10 or Base 100 link.LED(D13) is a green LED which will light to indicate a Base100 link and LED(D14) indicates an established Base10 link. LED indicators on the RJ-45 connector will indicate activity and Base 1000 link status. Table 20 defines thepinout between the FPGA and PHY device.

Table 20. LatticeSC FPGA to Ethernet PHY Connections

QDR2 Memory Interface

(see Appendix A, Figures 12 and 15)

Interconnection to a Cypress CY7C1413AV18-2Mx18 QDR2 SRAM memory device is supplied on board. Itincludes the proper termination and interface requirements needed to operate at speed.

Signal900-Ball fpBGA

ETH_TX_D0 D3

ETH_TX_D1 D2

ETH_TX_D2 J6

ETH_TX_D3 J5

ETH_TX_D4 E3

ETH_TX_D5 E2

ETH_TX_D6 K4

ETH_TX_D7 J4

ETH_RX_D0 F3

ETH_RX_D1 G3

ETH_RX_D2 K5

ETH_RX_D3 K6

ETH_RX_D4 F2

ETH_RX_D5 F1

ETH_RX_D6 E1

ETH_RX_D7 D1

ETH_CRS K3

ETH_COL L3

ETH_RX_CLK L6

ETH_RX_DV M6

ETH_TX_EN J1

ETH_TX_CLK K1

ETH_GTX_CLK L1

ETH_CLK_TO_MAC M1

Table 21. QDR2 Memory Interface Pinouts

NetName FPGA Ball NetName FPGA Ball NetName FPGA Ball

A_0 T30 Q_0 AG29 D_0 AK16

A_1 W28 Q_1 AG28 D_1 AK17

A_2 U26 Q_2 AH30 D_2 AJ16

A_3 U28 Q_3 AJ30 D_3 AJ17

A_4 M30 Q_4 AH29 D_4 AE16

A_5 R29 Q_5 AJ29 D_5 AH16

A_6 P29 Q_6 AE25 D_6 AG16

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

RLDRAM-II Memory Interface

(see Appendix A, Figures 14 and 15)

Interconnection to a Micron MT49H16M18CFM-25 SDRAM memory device is supplied on board. It includes theproper termination and interface requirements needed to operate at speed.

Table 22. LatticeSC FPGA to On-board SDRAM Connections

A_7 P27 Q_7 AH28 D_7 AK18

A_8 N29 Q_8 AJ28 D_8 AK19

A_9 N28 Q_9 AE22 D_9 AH17

A_10 R25 Q_10 AK29 D_10 AH18

A_11 R28 Q_11 AK28 D_11 AG17

A_12 N27 Q_12 AH21 D_12 AJ18

A_13 L30 Q_13 AH23 D_13 AJ19

A_14 J30 Q_14 AH22 D_14 AK20

A_15 M26 Q_15 AG22 D_15 AK21

A_16 G29 Q_16 AG21 D_16 AF18

A_17 F29 Q_17 AF21 D_17 AG18

R_N AA30

W_N Y30

CQ AK24

K AJ20

K_N AJ21

NetName900 Ball fpBGA NetName

900 Ball fpBGA NetName

900 Ball fpBGA NetName

900 Ball fpBGA

A_0 AH4 D_0 V2 Q_0 V1 BA_0 AJ2

A_1 AG5 D_1 W2 Q_1 U5 BA_1 AK2

A_2 AF8 D_2 V5 Q_2 U4 BA_2 AD7

A_3 AG8 D_3 V4 Q_3 T4 CS_N AH1

A_4 AH3 D_4 Y1 Q_4 T5 DM AJ12

A_5 AJ3 D_5 AA1 Q_5 U1 QK AC7

A_6 AF9 D_6 Y2 Q_6 T1 QVLD N3

A_7 AE10 D_7 AA2 Q_7 V3 DK AC4

A_8 AK3 D_8 Y3 Q_8 U3 DK_N AD4

A_9 AJ4 D_9 W3 Q_9 T6 CK AC3

A_10 AE11 D_10 AB1 Q_10 U2 CK_N AD3

A_11 AF10 D_11 AC1 Q_11 T2

A_12 AH7 D_12 W5 Q_12 R4

A_13 AH8 D_13 Y5 Q_13 R1

A_14 AE12 D_14 Y6 Q_14 P1

A_15 AE13 D_15 AD2 Q_15 R2

A_16 AK4 D_16 AE2 Q_16 P4

A_17 AK5 D_17 AB5 Q_17 P3

Table 21. QDR2 Memory Interface Pinouts (Continued)

NetName FPGA Ball NetName FPGA Ball NetName FPGA Ball

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LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Ordering Information

Technical Support AssistanceHotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)e-mail: techsupport@latticesemi.comInternet: www.latticesemi.com

Revision History

© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are aslisted at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks oftheir respective holders. The specifications and information herein are subject to change without notice.

A_18 AJ5

A_19 AJ6

Description Ordering Part NumberChina RoHS Environment-Friendly

Use Period (EFUP)

LatticeSC PCI Express x1 Evaluation Board LFSC25E-P1-EV

Date Version Change Summary

October 2006 01.0 Initial release.

December 2006 01.1 Includes new SERDES schematic in Appendix A.

March 2007 01.2 Added Ordering Information section.

April 2007 01.3 Added important information for proper connection of ispDOWNLOAD (Programming) Cables.

November 2008 01.4 Updated FPGA Clock Management text section.

Updated Clock Source Selection table.

Updated Clock Input SMA table.

Updated 10/100/1000 PHY schematic.

NetName900 Ball fpBGA NetName

900 Ball fpBGA NetName

900 Ball fpBGA NetName

900 Ball fpBGA

10

17

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Appendix A. SchematicFigure 4. Cover Page

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

Co

ver

Pag

e

C

11

4

Tit

le

ve

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te

eh

S:

eta

Do

f

SC-9

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fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

Co

ver

Pag

e

C

11

4

Tit

le

ve

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te

eh

S:

eta

Do

f

SC-9

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fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

Co

ver

Pag

e

C

11

4

Board will meet PCI Express Electromechanical

Specification Rev 1.0

Add-in card form factor for standard height and full length

4.376" Height x 9.5" Length

Latt

iceS

C-90

0fpB

GA

X1 P

CI E

xpre

ss P

latf

orm

Eval

uatio

n Bo

ard

18

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 5. Configuration/Top Bank5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Q_

0W

RIT

E_P

RO

T_

N

Q_

1SC

SN_

1

FLA

SH_

DIS

MPIIRQN

SCSN

_0

SCSN

TC

K

LOC

AL_

TD

I

LOC

AL_

TC

K

TD

I

LOC

AL_

TM

S

PR

OG

RA

MN

TM

S

TD

O

TDO

TMS

INIT

N

DO

NE

M1

M2

M3

CS0

N

WR

N

CS1

RDCFGN

SCSN

INIT

N

DO

NE

DO

NE

INIT

N

FLA

SH_

DIS

CS1

WR

N

CS0

N

SCSN

_0

SCSN

_1

WR

ITE_

PR

OT

_N

FLA

SH_

DIS

M0

TD

I

TM

S

TC

K

GSR

N

TD

O

PR

OG

RA

MN

CC

LK

SCSN

_0

DA

TA

0

DA

TA

1

Q_

0

Q_

1

Q_

0

FLA

SH_

DIS

WR

ITE_

PR

OT

_N

WR

ITE_

PR

OT

_N

GSRN

PROGRAMN

PR

OG

RA

MN

GSR

N

SCK

SI

M0

M1

M2

M3

SI

SCK

RD

CFG

N

TCK

TDI

MP

IIRQ

N

DA

TA

1D

AT

A0

ETH

_M

DIO

ETH

_M

DC

ETH

_T

X_

ER

ETH

_R

X_

ERET

H_

RES

ET_

NET

H_

MA

C_

CLK

_EN

LCD

_R

/WLC

D0

LCD

_D

B0

LCD

1LC

D_

DB

2LC

D2

LCD

_D

B4

LCD

3LC

D_

DB

6LC

D4

LCD

_E

LCD

6

LCD

_R

SLC

D5

LCD

_D

B1

LCD

7LC

D_

DB

3LC

D8

LCD

_D

B5

LCD

9LC

D_

DB

7LC

D1

0

LCD[0..10]

ETH

_EG

P5

ETH

_EG

P6

ETH

_EG

P4

ETH

_EG

P7

ETH

_EG

P2

ETH

_EG

P3

ETH

_EG

P0

ETH

_EG

P1

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

2_

5V

3_

3V

3_

3V

3_

3V

2_

5V

3_

3V

2_

5V

2_

5V

2_

5V

3_

3V

2_

5V

2_

5V

3_

3V

2_

5V

PC

IE_

PER

STN

[5]

PC

IE_

SMC

LK[5

]P

CIE

_SM

DA

T[5

]P

CIE

_W

AK

EN[5

]

PT

EMP

[13

]

PC

IE_

PER

STN

[5]

RS2

32

_R

XD

[13

]SD

A[1

3]

SCL

[13

]

RS2

32

_T

XD

[13

] OSC

_IN

_1

[7]ET

H_

MD

IO[1

0]

ETH

_M

DC

[10

]

SFP

_LO

S[5

]

SFP

_T

XD

IS[5

]SF

P_

MO

DD

EF2

[5]

SFP

_M

OD

DEF

1[5

]SF

P_

MO

DD

EF0

[5]

SFP

_T

XFA

ULT

[5]

SFP

_R

AT

ESEL

[5]

CLO

CK

_C

TR

L_L

[7]

CLO

CK

_C

TR

L_R

[7]

ETH

_T

X_

ER[1

0] ET

H_

RX

_ER

[10

]ET

H_

RES

ET_

N[1

0]

ETH

_M

AC

_C

LK_

EN[1

0]

LCD

[0..1

0]

[13

]

ETH

_EG

P[0

..7]

[10

]

Tit

le

ve

Rt

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o rP

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S

te

eh

S:

eta

Do

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SC-9

00

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GA

X1

PC

I EX

PR

ESS

Car

d1

.0

Co

nfi

gu

rati

on

/To

p B

ank

C

21

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

X1

PC

I EX

PR

ESS

Car

d1

.0

Co

nfi

gu

rati

on

/To

p B

ank

C

21

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

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GA

X1

PC

I EX

PR

ESS

Car

d1

.0

Co

nfi

gu

rati

on

/To

p B

ank

C

21

4

FROM ISPVM CABLE

This LED

indicates activity

on TDI.

FPGA RESETN/GSRN

PROGRAMN

SPI3 MODE SETTING

DONE indicator will light when

configuration is successfully

completed

INITN indicator will light

if an error occurs during

configuration programming

FLASH1

FLASH0

Top

BANK1

SC-900FPBGA

U1

K

SC2

5-9

00

fpB

GA

Top

BANK1

SC-900FPBGA

U1

K

SC2

5-9

00

fpB

GA

PT

23

D/D

14

/MP

IWR

DA

TA

14

E1

2

PT

47

C/D

10

/MP

IWR

DA

TA

10

A1

9

PT

47

D/D

9/M

PIW

RD

AT

A9

A2

0

PT

49

B/D

8/M

PIW

RD

AT

A8

B2

0

PT

23

A/D

15

/MP

IWR

DA

TA

15

G9

PT

25

A/A

17

/MP

IAD

DR

31

D1

3

PT

25

B/A

15

/MP

IAD

DR

29

D1

4

PT

25

D/A

16

/MP

IAD

DR

30

G1

2

PT

27

A/A

14

/MP

IAD

DR

28

E1

3

PT

27

B/A

13

/MP

IAD

DR

27

E1

4

PT

28

A/A

12

/MP

IAD

DR

26

A1

3

PT

28

B/A

11

/MP

IAD

DR

25

A1

4

PT

29

A/A

10

/MP

IAD

DR

24

F14

PT

29

B/A

9/M

PIA

DD

R2

3G

14

PT

31

A/A

8/M

PIA

DD

R2

2B

13

PT

31

B/A

7/M

PIA

DD

R2

1B

14

PT

32

A/A

6/M

PIA

DD

R2

0C

13

PT

32

B/A

5/M

PIA

DD

R1

9C

14

PT

33

A/A

4/M

PIA

DD

R1

8D

15

PT

33

B/A

3/M

PIA

DD

R1

7E

15

PT

33

C/A

2/M

PIA

DD

R1

6F1

5

PT

33

D/A

1/M

PIA

DD

R1

5G

15

PT

35

A/A

0/M

PIA

DD

R1

4A

15

PT

27

D/D

11

/MP

IWR

DA

TA

11

G1

3P

T2

7C

/D1

2/M

PIW

RD

AT

A1

2H

13

PT

25

C/D

13

/MP

IWR

DA

TA

13

G1

1

PT

43

B/D

0/M

PIW

RD

AT

A0

B1

8

PT

45

A/D

1/M

PIW

RD

AT

A1

G1

7

PT

45

B/D

2/M

PIW

RD

AT

A2

G1

8

PT

45

C/D

3/M

PIW

RD

AT

A3

E1

6

PT

45

D/D

4/M

PIW

RD

AT

A4

E1

7

PT

46

A/D

5/M

PIW

RD

AT

A5

C1

7

PT

46

B/D

6/M

PIW

RD

AT

A6

C1

8

PT

46

C/D

7/M

PIW

RD

AT

A7

F18

PT

23

B/A

21

/MP

IBU

RS

TG

10

PT

23

C/D

P1

/MP

IWR

PA

RIT

Y1

D1

2

PT

24

C/A

20

/MP

IBD

IPF1

3

PT

24

A/M

PIT

EA

N/M

PIT

EA

B1

1

PT

24

B/A

18

/MP

ITS

IZ0

B1

2

PT

24

D/A

19

/MP

ITS

IZ1

F12

PT

46

D/W

RN

/MP

IRW

NF1

9

PT

47

A/R

DN

/MP

IST

RB

ND

18

PT

38

B/D

P0

/MP

IWR

PA

RIT

Y0

C1

6P

T3

8A

/MP

IAC

KN

/MP

ITA

C1

5

PT

37

A/M

PIC

LK/P

CLK

T1

_0

/MP

ICLK

B1

5

PT

35

B/M

PIR

TR

YN

/MP

IRE

TR

YA

16

PT

49

A/C

S1

/CS

1B

19

PT

47

B/C

S0

N/C

S0

ND

19

PT

35

D/D

P3

/PC

LKC

1_

4/M

PIW

RP

AR

ITY

3H

16

PT

42

D/V

RE

F2_

1G

16

PT

31

C/V

RE

F1_

1H

14

PT

37

B/P

CLK

C1

_0

B1

6

PT

38

D/E

XT

DO

NE

OF1

7

PT

39

A/E

XT

CLK

P2

ID

16

PT

39

B/E

XT

CLK

P2

OD

17

PT

41

A/E

XT

CLK

P1

IH

17

PT

41

B/E

XT

CLK

P1

OH

18

PT

42

A/E

XT

DO

NE

IA

17

R10 4_7K-0603SMTR10 4_7K-0603SMT

RN1D

EXB

V8

V4

72

JV

4.7

K

RN1D

EXB

V8

V4

72

JV

4.7

K

4 5

R24_7K-0603SMT

R24_7K-0603SMT R11

10K-0603SMTR11

10K-0603SMT

R3

01

0K

-06

03

SMT

R3

01

0K

-06

03

SMT

U7

B

SN7

4LV

C1

25

A/S

O1

4

U7

B

SN7

4LV

C1

25

A/S

O1

4

3Y

83

A9

3O

E_

N1

0

4Y

11

4A

12

4O

E_

N1

3

VCC14

R9 4_7K-0603SMTR9 4_7K-0603SMT

SW3

B3

F-1

15

0M

om

en

tary

Sw

itch

SW3

B3

F-1

15

0M

om

en

tary

Sw

itch

13

24

PP

2P

P2

12

R4

10K-0603SMT

R4

10K-0603SMT

C1

100NF-0603SMT

C1

100NF-0603SMT

U6

NC

7W

Z1

6-M

AC

O6

A/F

airc

hild

Tin

yLo

gic

U6

NC

7W

Z1

6-M

AC

O6

A/F

airc

hild

Tin

yLo

gic

IN A

11

GND 2

IN A

23

OU

T Y

24

VCC5

OU

T Y

16

R27100R-0603SMT

R27100R-0603SMT

R2

2

68

0R

-06

03

SMT

R2

2

68

0R

-06

03

SMT

R134_7K-0603SMT

R134_7K-0603SMT

RN1C

4.7

K

RN1C

4.7

K

3 6

R24

220R-0603SMT

R24

220R-0603SMT

SC-900FPBGA

U1

I

SC2

5-9

00

fpB

GA

SC-900FPBGA

U1

I

SC2

5-9

00

fpB

GA

CC

LKF2

5

DO

NE

G6

INIT

NG

5

M0

F5

M1

F6

M2

F4

M3

E4

RD

CFG

NH

6

RE

SE

TN

H5

TC

KG

25

TD

IG

24

TD

OH

25

TEMP AD5

TM

SJ2

6

PR

OG

RA

MN

F26

PT

42

B/D

OU

TA

18

PT

49

C/L

DC

NF2

2

PT

49

D/H

DC

G2

2

PT

38

C/R

DY

F16

PT

43

A/Q

OU

TB

17

MP

IIRQ

NH

24

R64_7K-0603SMT

R64_7K-0603SMT

PP

3P

P3

12

R28

4_7K-0603SMT

R28

4_7K-0603SMT

R84_7K-0603SMT

R84_7K-0603SMT

VCC

GND

TDO

TDI

ispEN_N

NC

TMS

TCK

DONE

INITN

J3 HEA

DER

10

VCC

GND

TDO

TDI

ispEN_N

NC

TMS

TCK

DONE

INITN

J3 HEA

DER

10

12 3 4 5 6

7

8 91

0

C2

10NF-0603SMT

C2

10NF-0603SMT

U4

M2

5P

80

-FLA

SH

U4

M2

5P

80

-FLA

SH

S#

1

Q2

W#

3

GN

D4

VC

C8

HO

LD#

7

CLK

6

DI

5

R2

5

0R

-06

03

SMT

R2

5

0R

-06

03

SMT

Y

D3

LED

-SM

T1

20

6_

RED

Y

D3

LED

-SM

T1

20

6_

RED

RN1A

4.7

K

RN1A

4.7

K

1 8

C4100NF-0603SMT

C4100NF-0603SMT

R D1

LED

-SM

T1

20

6_

GR

EEN

R D1

LED

-SM

T1

20

6_

GR

EEN

C5

100NF-0603SMT

C5

100NF-0603SMT

U5

MA

X6

81

7

U5

MA

X6

81

7

IN1

1

GND 2

IN2

3

OU

T2

4

VCC5

OU

T1

6

R16

4_7K-0603SMT

R16

4_7K-0603SMT

U3

M2

5P

64

-FLA

SH(N

OB

)

U3

M2

5P

64

-FLA

SH(N

OB

)

S#

7

Q8

DU

13

DU

24

VC

C2

HO

LD#

1

DU

46

DU

35

W#

9V

SS

10

DU

51

1D

U6

12

DU

71

3D

U8

14

D1

5C

K1

6

C7

100NF-0603SMT

C7

100NF-0603SMT

Y

D4

LED

-SM

T1

20

6_

RED

Y

D4

LED

-SM

T1

20

6_

RED

R2

36

80

R-0

60

3SM

TR

23

68

0R

-06

03

SMT

C6

100NF-0603SMT

C6

100NF-0603SMT

SW1

TD

A1

0H

0SK

1

SW1

TD

A1

0H

0SK

1

11

22

33

44

55

66

77

88

99

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

R15 4_7K-0603SMTR15 4_7K-0603SMT

R2

0

4_7K-0603SMT

R2

0

4_7K-0603SMT

G

D5

LED-SMT1206_GREEN

G

D5

LED-SMT1206_GREENR1

7

BO

UR

NS-

32

24

W-1

0K

R1

7

BO

UR

NS-

32

24

W-1

0K

R1

82

20

R-0

60

3SM

TR

18

22

0R

-06

03

SMT

R1210K-0603SMT

R1210K-0603SMT

RN1B

4.7

K

RN1B

4.7

K

2 7

SW2

B3

F-1

15

0M

om

en

tary

Sw

itch

SW2

B3

F-1

15

0M

om

en

tary

Sw

itch

13

24

U7

A

SN7

4LV

C1

25

A/S

O1

4

U7

A

SN7

4LV

C1

25

A/S

O1

4

1O

E_

N1

1A

21

Y3

2O

E_

N4

2A

52

Y6

GND 7

U2

M2

5P

80

-FLA

SH

U2

M2

5P

80

-FLA

SH

S#

1

Q2

W#

3

GN

D4

VC

C8

HO

LD#

7

CLK

6

DI

5

R14 4_7K-0603SMTR14 4_7K-0603SMT

C3

100NF-0603SMT

C3

100NF-0603SMT

J2 HEA

DER

4

J2 HEA

DER

4

1234

R

D2

LED

-SM

T1

20

6_

RED

R

D2

LED

-SM

T1

20

6_

RED

Q1

2N

22

22

/SO

T2

3Q1

2N

22

22

/SO

T2

3

3

1

2

R34_7K-0603SMT

R34_7K-0603SMT

R7470R-0603SMT

R7470R-0603SMT

R1

9

4_7K-0603SMT

R1

9

4_7K-0603SMT

R5470R-0603SMT

R5470R-0603SMT

PP

1P

P1

12

R294_7K-0603SMT

R294_7K-0603SMT

R2

1

68

0R

-06

03

SMT

R2

1

68

0R

-06

03

SMT

R26

100R-0603SMT

R26

100R-0603SMT

R14_7K-0603SMT

R14_7K-0603SMT

U8

NC

7W

Z1

6-M

AC

O6

A/F

airc

hild

Tin

yLo

gic

U8

NC

7W

Z1

6-M

AC

O6

A/F

airc

hild

Tin

yLo

gic

IN A

11

GND 2

IN A

23

OU

T Y

24

VCC5

OU

T Y

16

J1 JUM

PER

1

J1 JUM

PER

1

12

19

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 6. Power Supplies

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VR

EF_

REG

1

VR

EF_

REG

2

PROBE_VCC

VC

C_

CO

RE

1_

8V

2_

5V

2_

5V

1_

8V

1_

8V

SC_

QD

R_

VT

T

2_

5V

VC

C_

CO

RE

2_

5V

1_

8V

SC_

QD

R_

VT

T

3_

3V

3_

3V

2_

5V

1_

8V

1_

8V

SC_

RLD

RA

M_

VT

T

SC_

RLD

RA

M_

VT

T

VC

CIO

1

2_

5V

2_

5V

SC_

RLD

RA

M_

VT

T

2_

5V

SC_

QD

R_

VT

T

1_

2V

DD

A

SC_

QD

R_

VR

EF[1

2]

SC_

RLD

RA

M_

VR

EF[1

2]

PR

OB

E_V

CC

[4]

Tit

le

ve

Rt

cej

orP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Po

wer

Su

pp

lies

C

31

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Po

wer

Su

pp

lies

C

31

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Po

wer

Su

pp

lies

C

31

4

1.8V PROBE POINT

VCC12 PROBE POINT

VCCAUX PROBE POINT

0.9V VTT PROBE POINT

VCCIO1 SELECT

VCCIO1PROBE POINT

0.9V VTT PROBE POINT

2.5V PROBE POINT

BANK 2, 3, 4, 5, 6

VCCIO = 1.8V

BANK 7

VCCIO = 2.5V

+C

53

22UF-16V_TANTBSMT

+C

53

22UF-16V_TANTBSMT

C6

6

10

NF-

06

03

SMT

C6

6

10

NF-

06

03

SMT

C1

5

10

0N

F-0

60

3SM

T

C1

5

10

0N

F-0

60

3SM

T

PP

8P

P8

1 2

VCC SC-900FPBGA

U1

E

SC2

5-9

00

fpB

GA

VCC SC-900FPBGA

U1

E

SC2

5-9

00

fpB

GA

VC

CL1

0

VC

CL2

1

VC

CM

10

VC

CM

21

VC

CN

10

VC

CN

21

VC

CP

10

VC

CP

21

VC

CU

10

VC

CU

21

VC

CV

10

VC

CV

21

VC

CW

10

VC

CW

21

VC

CY

10

VC

CY

21

VC

CK

10

VC

CK

11

VC

CK

12

VC

CK

13

VC

CK

14

VC

CK

17

VC

CK

18

VC

CK

19

VC

CK

20

VC

CA

A1

0

VC

CA

A1

1

VC

CA

A1

2

VC

CA

A1

3

VC

CA

A1

4

VC

CA

A1

7

VC

CA

A1

8

VC

CA

A1

9

VC

CA

A2

0

VC

CA

A2

1

VC

CA

A2

2

VC

CA

A9

VC

CA

B1

0

VC

CA

B2

1

VC

CJ1

0

VC

CJ2

1

VC

CJ2

2

VC

CJ9

VC

CK

22

VC

CK

9

VC

CK

21

C8

1

10

0N

F-0

60

3SM

T

C8

1

10

0N

F-0

60

3SM

T

C7

5

10

0N

F-0

60

3SM

T

C7

5

10

0N

F-0

60

3SM

T

PP

10

PP

10

1 2

C5

1

1UF-16V-0805SMT

C5

1

1UF-16V-0805SMT

C1

07

10

NF-

06

03

SMT

C1

07

10

NF-

06

03

SMT

C1

12

10

0N

F-0

60

3SM

T

C1

12

10

0N

F-0

60

3SM

T

PP

6P

P6

1 2

C31

10NF-0603SMT

C31

10NF-0603SMT

R33 4_7K-0603SMTR33 4_7K-0603SMT

+C

33

22UF-16V_TANTBSMT

+C

33

22UF-16V_TANTBSMT

R3

5

0R

-06

03

SMT

R3

5

0R

-06

03

SMT

R4

7O

PEN

-06

03

SMT

R4

7O

PEN

-06

03

SMT

C8

4

10

0N

F-0

60

3SM

T

C8

4

10

0N

F-0

60

3SM

T

C9

5

10

NF-

06

03

SMT

C9

5

10

NF-

06

03

SMT

C2

3

10

NF-

06

03

SMT

C2

3

10

NF-

06

03

SMT

C1

14

10

0N

F-0

60

3SM

T

C1

14

10

0N

F-0

60

3SM

T

C9

3

10

NF-

06

03

SMT

C9

3

10

NF-

06

03

SMT

C6

1

10

0N

F-0

60

3SM

T

C6

1

10

0N

F-0

60

3SM

T

C4

3

10

NF-

06

03

SMT

C4

3

10

NF-

06

03

SMT

+C

21

22UF-16V_TANTBSMT

+C

21

22UF-16V_TANTBSMT

C8

7

10

0N

F-0

60

3SM

T

C8

7

10

0N

F-0

60

3SM

TC

94

10

NF-

06

03

SMT

C9

4

10

NF-

06

03

SMT

C1

13

10

0N

F-0

60

3SM

T

C1

13

10

0N

F-0

60

3SM

T

VCCAUX

SC-900FPBGA

U1

L

SC2

5-9

00

fpB

GA

VCCAUX

SC-900FPBGA

U1

L

SC2

5-9

00

fpB

GA

VC

CA

UX

1H

12

VC

CA

UX

1H

11

VC

CA

UX

1H

20

VC

CA

UX

1H

19

VC

CA

UX

2M

23

VC

CA

UX

2N

24

VC

CA

UX

2M

24

VC

CA

UX

2N

23

VC

CA

UX

3U

23

VC

CA

UX

3V

23

VC

CA

UX

3V

24

VC

CA

UX

3U

24

VC

CA

UX

3W

24

VC

CA

UX

3W

23

VC

CA

UX

4A

C1

8

VC

CA

UX

4A

C1

7

VC

CA

UX

4A

D1

7

VC

CA

UX

4A

D1

8

VC

CA

UX

4A

C1

9

VC

CA

UX

4A

D1

9

VC

CA

UX

5A

C1

3

VC

CA

UX

5A

C1

4

VC

CA

UX

5A

C1

2

VC

CA

UX

5A

D1

3

VC

CA

UX

5A

D1

4

VC

CA

UX

5A

D1

2

VC

CA

UX

6V

7

VC

CA

UX

6V

8

VC

CA

UX

6U

7

VC

CA

UX

6U

8

VC

CA

UX

6W

8

VC

CA

UX

6W

7

VC

CA

UX

7M

7

VC

CA

UX

7N

8

VC

CA

UX

7M

8

VC

CA

UX

7N

7

C1

1

10

NF-

06

03

SMT

C1

1

10

NF-

06

03

SMT

C6

2

10

NF-

06

03

SMT

C6

2

10

NF-

06

03

SMT

R3

7

1K-0603SMT

R3

7

1K-0603SMT

C1

2

1UF-16V-0805SMT

C1

2

1UF-16V-0805SMT

C7

1

10

0N

F-0

60

3SM

T

C7

1

10

0N

F-0

60

3SM

T

C1

6

10

0N

F-0

60

3SM

T

C1

6

10

0N

F-0

60

3SM

T

R4

30

R-0

60

3SM

TR

43

0R

-06

03

SMT

C44

100NF-0603SMT

C44

100NF-0603SMT

C3

8

10

NF-

06

03

SMT

C3

8

10

NF-

06

03

SMT

PP

13

PP

13

1 2

C2

7

1UF-16V-0805SMT

C2

7

1UF-16V-0805SMT

C1

09

10

0N

F-0

60

3SM

T

C1

09

10

0N

F-0

60

3SM

T

J5 HEA

DER

3X

1

J5 HEA

DER

3X

1

112 2

33

C3

5

10

0N

F-0

60

3SM

T

C3

5

10

0N

F-0

60

3SM

T

R3

4

1K

_A

DJ/

SMT

3M

M

R3

4

1K

_A

DJ/

SMT

3M

M

R40 4_7K-0603SMTR40 4_7K-0603SMT

R3

9O

PEN

-06

03

SMT

R3

9O

PEN

-06

03

SMT

+

C45

47UF-16V_TANTBSMT

+

C45

47UF-16V_TANTBSMT

C2

4

10

NF-

06

03

SMT

C2

4

10

NF-

06

03

SMT

C6

8

10

NF-

06

03

SMT

C6

8

10

NF-

06

03

SMT

C4

2

10

0N

F-0

60

3SM

T

C4

2

10

0N

F-0

60

3SM

T

+C

19

22UF-16V_TANTBSMT

+C

19

22UF-16V_TANTBSMT

C8

100NF-0603SMT

C8

100NF-0603SMT

C8

6

10

0N

F-0

60

3SM

T

C8

6

10

0N

F-0

60

3SM

T

C7

7

10

0N

F-0

60

3SM

T

C7

7

10

0N

F-0

60

3SM

T

C8

0

10

0N

F-0

60

3SM

T

C8

0

10

0N

F-0

60

3SM

T

C4

1

10

0N

F-0

60

3SM

T

C4

1

10

0N

F-0

60

3SM

T

C1

01

10

NF-

06

03

SMT

C1

01

10

NF-

06

03

SMT

R4

10

R-0

80

5SM

TR

41

0R

-08

05

SMT

+C

14

22UF-16V_TANTBSMT

+C

14

22UF-16V_TANTBSMT

R4

6

0R

-06

03

SMT

R4

6

0R

-06

03

SMT

C9

0

10

NF-

06

03

SMT

C9

0

10

NF-

06

03

SMT

C3

9

10

0N

F-0

60

3SM

T

C3

9

10

0N

F-0

60

3SM

T

R3

1

1K-0603SMT

R3

1

1K-0603SMT

C47

1UF-16V-0805SMT

C47

1UF-16V-0805SMT

C1

02

10

NF-

06

03

SMT

C1

02

10

NF-

06

03

SMT

C26100NF-0603SMT

C26100NF-0603SMT

C1

15

10

0N

F-0

60

3SM

T

C1

15

10

0N

F-0

60

3SM

T

C1

7

10

0N

F-0

60

3SM

T

C1

7

10

0N

F-0

60

3SM

T

C48100NF-0603SMT

C48100NF-0603SMT

C25

1UF-16V-0805SMT

C25

1UF-16V-0805SMT

VCCIO

SC-900FPBGA

U1

C

SC2

5-9

00

fpB

GA

VCCIO

SC-900FPBGA

U1

C

SC2

5-9

00

fpB

GA

VC

CIO

1H

10

VC

CIO

1J2

0

VC

CIO

1J1

4

VC

CIO

1H

21

VC

CIO

1H

22

VC

CIO

1H

9

VC

CIO

1J1

1

VC

CIO

1J1

2

VC

CIO

1J1

3

VC

CIO

1J1

7

VC

CIO

1J1

5

VC

CIO

1J1

6

VC

CIO

1J1

8

VC

CIO

1J1

9

VC

CIO

1F2

0V

CC

IO1

C1

9V

CC

IO1

C1

2V

CC

IO1

F11

VC

CIO

2P

22

VC

CIO

2R

22

VC

CIO

2L2

3

VC

CIO

2L2

2

VC

CIO

2K

24

VC

CIO

2K

23

VC

CIO

2J2

4

VC

CIO

2N

22

VC

CIO

2M

22

VC

CIO

2J2

3

VC

CIO

2G

30

VC

CIO

2J2

9

VC

CIO

2K

27

VC

CIO

2N

25

VC

CIO

3T

22

VC

CIO

3A

B2

4

VC

CIO

3A

A2

3

VC

CIO

3A

A2

4

VC

CIO

3A

B2

3

VC

CIO

3Y

24

VC

CIO

3W

22

VC

CIO

3U

22

VC

CIO

3V

22

VC

CIO

3Y

22

VC

CIO

3Y

23

VC

CIO

3A

A2

6

VC

CIO

3A

A2

9

VC

CIO

3Y

28

VC

CIO

3A

C2

9

VC

CIO

4A

C2

2

VC

CIO

4A

C2

1

VC

CIO

4A

B1

6

VC

CIO

4A

B1

7

VC

CIO

4A

B1

8

VC

CIO

4A

B1

9

VC

CIO

4A

B2

0

VC

CIO

4A

C2

0

VC

CIO

4A

D2

1

VC

CIO

4A

D2

2

VC

CIO

4A

D2

0

VC

CIO

4A

G2

3

VC

CIO

4A

G2

0

VC

CIO

4A

J23

VC

CIO

4A

J26

VC

CIO

5A

H6

VC

CIO

5A

G1

1

VC

CIO

5A

J9

VC

CIO

5A

E7

VC

CIO

5A

D1

0

VC

CIO

5A

C9

VC

CIO

5A

C1

1

VC

CIO

5A

C1

0

VC

CIO

5A

B1

5

VC

CIO

5A

B1

4

VC

CIO

5A

B1

3

VC

CIO

5A

B1

2

VC

CIO

5A

B1

1

VC

CIO

5A

D9

VC

CIO

5A

D1

1

VC

CIO

6Y

9

VC

CIO

6W

9

VC

CIO

6Y

8

VC

CIO

6Y

7

VC

CIO

6T

9

VC

CIO

6A

B8

VC

CIO

6A

B7

VC

CIO

6A

A8

VC

CIO

6A

A7

VC

CIO

6V

9

VC

CIO

6U

9

VC

CIO

6A

A4

VC

CIO

6A

D1

VC

CIO

6A

B2

VC

CIO

6W

4

VC

CIO

7J8

VC

CIO

7K

7

VC

CIO

7J7

VC

CIO

7P

9

VC

CIO

7R

9

VC

CIO

7K

8

VC

CIO

7L8

VC

CIO

7H

4

VC

CIO

7L2

VC

CIO

7J2

VC

CIO

7N

6

VC

CIO

7N

4

VC

CIO

7H

2

VC

CIO

7N

9

VC

CIO

7M

9

VC

CIO

7L9

C8

5

10

0N

F-0

60

3SM

T

C8

5

10

0N

F-0

60

3SM

TC

96

10

NF-

06

03

SMT

C9

6

10

NF-

06

03

SMT

C1

08

10

NF-

06

03

SMT

C1

08

10

NF-

06

03

SMT

C7

0

10

NF-

06

03

SMT

C7

0

10

NF-

06

03

SMT

C20

100NF-0603SMT

C20

100NF-0603SMT

C7

9

10

0N

F-0

60

3SM

T

C7

9

10

0N

F-0

60

3SM

T

U9

LP2

99

6-S

O8

U9

LP2

99

6-S

O8

GND 1

SD

2

VS

EN

SE

3V

RE

F4

VD

DQ

5

AVIN6

PVIN7

VT

T8

+

C9

47UF-16V_TANTBSMT

+

C9

47UF-16V_TANTBSMT

+C

50

100UF-FKSMT

+C

50

100UF-FKSMT

C8

8

10

0N

F-0

60

3SM

T

C8

8

10

0N

F-0

60

3SM

T

C1

17

10

0N

F-0

60

3SM

T

C1

17

10

0N

F-0

60

3SM

T

C6

4

10

NF-

06

03

SMT

C6

4

10

NF-

06

03

SMT

R381K-0603SMT

R381K-0603SMT

C7

3

10

0N

F-0

60

3SM

T

C7

3

10

0N

F-0

60

3SM

T

C46

100NF-0603SMT

C46

100NF-0603SMT

DP

1D

P1

1

2

3

C5

5

10

0N

F-0

60

3SM

T

C5

5

10

0N

F-0

60

3SM

T

PP

7P

P7

1 2

C1

11

10

0N

F-0

60

3SM

T

C1

11

10

0N

F-0

60

3SM

T

C9

8

10

NF-

06

03

SMT

C9

8

10

NF-

06

03

SMT

R3

6

0R

-06

03

SMT

R3

6

0R

-06

03

SMT

+C

32

100UF-FKSMT

+C

32

100UF-FKSMT

J4 JUM

PER

1

J4 JUM

PER

1

12

C1

0

10

0N

F-0

60

3SM

T

C1

0

10

0N

F-0

60

3SM

T

C5

6

10

NF-

06

03

SMT

C5

6

10

NF-

06

03

SMT

PP

11

PP

11

1 2

C1

00

10

NF-

06

03

SMT

C1

00

10

NF-

06

03

SMT

C49

10NF-0603SMT

C49

10NF-0603SMT

C9

2

10

NF-

06

03

SMT

C9

2

10

NF-

06

03

SMT

C2

9

1UF-16V-0805SMT

C2

9

1UF-16V-0805SMT

C18

100NF-0603SMT

C18

100NF-0603SMT

SC-900FPBGA

U1

G

SC2

5-9

00

fpB

GA

SC-900FPBGA

U1

G

SC2

5-9

00

fpB

GA

NC

1M

4

NC

2P

5

NC

3J3

NC

4A

B3

NC

5A

H9

NC

6A

G7

NC

7A

K2

7

NC

8A

J24

NC

9A

A2

8

NC

10

P2

4

NC

11

K2

8

NC

12

P2

3

NC

13

L28

NC

14

E1

9

NC

15

G2

1

NC

16

G2

0

NC

17

G1

9

NC

18

F9

NC

19

A1

1

NC

20

G7

NC

21

AC

16

NC

22

AB

30

NC

23

AF1

2

NC

24

AG

10

C6

3

10

NF-

06

03

SMT

C6

3

10

NF-

06

03

SMT

PP

12

PP

12

1 2

PP

4P

P4

1 2

C1

03

10

NF-

06

03

SMT

C1

03

10

NF-

06

03

SMT

R4

5

0R

-06

03

SMT

R4

5

0R

-06

03

SMT

C6

9

10

NF-

06

03

SMT

C6

9

10

NF-

06

03

SMT

C7

2

10

0N

F-0

60

3SM

T

C7

2

10

0N

F-0

60

3SM

T

C7

8

10

0N

F-0

60

3SM

T

C7

8

10

0N

F-0

60

3SM

T

C8

2

10

0N

F-0

60

3SM

T

C8

2

10

0N

F-0

60

3SM

T

C5

7

10

0N

F-0

60

3SM

T

C5

7

10

0N

F-0

60

3SM

T

C1

06

10

NF-

06

03

SMT

C1

06

10

NF-

06

03

SMT

PP

9P

P9

1 2

C1

10

10

0N

F-0

60

3SM

T

C1

10

10

0N

F-0

60

3SM

T

R4

8

1K-0603SMT

R4

8

1K-0603SMT

SC-900FPBGA

U1

H

SC2

5-9

00

fpB

GA

SC-900FPBGA

U1

H

SC2

5-9

00

fpB

GA

VT

T_

2L2

4

VT

T_

2T

23

VT

T_

3A

C2

4

VT

T_

3T

25

VT

T_

3W

25

VT

T_

4A

D2

4

VT

T_

4A

E1

7

VT

T_

4A

E1

8

VT

T_

5A

C1

5

VT

T_

5A

D1

6

VT

T_

5A

E9

VT

T_

6A

A6

VT

T_

6T

7

VT

T_

6W

6

VT

T_

7L7

VT

T_

7P

7

C1

3

10

0N

F-0

60

3SM

T

C1

3

10

0N

F-0

60

3SM

T

C8

3

10

0N

F-0

60

3SM

T

C8

3

10

0N

F-0

60

3SM

T

C1

16

10

0N

F-0

60

3SM

T

C1

16

10

0N

F-0

60

3SM

T

R3

20

R-0

60

3SM

TR

32

0R

-06

03

SMT

C5

8

10

NF-

06

03

SMT

C5

8

10

NF-

06

03

SMT

R4

41

K_

AD

J/SM

T3

MM

R4

41

K_

AD

J/SM

T3

MM

C8

9

10

0N

F-0

60

3SM

T

C8

9

10

0N

F-0

60

3SM

T

+C

52

10UF-16V_TANTBSMT

+C

52

10UF-16V_TANTBSMT

C4

0

10

NF-

06

03

SMT

C4

0

10

NF-

06

03

SMT

C9

1

10

NF-

06

03

SMT

C9

1

10

NF-

06

03

SMT

C3

6

10

NF-

06

03

SMT

C3

6

10

NF-

06

03

SMT

SC-900FPBGA

AG

Bpf

00

9-5

2C

SD

1U

SC-900FPBGA

AG

Bpf

00

9-5

2C

SD

1U

VC

C1

P2

AB

9

VC

C1

P2

AC

8

VC

C1

P2

H2

3

VC

C1

P2

H1

5

VC

C1

P2

AC

23

VC

C1

P2

R2

3

VC

C1

P2

AB

22

VC

C1

P2

T8

VC

C1

P2

H8

VC

CJ

J25

VC

CL_

LLC

_A

AG

4V

CC

L_LL

C_

BA

F5V

CC

L_LR

C_

AA

G2

7V

CC

L_LR

C_

BA

F26

VC

CL_

ULC

_A

E5

VC

CL_

ULC

_B

D4

VC

CL_

UR

C_

AE

26

VC

CL_

UR

C_

BD

27

XRES AE4

PROBE_GND AE28

PROBE_VCC AD27

C1

05

10

NF-

06

03

SMT

C1

05

10

NF-

06

03

SMT

PP

5P

P5

1 2

C9

7

10

NF-

06

03

SMT

C9

7

10

NF-

06

03

SMT

C5

9

10

0N

F-0

60

3SM

T

C5

9

10

0N

F-0

60

3SM

T

C9

9

10

NF-

06

03

SMT

C9

9

10

NF-

06

03

SMT

R4

2

1K-0603SMT

R4

2

1K-0603SMT

C2

2

10

NF-

06

03

SMT

C2

2

10

NF-

06

03

SMT

C3

4

1UF-16V-0805SMT

C3

4

1UF-16V-0805SMT

C5

4

1UF-16V-0805SMT

C5

4

1UF-16V-0805SMT

+C

30

10UF-16V_TANTBSMT

+C

30

10UF-16V_TANTBSMT

C6

5

10

NF-

06

03

SMT

C6

5

10

NF-

06

03

SMT

U1

0

LP2

99

6-S

O8

U1

0

LP2

99

6-S

O8

GND 1

SD

2

VS

EN

SE

3V

RE

F4

VD

DQ

5

AVIN6

PVIN7

VT

T8

C2

8

1UF-16V-0805SMT

C2

8

1UF-16V-0805SMT

C6

7

10

NF-

06

03

SMT

C6

7

10

NF-

06

03

SMT

C7

4

10

0N

F-0

60

3SM

T

C7

4

10

0N

F-0

60

3SM

T

C7

6

10

0N

F-0

60

3SM

T

C7

6

10

0N

F-0

60

3SM

T

C6

0

10

NF-

06

03

SMT

C6

0

10

NF-

06

03

SMT

C3

7

10

0N

F-0

60

3SM

T

C3

7

10

0N

F-0

60

3SM

T

C1

04

10

NF-

06

03

SMT

C1

04

10

NF-

06

03

SMT

20

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 7. DC/DC Conversion5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

2_5_TRIM

CORE_TRIM

1_2_TRIM3_3_TRIM

12

_0

V

2_

5V

3_

3V

12

_0

V

VC

C_

CO

RE

1_

5V

2_

5V

12

_0

V

1_

2V

1_

8V

12

_0

V1

2_

0V

VC

C_

CO

RE

3_

3V

IN

12

_0

V

1_

8V

1_

5V

1_

2V

3_

3V

IN3_

3V

IN

12

_0

V

12

_0

V

12

_0

V

12

_0

V

3_

3V

IN3

_3

V

12

_0

V1

2_

0V

1_

2V

DD

A

PR

OB

E_V

CC

[3]

Tit

le

ve

Rt

cej

orP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

DC

/DC

Co

nve

rsio

n

C

41

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

DC

/DC

Co

nve

rsio

n

C

41

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

DC

/DC

Co

nve

rsio

n

C

41

4

GN

D P

ads

Dis

trib

ute

d a

rou

nd

th

e b

oar

d

2.5

V

PO

WER

RA

IL G

OO

D IN

DIC

AT

OR

S

VC

CC

OR

E

V5.

2V

8.1

3.3

V1

.2V

1.5

V

SC VC

C_

CO

RE

1.8

V1.5

V

1.2

V

12

VIN

PU

TG

OO

D

+12VDC

GND

3.3

V

4.32K Typical

SET VALUE

1V= 36.5K

1.2V=17.4K

PO

WER

INP

UT

VCC12 power supply must always

be higher than VCC Core,

or if lower, then well within 150mV

of VCC Core

C1

37

22

UF-

16

V_

TA

NT

BSM

TC1

37

22

UF-

16

V_

TA

NT

BSM

T

R5

04

70

R-1

20

6SM

TR

50

47

0R

-12

06

SMT

TP

2

TES

TP

OIN

T

TP

2

TES

TP

OIN

T1

C1

28 100NF-0603SMT

C1

28 100NF-0603SMT

R8

1O

PEN

-08

05

SMT

R8

1O

PEN

-08

05

SMT

R7

9

0R

-06

03

SMT

R7

9

0R

-06

03

SMT

FB1

BLM

41

PG

60

0SN

1

FB1

BLM

41

PG

60

0SN

1

R8

3

12

4R

-06

03

SMT

R8

3

12

4R

-06

03

SMT

R5

51

50

R-0

60

3SM

TR

55

15

0R

-06

03

SMT

R5

41

00

R-0

60

3SM

TR

54

10

0R

-06

03

SMT

G

D6

LED

-SM

T1

20

6_

GR

EEN

G

D6

LED

-SM

T1

20

6_

GR

EEN

TP

12

TES

TP

OIN

T

TP

12

TES

TP

OIN

T1

R7

51

5_

4K

-06

03

SMT

R7

51

5_

4K

-06

03

SMT

TP

3

TES

TP

OIN

T

TP

3

TES

TP

OIN

T1

R6

6

OP

EN-0

60

3SM

T

R6

6

OP

EN-0

60

3SM

T

R6

5

12

4R

-06

03

SMT

R6

5

12

4R

-06

03

SMT

TB

1

Te

rmin

al B

lock

/ED

12

02

DS

TB

1

Te

rmin

al B

lock

/ED

12

02

DS

1 2

U1

3

PT

H1

20

60

W

U1

3

PT

H1

20

60

W

GN

D1

VIN

2

INHIBIT# 3

ADJUST 4

SE

NS

E5

VO

UT

6

GND 7TRACK8

MDWN9

MUP10

R6

7O

PEN

-08

05

SMT

R6

7O

PEN

-08

05

SMT

C1

35

10

UF-

16

V_

TA

NT

BSM

TC

13

51

0U

F-1

6V

_T

AN

TB

SMT

TP

7

TES

TP

OIN

T

TP

7

TES

TP

OIN

T1

F3 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

F3 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

C1

36

100NF-0603SMT

C1

36

100NF-0603SMT

R8

56

8K

-06

03

SMT

R8

56

8K

-06

03

SMT

R7

61

00

K-0

60

3SM

TR

76

10

0K

-06

03

SMT

TP

11

TES

TP

OIN

T

TP

11

TES

TP

OIN

T1

C1

38 100NF-0603SMT

C1

38 100NF-0603SMT

C1

22

10

UF-

16

V_

TA

NT

BSM

TC

12

21

0U

F-1

6V

_T

AN

TB

SMT

C1

30

1UF-16V-0805SMT

C1

30

1UF-16V-0805SMT

U1

4

PT

H1

20

60

W

U1

4

PT

H1

20

60

W

GN

D1

VIN

2

INHIBIT# 3

ADJUST 4

SE

NS

E5

VO

UT

6

GND 7TRACK8

MDWN9

MUP10

R86

56R-0603SMT

R86

56R-0603SMT

C1

33

10

UF-

16

V_

TA

NT

BSM

TC

13

31

0U

F-1

6V

_T

AN

TB

SMT

+C1

34

33

0U

F-FK

SMT

+C1

34

33

0U

F-FK

SMT

TP

10

TES

TP

OIN

T

TP

10

TES

TP

OIN

T1

R6

20

R-0

80

5SM

TR

62

0R

-08

05

SMT

U1

6 AM

S15

03

CT

U1

6 AM

S15

03

CT

VP

OW

ER

5

VC

ON

TR

OL

4O

UT

PU

T3

AD

JUS

T_

GN

D2

SE

NS

E1

C1

27

22

UF-

16

V_

TA

NT

BSM

TC1

27

22

UF-

16

V_

TA

NT

BSM

T

R6

01

00

K-0

60

3SM

TR

60

10

0K

-06

03

SMT

C1

31

10

UF-

16

V_

TA

NT

BSM

TC

13

11

0U

F-1

6V

_T

AN

TB

SMT

J8 JUM

PER

1

J8 JUM

PER

1

12

+C

11

84

70

UF-

FKSM

T

+C

11

84

70

UF-

FKSM

T

R6

3

0R

-06

03

SMT

R6

3

0R

-06

03

SMT

R8

7

BO

UR

NS-

32

24

W-1

0K

R8

7

BO

UR

NS-

32

24

W-1

0K

C1

25

10

UF-

16

V_

TA

NT

BSM

TC

12

51

0U

F-1

6V

_T

AN

TB

SMT

F4 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

F4 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

+C1

24

33

0U

F-FK

SMT

+C1

24

33

0U

F-FK

SMT

R7

8

0R

-06

03

SMT

R7

8

0R

-06

03

SMT

R7

22

4K

-06

03

SMT

R7

22

4K

-06

03

SMT

TP

8

TES

TP

OIN

T

TP

8

TES

TP

OIN

T1

F2 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

F2 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

+C

11

91

00

UF-

FKSM

T

+C

11

91

00

UF-

FKSM

T

F1 F12

51

CT

-ND

10

A F

ast-

Blo

SM

T S

ock

ete

d F

use

F1 F12

51

CT

-ND

10

A F

ast-

Blo

SM

T S

ock

ete

d F

use

G

D8

LED

-SM

T1

20

6_

GR

EEN

G

D8

LED

-SM

T1

20

6_

GR

EEN

+C1

32

33

0U

F-FK

SMT

+C1

32

33

0U

F-FK

SMT

Q5

2N

22

22

/SO

T2

3Q

52

N2

22

2/S

OT

23

3

1

2

R6

8

OP

EN-0

80

5SM

T

R6

8

OP

EN-0

80

5SM

T

R5

14

70

R-1

20

6SM

TR

51

47

0R

-12

06

SMT

J6

22

HP

03

7-2

.1m

m P

CM

ale

Po

we

r Ja

ck 2

.1m

mJ6

22

HP

03

7-2

.1m

m P

CM

ale

Po

we

r Ja

ck 2

.1m

m1

3

2

R5

6

10

K-0

60

3SM

T

R5

6

10

K-0

60

3SM

T

R7

3

BO

UR

NS-

32

24

W-2

K

R7

3

BO

UR

NS-

32

24

W-2

K

G

D9

LED

-SM

T1

20

6_

GR

EEN

G

D9

LED

-SM

T1

20

6_

GR

EEN

U1

2 AM

S15

03

CT

U1

2 AM

S15

03

CT

VP

OW

ER

5

VC

ON

TR

OL

4O

UT

PU

T3

AD

JUS

T_

GN

D2

SE

NS

E1

R6

11

00

K-0

60

3SM

TR

61

10

0K

-06

03

SMT

R4

9

47

0R

-12

06

SMTR4

9

47

0R

-12

06

SMT

R7

4

1_

8K

-06

03

SMT

R7

4

1_

8K

-06

03

SMT

R5

7

10

K-0

60

3SM

T

R5

7

10

K-0

60

3SM

T

R8

2O

PEN

-08

05

SMT

R8

2O

PEN

-08

05

SMT

Q4

2N

22

22

/SO

T2

3Q

42

N2

22

2/S

OT

23

3

1

2

R7

0

BO

UR

NS-

32

24

W-1

0K

R7

0

BO

UR

NS-

32

24

W-1

0K

TP

9

TES

TP

OIN

T

TP

9

TES

TP

OIN

T1

TP

5

TES

TP

OIN

T

TP

5

TES

TP

OIN

T1

G

D1

0

LED

-SM

T1

20

6_

GR

EEN

G

D1

0

LED

-SM

T1

20

6_

GR

EEN

+C1

20

33

0U

F-FK

SMT

+C1

20

33

0U

F-FK

SMT

G

D7

LED

-SM

T1

20

6_

GR

EEN

G

D7

LED

-SM

T1

20

6_

GR

EEN

R8

9

BO

UR

NS-

32

24

W-5

K

R8

9

BO

UR

NS-

32

24

W-5

K

R69

27R-0603SMT

R69

27R-0603SMT

+C

12

9

22UF-16V_TANTBSMT

+C

12

9

22UF-16V_TANTBSMT

Q2

2N

22

22

/SO

T2

3Q

22

N2

22

2/S

OT

23

3

1

2

R8

4

BO

UR

NS-

32

24

W-1

0K

R8

4

BO

UR

NS-

32

24

W-1

0K

C1

23

10

UF-

16

V_

TA

NT

BSM

TC

12

31

0U

F-1

6V

_T

AN

TB

SMT

F6 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

F6 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

TP

1

TES

TP

OIN

T

TP

1

TES

TP

OIN

T1

C1

26

100NF-0603SMT

C1

26

100NF-0603SMT

TP

6

TES

TP

OIN

T

TP

6

TES

TP

OIN

T1

G

D1

1

LED

-SM

T1

20

6_

GR

EEN

G

D1

1

LED

-SM

T1

20

6_

GR

EEN

R7

71

00

K-0

60

3SM

TR

77

10

0K

-06

03

SMT

TP

4

TES

TP

OIN

T

TP

4

TES

TP

OIN

T1

R5

9

10

K-0

60

3SM

T

R5

9

10

K-0

60

3SM

T

R8

82

_2

K-0

60

3SM

TR

88

2_

2K

-06

03

SMT

G

D1

2LE

D-S

MT

12

06

_G

REE

N

G

D1

2LE

D-S

MT

12

06

_G

REE

N

R7

1

BO

UR

NS-

32

24

W-1

0K

R7

1

BO

UR

NS-

32

24

W-1

0K

R5

24

70

R-1

20

6SM

TR

52

47

0R

-12

06

SMT

C1

21

10

UF-

16

V_

TA

NT

BSM

TC

12

11

0U

F-1

6V

_T

AN

TB

SMT

R5

8

10

K-0

60

3SM

T

R5

8

10

K-0

60

3SM

T

R8

00

R-0

80

5SM

TR

80

0R

-08

05

SMT

R5

3

47

0R

-12

06

SMTR5

3

47

0R

-12

06

SMT

U1

5

PT

H1

20

60

W

U1

5

PT

H1

20

60

W

GN

D1

VIN

2

INHIBIT# 3

ADJUST 4

SE

NS

E5

VO

UT

6

GND 7TRACK8

MDWN9

MUP10

J7 HEA

DER

3x1

J7 HEA

DER

3x1

1V

1

AD

J2

1.2

V3

Q3

2N

22

22

/SO

T2

3Q

32

N2

22

2/S

OT

23

3

1

2

F5 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

F5 F12

28

CT

-ND

5A

Fas

t-B

lo S

MT

So

cke

ted

Fu

se

R6

4

0R

-06

03

SMT

R6

4

0R

-06

03

SMT

U1

1

PT

H0

30

10

W

U1

1

PT

H0

30

10

W

GN

D1

VIN

2

INHIBIT# 3

ADJUST 4

SE

NS

E5

VO

UT

6

GND 7TRACK8

MDWN9

MUP10

21

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 8. SERDES

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PET

n0

PET

p0

A_

HD

INP

0_

L5

0

A_

HD

INN

0_

L5

0

A_

HD

OU

TP

0_

L5

0

A_

HD

OU

TN

0_

L5

0

PER

p0

PER

n0

PET

p0

PET

n0

PC

IE_

3V

3

PC

IE_

CLK

NP

CIE

_C

LKP

x1

x1

PC

IE_

3V

3

PET

n0

PET

p0

PER

p0

PER

n0

A_

REF

CLK

N_

RA

_R

EFC

LKP

_R

A_

REF

CLK

N_

LA

_R

EFC

LKP

_L

A_

HD

OU

TP

0_

LA

_H

DO

UT

N0

_L

A_

HD

INP

0_

LA

_H

DIN

N0

_L

A_

HD

INP

0_

RA

_H

DIN

N0

_R

A_

HD

INP

1_

RA

_H

DIN

N1

_R

A_

HD

INP

2_

RA

_H

DIN

N2

_R

A_

HD

OU

TP

0_

RA

_H

DO

UT

N0

_R

A_

HD

OU

TP

1_

RA

_H

DO

UT

N1

_R

A_

HD

OU

TP

2_

RA

_H

DO

UT

N2

_R

A_

HD

OU

TP

1_

LA

_H

DO

UT

N1

_L

A_

HD

OU

TP

2_

LA

_H

DO

UT

N2

_L

A_

HD

INP

1_

LA

_H

DIN

N1

_L

A_

HD

INP

2_

LA

_H

DIN

N2

_L

IN_

SAT

A_

HO

ST+

IN_

SAT

A_

HO

ST-

IN_

SAT

A_

TG

T+

IN_

SAT

A_

TG

T-

QUAD_LOOP1_N

QUAD_LOOP1_P

QUAD_LOOP2_P

QUAD_LOOP2_N

A_

HD

INP

1_

L

A_

HD

INN

1_

L

A_

HD

INP

2_

L

A_

HD

INN

2_

L

A_

HD

OU

TP

1_

L

A_

HD

OU

TN

1_

L

A_

HD

OU

TP

2_

L

A_

HD

OU

TN

2_

L

RES

P_

L

RES

P_

R

RES

P_

L_N

RES

P_

R_

N

OU

T_

SAT

A_

TG

T+

50

OU

T_

SAT

A_

TG

T-

50

A_

HD

OU

TP

2_

R

A_

HD

OU

TN

2_

R

OU

T_

SAT

A_

HO

ST+

50

OU

T_

SAT

A_

HO

ST-

50

A_

HD

OU

TP

1_

R

A_

HD

OU

TN

1_

R

OU

T_

SAT

A_

HO

ST+

OU

T_

SAT

A_

HO

ST-

OU

T_

SAT

A_

TG

T+

50

OU

T_

SAT

A_

TG

T-

50

OU

T_

SAT

A_

HO

ST-

50

OU

T_

SAT

A_

HO

ST+

50

RES

P_

LR

ESP

_L_

NR

ESP

_R

RES

P_

R_

N

SFP

_R

DP

SFP

_R

DN

IN_

SAT

A_

TG

T+

50

IN_

SAT

A_

TG

T-

50

A_

HD

INP

2_

R

A_

HD

INN

2_

R

IN_

SAT

A_

HO

ST+

50

IN_

SAT

A_

HO

ST-

50

A_

HD

INP

1_

R

A_

HD

INN

1_

R

SFP

_R

DN

50

SFP

_R

DP

50

SFP

_T

DN

SFP

_T

DP

RX

REF

CLK

P_

L

RX

REF

CLK

P_

R

A_

HD

INN

0_

R

A_

HD

INP

0_

R

A_

HD

OU

TP

0_

R

A_

HD

OU

TN

0_

R

OU

T_

SAT

A_

TG

T-

OU

T_

SAT

A_

TG

T+

12

_0

V

3_

3V

3_

3V

PC

IE_

CLK

N[1

2]

PC

IE_

CLK

P[1

2]P

CIE

_P

ERST

N[2

]P

CIE

_W

AK

EN[2

]

PC

IE_

SMC

LK[2

]

A_

REF

CLK

N_

R[8

]A

_R

EFC

LKP

_R

[8]

A_

REF

CLK

N_

L[8

]A

_R

EFC

LKP

_L

[8]

PC

IE_

SMD

AT

[2]

SFP

_T

XFA

ULT

[2]

SFP

_T

XD

IS[2

]SF

P_

MO

DD

EF2

[2]

SFP

_M

OD

DEF

1[2

]SF

P_

MO

DD

EF0

[2]

SFP

_R

AT

ESEL

[2]

SFP

_LO

S[2

]

Tit

le

ve

Rt

cej

orP

ez i

S

te

eh

S:

e ta

Do

f

SC P

CI E

XP

RES

S C

ard

2.0

SER

DES

C

51

4

Tit

le

ve

Rt

cej

orP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

2.0

SER

DES

C

51

4

Tit

le

ve

Rt

cej

orP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

2.0

SER

DES

C

51

4

HD

INH

DO

UT

Pla

ce C

ap

aci

tors

a

nd

Re

sist

ors

as

Ph

ysic

ally

clo

se t

od

evi

ce p

in a

s p

oss

ible

3G

SM

As

X1

PC

Ie B

oa

rd F

ing

ers

B s

ide

= P

rim

ary

Co

mp

on

en

t S

ide

(TO

P)

A s

ide

= S

eco

nd

ary

Co

mp

on

en

t S

ide

(BO

TT

OM

)

200K

200K

AC

Co

up

led

re

ceiv

er

+ 2

00

K O

hm

to

GN

D

Hos

t

Targ

et

SGM

II

SFP

SATA

STU

FF O

PTIO

N A

:RE

PLA

CE C

157,

C15

8 W

ITH

0-O

HM

SH

UN

TS

STU

FF O

PTIO

N A

:LE

AVE

R10

6, R

107

== O

PEN

C1

46

10

NF-

04

02

SMT

C1

46

10

NF-

04

02

SMT

R9

6

15

0R

-06

03

SMT

R9

6

15

0R

-06

03

SMT

R9

3

4_

02

K-0

60

3SM

T

R9

3

4_

02

K-0

60

3SM

T

C1

59

10

0N

FX5

R-0

40

2SM

TC

15

91

00

NFX

5R

-04

02

SMT

C1

40

10

NF-

04

02

SMT

C1

40

10

NF-

04

02

SMT

R103

1K-0603SMT

R103

1K-0603SMT

C1

57

10

0N

FX5

R-0

40

2SM

TC

15

71

00

NFX

5R

-04

02

SMT

J17

SMA

_9

01

_1

44

_8

(NO

B)

J17

SMA

_9

01

_1

44

_8

(NO

B)

12 3 4 5

C1

58

10

0N

FX5

R-0

40

2SM

TC

15

81

00

NFX

5R

-04

02

SMT

C1

53

10

UF-

16

V_

TA

NT

BSM

TC

15

31

0U

F-1

6V

_T

AN

TB

SMT

J18

SMA

_9

01

_1

44

_8

(NO

B)

J18

SMA

_9

01

_1

44

_8

(NO

B)

12 3 4 5

C1

60

10

0N

FX5

R-0

40

2SM

TC

16

01

00

NFX

5R

-04

02

SMT

CG

1

SFP

_C

AG

E

CG

1

SFP

_C

AG

E

11

22

33

44

55

66

77

88

99

10

10

11

11

R101

10K-0603SMT

R101

10K-0603SMT

C1

55

10

0N

FX5

R-0

40

2SM

TC

15

51

00

NFX

5R

-04

02

SMT

R99

10K-0603SMT

R99

10K-0603SMT

R1

05

15

0R

-06

03

SMT

R1

05

15

0R

-06

03

SMT

L2

1U

H-1

20

6SM

T

L2

1U

H-1

20

6SM

TC

15

4

100NF-0603SMT

C1

54

100NF-0603SMT

C1

50

100NF-0603SMT

C1

50

100NF-0603SMT

C1

44

10

NF-

04

02

SMT

C1

44

10

NF-

04

02

SMT

C1

42

10

NF-

04

02

SMT

C1

42

10

NF-

04

02

SMT

C1

41

10

NF-

04

02

SMT

C1

41

10

NF-

04

02

SMT

CN

3 HO

ST_

SFP

CN

3 HO

ST_

SFP

Ve

eT

1

TxF

ault

2

TxD

isab

le3

Mo

d_

De

f_2

4

Mo

d_

De

f_1

5

Mo

d_

De

f_0

6

Rat

eS

el

7

LOS

8

Ve

eR

9

Ve

eR

10

Ve

eR

11

RD

-1

2R

D+

13

Ve

eR

14

Vcc

R1

5V

ccT

16

Ve

eT

17

TD

-1

9V

ee

T2

0

TD

+1

8

C1

48

10

0N

FX5

R-0

40

2SM

TC

14

81

00

NFX

5R

-04

02

SMT

J14

Ro

sen

be

rge

r 3

2K

15

3-4

00

E3J14

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

SERD

ESSC

-900

FPBG

AU

1A

SC2

5-9

00

fpB

GA

SERD

ESSC

-900

FPBG

AU

1A

SC2

5-9

00

fpB

GA

A_

HD

INN

0_

LB

4

A_

HD

INN

1_

LB

5

A_

HD

INN

2_

LB

8

A_

HD

INN

3_

LB

9

A_

HD

INP

0_

LB

3

A_

HD

INP

1_

LB

6

A_

HD

INP

2_

LB

7

A_

HD

INP

3_

LB

10

A_

HD

OU

TN

0_

LA

4

A_

HD

OU

TN

1_

LA

5

A_

HD

OU

TN

2_

LA

8

A_

HD

OU

TN

3_

LA

9

A_

HD

OU

TP

0_

LA

3

A_

HD

OU

TP

1_

LA

6

A_

HD

OU

TP

2_

LA

7

A_

RE

FCLK

N_

LC

1

A_

RE

FCLK

N_

RC

30

A_

RE

FCLK

P_

LB

1

A_

RE

FCLK

P_

RB

30

A_

RX

RE

FCLK

N_

LC

2

A_

RX

RE

FCLK

N_

RC

29

A_

RX

RE

FCLK

P_

LB

2

A_

RX

RE

FCLK

P_

RB

29

A_

HD

INP

0_

RB

28

A_

HD

INN

0_

RB

27

A_

HD

INP

1_

RB

25

A_

HD

INN

1_

RB

26

A_

HD

INP

2_

RB

24

A_

HD

INN

2_

RB

23

A_

HD

INP

3_

RB

21

A_

HD

INN

3_

RB

22

A_

HD

OU

TP

0_

RA

28

A_

HD

OU

TN

0_

RA

27

A_

HD

OU

TP

1_

RA

25

A_

HD

OU

TN

1_

RA

26

A_

HD

OU

TP

2_

RA

24

A_

HD

OU

TN

2_

RA

23

A_

HD

OU

TP

3_

RA

21

A_

HD

OU

TN

3_

RA

22

A_

HD

OU

TP

3_

LA

10

RE

SP

_U

LCA

2

RE

SP

_U

RC

A2

9

C1

52

100NF-0603SMT

C1

52

100NF-0603SMT

R9

5

15

0R

-06

03

SMT

R9

5

15

0R

-06

03

SMT

R9

0

OP

EN-0

60

3SM

T R9

0

OP

EN-0

60

3SM

T

R9

7

15

0R

-06

03

SMT

R9

7

15

0R

-06

03

SMT

J13

Ro

sen

be

rge

r 3

2K

15

3-4

00

E3J13

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

CN

4

PC

I Exp

ress

x1

Ed

ge

Fin

ge

r C

on

n.

CN

4

PC

I Exp

ress

x1

Ed

ge

Fin

ge

r C

on

n.

PR

SN

T1

#A

1

+1

2V

A2

+1

2V

A3

GN

DA

4

JTA

G2

A5

JTA

G3

A6

JTA

G4

A7

JTA

G5

A8

+3

.3V

A9

+3

.3V

A1

0

PE

RS

T#

A1

1

GN

DA

12

RE

FCLK

+A

13

RE

FCLK

-A

14

GN

DA

15

PE

Rp

0A

16

PE

Rn

0A

17

GN

DA

18

+1

2V

B1

+1

2V

B2

RS

VD

_B

3B

3

GN

DB

4

SM

CLK

B5

SM

DA

TB

6

GN

DB

7

+3

.3V

B8

JTA

G1

B9

3.3

Vau

xB

10

WA

KE

#B

11

RS

VD

_B

12

B1

2

GN

DB

13

PE

Tp

0B

14

PE

Tn

0B

15

GN

DB

16

PR

SN

T3

#B

17

GN

DB

18

C1

45

10

NF-

04

02

SMT

C1

45

10

NF-

04

02

SMT

J16

Ro

sen

be

rge

r 3

2K

15

3-4

00

E3J16

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

C1

51

10

UF-

16

V_

TA

NT

BSM

TC

15

11

0U

F-1

6V

_T

AN

TB

SMT

J10

Ro

sen

be

rge

r 3

2K

15

3-4

00

E3J10

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

J9R

ose

nb

erg

er

32

K1

53

-40

0E3J9

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

G A+ A- G B- B+ G

CN

1

SAT

A

G A+ A- G B- B+ G

CN

1

SAT

A

1 2 3 4 5 6 7

TP

13

TES

TP

OIN

TT

P1

3T

EST

PO

INT

1

C1

39

10

NF-

04

02

SMT

C1

39

10

NF-

04

02

SMT

J15

Ro

sen

be

rge

r 3

2K

15

3-4

00

E3J15

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

R1

07

20

0K

-04

02

SMT

R1

07

20

0K

-04

02

SMT

J12

Ro

sen

be

rge

r 3

2K

15

3-4

00

E3J12

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

J11

Ro

sen

be

rge

r 3

2K

15

3-4

00

E3J11

Ro

sen

be

rge

r 3

2K

15

3-4

00

E31

2

C1

49

100NF-0603SMT

C1

49

100NF-0603SMT

R1

06

20

0K

-04

02

SMT

R1

06

20

0K

-04

02

SMT

R98

10K-0603SMT

R98

10K-0603SMT

R100

10K-0603SMT

R100

10K-0603SMT

C1

56

10

0N

FX5

R-0

40

2SM

TC

15

61

00

NFX

5R

-04

02

SMT

R1

04

15

0R

-06

03

SMT

R1

04

15

0R

-06

03

SMT

L1 1U

H-1

20

6SM

TL1 1

UH

-12

06

SMT

C1

47

10

0N

FX5

R-0

40

2SM

TC

14

71

00

NFX

5R

-04

02

SMT

R102

10K-0603SMT

R102

10K-0603SMT

C1

43

10

NF-

04

02

SMT

C1

43

10

NF-

04

02

SMT

R9

2

OP

EN-0

60

3SM

T R9

2

OP

EN-0

60

3SM

T

R9

1

4_

02

K-0

60

3SM

T

R9

1

4_

02

K-0

60

3SM

T

R9

4

15

0R

-06

03

SMT

R9

4

15

0R

-06

03

SMT

G A+ A- G B- B+ G

CN

2

SAT

A

G A+ A- G B- B+ G

CN

2

SAT

A

1 2 3 4 5 6 7

22

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 9. SERDES Power Supplies5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

A_

VD

DIB

0_

L

VD

DO

B

VD

DIB

VD

DO

B

VD

DIB

VD

DO

B

VD

DIB

A_

VD

DIB

0_

R

2_

5V

1_

5V

1_

2V

DD

A

1_

2V

1_

2V

DD

A

1_

2V

1_

5V

1_

2V

DD

A

VD

DO

B

VD

DIB

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

X1

PC

I EX

PR

ESS

Car

d1

.0

SER

DES

Po

wer

Su

pp

lies

C

61

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

X1

PC

I EX

PR

ESS

Car

d1

.0

SER

DES

Po

wer

Su

pp

lies

C

61

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

X1

PC

I EX

PR

ESS

Car

d1

.0

SER

DES

Po

wer

Su

pp

lies

C

61

4

VDDAX25 PROBE POINT

VDD_SERDES PROBE POINT

C1

68

10

0N

F-0

60

3SM

T

C1

68

10

0N

F-0

60

3SM

T

PP

14

PP

14

1 2

R1

08

OP

EN-0

80

5SM

TR

10

8O

PEN

-08

05

SMT

C1

77

10

NF-

06

03

SMT

C1

77

10

NF-

06

03

SMT

C1

78

10

0N

F-0

60

3SM

T

C1

78

10

0N

F-0

60

3SM

T

SERDES

SUPPLIES

SC-900FPBGA

U1

B

SC2

5-9

00

fpB

GA

SERDES

SUPPLIES

SC-900FPBGA

U1

B

SC2

5-9

00

fpB

GA

A_

VD

DIB

0_

LC

3

A_

VD

DIB

1_

LC

6

A_

VD

DIB

2_

LC

7

A_

VD

DIB

3_

LC

10

A_

VD

DO

B0

_L

C4

A_

VD

DO

B1

_L

C5

A_

VD

DO

B2

_L

C8

A_

VD

DO

B3

_L

C9

A_

VD

DR

X0

_L

D6

A_

VD

DR

X1

_L

E7

A_

VD

DR

X2

_L

D8

A_

VD

DR

X3

_L

E9

A_

VD

DT

X0

_L

E6

A_

VD

DT

X1

_L

D7

A_

VD

DT

X2

_L

E8

A_

VD

DT

X3

_L

D9

A_

VD

DA

X2

5_

LF7

A_

VD

DA

X2

5_

RF2

4A

_V

DD

P_

LD

5

A_

VD

DP

_R

D2

6

A_

VD

DIB

0_

RC

28

A_

VD

DIB

1_

RC

25

A_

VD

DIB

2_

RC

24

A_

VD

DIB

3_

RC

21

A_

VD

DO

B0

_R

C2

7

A_

VD

DO

B1

_R

C2

6

A_

VD

DO

B2

_R

C2

3

A_

VD

DO

B3

_R

C2

2

A_

VD

DR

X0

_R

D2

5

A_

VD

DR

X1

_R

E2

4

A_

VD

DR

X2

_R

D2

3

A_

VD

DR

X3

_R

E2

2

A_

VD

DT

X0

_R

E2

5

A_

VD

DT

X1

_R

D2

4

A_

VD

DT

X2

_R

E2

3

A_

VD

DT

X3

_R

D2

2

R1

09

0R

-08

05

SMT

R1

09

0R

-08

05

SMT

+C

16

4

22UF-16V_TANTBSMT

+C

16

4

22UF-16V_TANTBSMT

C4

38

10

0N

F-0

60

3SM

T

C4

38

10

0N

F-0

60

3SM

T

C1

73

10

NF-

06

03

SMT

C1

73

10

NF-

06

03

SMT

C1

75

10

NF-

06

03

SMT

C1

75

10

NF-

06

03

SMT

C1

65

1UF-16V-0805SMTC

16

51UF-16V-0805SMT

R1

11

0R

-08

05

SMT

R1

11

0R

-08

05

SMT

C1

71

10

NF-

06

03

SMT

C1

71

10

NF-

06

03

SMT

C1

76

10

0N

F-0

60

3SM

T

C1

76

10

0N

F-0

60

3SM

T

+C

16

2

22UF-16V_TANTBSMT

+C

16

2

22UF-16V_TANTBSMT

R1

10

OP

EN-0

80

5SM

TR

11

0O

PEN

-08

05

SMT

C1

74

10

0N

F-0

60

3SM

T

C1

74

10

0N

F-0

60

3SM

T

C1

67

1UF-16V-0805SMT

C1

67

1UF-16V-0805SMTC

17

2

10

0N

F-0

60

3SM

T

C1

72

10

0N

F-0

60

3SM

T

C1

63

1UF-16V-0805SMT

C1

63

1UF-16V-0805SMT+

C1

66

22UF-16V_TANTBSMT

+C

16

6

22UF-16V_TANTBSMT

C1

61

10

0N

F-0

60

3SM

T

C1

61

10

0N

F-0

60

3SM

T

C1

69

10

NF-

06

03

SMT

C1

69

10

NF-

06

03

SMT

C1

70

10

0N

F-0

60

3SM

T

C1

70

10

0N

F-0

60

3SM

T

C1

79

10

NF-

06

03

SMT

C1

79

10

NF-

06

03

SMT

PP

15

PP

15

1 2

23

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 10. Clocks5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

OSC

_IN

_1

OSC

_IN

_3

OSC

_IN

_4

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

1_

8V

3_

3V

3_

3V

REF

CLK

P_

L[8

]

REF

CLK

N_

L[8

]

OSC

_IN

_1

[2]

REF

CLK

P_

R[8

]

REF

CLK

N_

R[8

]

CLO

CK

_C

TR

L_R

[2]

CLO

CK

_C

TR

L_L

[2]

OSC

_IN

_3

[12

]O

SC_

IN_

4[1

2]

Tit

le

ve

Rt

ce j

orP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Clo

cks

C

71

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Clo

cks

C

71

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Clo

cks

C

71

4

NOTE: PLACE

TERMINATIONS

CLOSE TO

DEVICE.

NOTE: PLACE

TERMINATIONS

CLOSE TO

DEVICE.

Oscillator

Control

Oscillator

Socket

SMT Oscillator

Oscillator

Control

Oscillator

Socket

SMT Oscillator

EXTERNAL CLKINPUT

EXTERNAL CLKINPUT

NOTE: PLACE

TERMINATIONS

CLOSE TO

DEVICE.

NOTE: PLACE

TERMINATIONS

CLOSE TO

DEVICE.SEL0 SEL1 Q0/Q0# Q1/Q1#

L L B B

L H B A

H H A A

H L A B

*** Pin is Low when open/float

SEL0

SEL1

Q7

2N

22

22

/SO

T2

3

Q7

2N

22

22

/SO

T2

33

1

2

R1

43

82

R-0

60

3SM

TR

14

38

2R

-06

03

SMT

R1

15

13

0R

-06

03

SMT

R1

15

13

0R

-06

03

SMT

R1

34

82

R-0

60

3SM

TR

13

48

2R

-06

03

SMT

J21

HEA

DER

2X

1

J21

HEA

DER

2X

1

1 1

2 2

+C

19

4

10

0N

F-0

60

3SM

T

+C

19

4

10

0N

F-0

60

3SM

TU

29

PC

A9

30

6

U2

9

PC

A9

30

6

GND 1

VR

EF_

LV2

SIG

A_

LV3

SIG

B_

LV4

SIG

B_

HV

5S

IGA

_H

V6

VR

EF_

HV

7

EN8

R1

18

82

R-0

60

3SM

TR

11

88

2R

-06

03

SMT

R2

83

OP

EN-0

60

3SM

TR

28

3O

PEN

-06

03

SMT

R1

28

1_

6R

-06

03

SMT

R1

28

1_

6R

-06

03

SMT

C196

10NF-0603SMT

C196

10NF-0603SMT

R1

38

13

0R

-06

03

SMT

R1

38

13

0R

-06

03

SMT

J23

J23

12 3 4 5

R1

39

10

7R

-06

03

SMT

R1

39

10

7R

-06

03

SMT

R1

21

13

0R

-06

03

SMT

R1

21

13

0R

-06

03

SMT

C1

88

10

0N

F-0

60

3SM

T

C1

88

10

0N

F-0

60

3SM

T

C181

100NF-0603SMT

C181

100NF-0603SMT

R1

20

82

R-0

60

3SM

TR

12

08

2R

-06

03

SMT

R2

81

OP

EN-0

60

3SM

TR2

81

OP

EN-0

60

3SM

T

Y1

11

0-9

3-3

14

-41

-00

1Y

11

10

-93

-31

4-4

1-0

01

Q_

N1

Q8

VDD14 GND 7

R1

24

27

0R

-06

03

SMT

R1

24

27

0R

-06

03

SMT

R2

80

20

0K

-06

03

SMT

R2

80

20

0K

-06

03

SMT

R1

27

82

R-0

60

3SM

TR

12

78

2R

-06

03

SMT

Y5

CW

-P4

23

F-3

12

.5M

HZ

Y5

CW

-P4

23

F-3

12

.5M

HZ

Q_

N5

Q4

VCC6 GND 3

DIS

#1

NC

2

R1

14

13

0R

-06

03

SMT

R1

14

13

0R

-06

03

SMT

R2

82

OP

EN-0

60

3SM

TR

28

2O

PEN

-06

03

SMT

C1

89

10

NF-

06

03

SMT

C1

89

10

NF-

06

03

SMT

MUX

U1

7B

MC

10

0LV

EL5

6MUX

U1

7B

MC

10

0LV

EL5

6

D1

A6

D1

A_

N7

VB

B1

8

D1

B9

D1

B_

N1

0

VEE 11Q1

_N

12

Q1

13

VCC14

SE

L11

5

J24

J24

12 3 4 5

R1

23

10

7R

-06

03

SMT

R1

23

10

7R

-06

03

SMT

R1

22

13

0R

-06

03

SMT

R1

22

13

0R

-06

03

SMT

R1

31

13

0R

-06

03

SMT

R1

31

13

0R

-06

03

SMT

R1

16

13

0R

-06

03

SMT

R1

16

13

0R

-06

03

SMT

R2

78

OP

EN-0

60

3SM

TR2

78

OP

EN-0

60

3SM

T

J19

HEA

DER

3x1

J19

HEA

DER

3x1

1

32

R1

25

82

R-0

60

3SM

TR

12

58

2R

-06

03

SMT

+C

18

2

10UF-16V_TANTBSMT

+C

18

2

10UF-16V_TANTBSMT

J28

JUM

PER

1

J28

JUM

PER

1

12

R1

35

82

R-0

60

3SM

TR

13

58

2R

-06

03

SMT

U1

8

CY

23

04

-1

U1

8

CY

23

04

-1

RE

F1

CLK

A1

2

CLK

A2

3

GN

D4

CLK

B1

5C

LKB

26

VD

D7

FBK

8

R2

84

OP

EN-0

60

3SM

TR

28

4O

PEN

-06

03

SMT

R1

12

1_

6R

-06

03

SMT

R1

12

1_

6R

-06

03

SMT

R2

79

OP

EN-0

60

3SM

TR

27

9O

PEN

-06

03

SMT

R1

32

13

0R

-06

03

SMT

R1

32

13

0R

-06

03

SMT

J25

JUM

PER

1

J25

JUM

PER

1

12

Y4

11

0-9

3-3

14

-41

-00

1

Y4

11

0-9

3-3

14

-41

-00

1

Q_

N1

Q8

VDD14 GND 7

Q6

2N

22

22

/SO

T2

3

Q6

2N

22

22

/SO

T2

33

1

2

C185

100NF-0603SMT

C185

100NF-0603SMT

R1

41

10

K-0

60

3SM

T

R1

41

10

K-0

60

3SM

T

C195

100NF-0603SMT

C195

100NF-0603SMT

R1

36

82

R-0

60

3SM

TR

13

68

2R

-06

03

SMT

R1

30

13

0R

-06

03

SMT

R1

30

13

0R

-06

03

SMT

J27

HEA

DER

2X

1

J27

HEA

DER

2X

1

1 1

2 2

C183

100NF-0603SMT

C183

100NF-0603SMT

MUX

U1

7A

MC

10

0LV

EL5

6

MUX

U1

7A

MC

10

0LV

EL5

6

D0

A1

D0

A_

N2

VB

B0

3

D0

B4

D0

B_

N5

CO

M_

SE

L1

6

SE

L01

7

Q0

_N

18

Q0

19

VCC20

R1

29

13

0R

-06

03

SMT

R1

29

13

0R

-06

03

SMT

C190

100NF-0603SMT

C190

100NF-0603SMT

Y2

CW

-P4

23

F-3

12

.5M

HZ

Y2

CW

-P4

23

F-3

12

.5M

HZ

Q_

N5

Q4

VCC6 GND 3D

IS#

1

NC

2

+C

18

41

00

NF-

06

03

SMT

+C

18

41

00

NF-

06

03

SMT

J26

HEA

DER

3x1

J26

HEA

DER

3x1

1

32

Y3

CT

S-C

B3

LV-3

C-1

00

.00

MH

Z

Y3

CT

S-C

B3

LV-3

C-1

00

.00

MH

Z

N/C

1

GN

D2

OU

T3

Vcc

4

R1

33

82

R-0

60

3SM

TR

13

38

2R

-06

03

SMT

J20

JUM

PER

1

J20

JUM

PER

1

12

R1

40

27

0R

-06

03

SMT

R1

40

27

0R

-06

03

SMT

R1

37

13

0R

-06

03

SMT

R1

37

13

0R

-06

03

SMT

R1

17

82

R-0

60

3SM

T

R1

17

82

R-0

60

3SM

T

+C

18

01

00

NF-

06

03

SMT

+C

18

01

00

NF-

06

03

SMT

C186

10NF-0603SMT

C186

10NF-0603SMT

C192

100NF-0603SMT

C192

100NF-0603SMT

J29

J29

12 3 4 5

C1

87

10

0N

F-0

60

3SM

T

C1

87

10

0N

F-0

60

3SM

T

R1

19

82

R-0

60

3SM

T

R1

19

82

R-0

60

3SM

T

R1

42

82

R-0

60

3SM

TR

14

28

2R

-06

03

SMT

C5

00

10

0N

F-0

60

3SM

T

C5

00

10

0N

F-0

60

3SM

T+

C1

91

10

0N

F-0

60

3SM

T

+C

19

1

10

0N

F-0

60

3SM

T

J30

J30

12 3 4 5

R1

13

13

0R

-06

03

SMT

R1

13

13

0R

-06

03

SMT

+C

19

3

10UF-16V_TANTBSMT

+C

19

3

10UF-16V_TANTBSMT

R1

26

10

K-0

60

3SM

T

R1

26

10

K-0

60

3SM

T

J22

JUM

PER

1

J22

JUM

PER

1

12

24

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 11. Clocks (Cont.)

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

L_EX

T_

OU

T_

N

L_EX

T_

OU

T_

P

R_

EXT

_O

UT

_N

R_

EXT

_O

UT

_P

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

3_

3V

A_

REF

CLK

N_

L[5

]

A_

REF

CLK

P_

L[5

]

REF

CLK

P_

L[7

]

REF

CLK

N_

L[7

]

A_

REF

CLK

N_

R[5

]

A_

REF

CLK

P_

R[5

]

REF

CLK

P_

R[7

]

REF

CLK

N_

R[7

]

FPG

A_

REF

CLK

P_

L[1

2]

FPG

A_

REF

CLK

N_

L[1

2]

FPG

A_

REF

CLK

P_

R[1

2]

FPG

A_

REF

CLK

N_

R[1

2]

Tit

le

ve

Rt

ce j

orP

ez i

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Clo

cks(

Co

nti

nu

ed)

C

81

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Clo

cks(

Co

nti

nu

ed)

C

81

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

Clo

cks(

Co

nti

nu

ed)

C

81

4

NOTE: PLACE

TERMINATIONS

CLOSE TO U1

DEVICE.

NOTE: PLACE

TERMINATIONS

CLOSE TO U1

DEVICE.

NOTE: PLACE

TERMINATIONS

CLOSE TO U1

DEVICE.

NOTE: PLACE

TERMINATIONS

CLOSE TO U1

DEVICE.

R1

54

82

R-0

60

3SM

TR

15

48

2R

-06

03

SMT

R1

45

OP

EN-0

60

3SM

TR

14

5O

PEN

-06

03

SMT

R1

67

82

R-0

60

3SM

TR

16

78

2R

-06

03

SMT

J33

J331

2 3 4 5

R1

53

82

R-0

60

3SM

TR

15

38

2R

-06

03

SMT

R1

65

62

R-0

60

3SM

TR

16

56

2R

-06

03

SMT

R1

68

82

R-0

60

3SM

TR

16

88

2R

-06

03

SMT

R1

48

13

0R

-06

03

SMT

R1

48

13

0R

-06

03

SMT

U1

9B

MC

10

0LV

EL1

3D

U1

9B

MC

10

0LV

EL1

3D

CLK

B6

CLK

B_

N7

VCC8

Q0

B_

N9

Q0

B1

0

VEE 11

Q1

B_

N1

2

Q1

B1

3

Q2

B_

N1

4

Q2

B1

5

R1

61

82

R-0

60

3SM

TR

16

18

2R

-06

03

SMT

U1

9A

MC

10

0LV

EL1

3D

U1

9A

MC

10

0LV

EL1

3D

Q0

A_

N1

Q0

A2

VCC3

CLK

A4

CLK

A_

N5

VCC16

Q2

A_

N1

7

Q2

A1

8

Q1

A_

N1

9

Q1

A2

0

R1

50

13

0R

-06

03

SMT

R1

50

13

0R

-06

03

SMT

R1

63

13

0R

-06

03

SMT

R1

63

13

0R

-06

03

SMT

R1

60

82

R-0

60

3SM

TR

16

08

2R

-06

03

SMT

R1

70

13

0R

-06

03

SMT

R1

70

13

0R

-06

03

SMT

J34

J341

2 3 4 5

R1

62

13

0R

-06

03

SMT

R1

62

13

0R

-06

03

SMT

+C

19

91

00

NF-

06

03

SMT

+C

19

91

00

NF-

06

03

SMT

R1

46

62

R-0

60

3SM

TR

14

66

2R

-06

03

SMT

R1

58

OP

EN-0

60

3SM

TR

15

8O

PEN

-06

03

SMT

+C

19

71

00

NF-

06

03

SMT

+C

19

71

00

NF-

06

03

SMT

R1

56

13

0R

-06

03

SMT

R1

56

13

0R

-06

03

SMT

R1

66

13

0R

-06

03

SMT

R1

66

13

0R

-06

03

SMT

R1

57

OP

EN-0

60

3SM

TR

15

7O

PEN

-06

03

SMT

R1

69

82

R-0

60

3SM

TR

16

98

2R

-06

03

SMT

R1

52

13

0R

-06

03

SMT

R1

52

13

0R

-06

03

SMT

R1

47

62

R-0

60

3SM

TR

14

76

2R

-06

03

SMT

+C

19

81

00

NF-

06

03

SMT

+C

19

81

00

NF-

06

03

SMT

R1

55

82

R-0

60

3SM

TR

15

58

2R

-06

03

SMT

R1

71

82

R-0

60

3SM

TR

17

18

2R

-06

03

SMT

J31

J311

2 3 4 5

R1

59

82

R-0

60

3SM

TR

15

98

2R

-06

03

SMT

R1

51

51

R-0

60

3SM

TR

15

15

1R

-06

03

SMT

R1

49

51

R-0

60

3SM

TR

14

95

1R

-06

03

SMT

R1

64

62

R-0

60

3SM

TR

16

46

2R

-06

03

SMT

J32

J321

2 3 4 5

R1

44

OP

EN-0

60

3SM

TR

14

4O

PEN

-06

03

SMT

25

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 12. QDR2 SRAM5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QD

R_

D1

0

QD

R_

A4

QD

R_

A5

QD

R_

D1

1

QD

R_

A6

QD

R_

A7

QD

R_

A8

QD

R_

REA

D_

N

QD

R_

A9

QD

R_

D1

3

QD

R_

A1

0Q

DR

_A

11

QD

R_

D1

4

QD

R_

A1

2Q

DR

_A

13

QD

R_

D1

5

QD

R_

A1

4

QD

R_

D1

6

VSENSE_QDR_VTT

QD

R_

K#

QD

R_

D1

QD

R_

D0

QD

R_

D2

QD

R_

D3

QD

R_

D5

QD

R_

D4

QD

R_

D6

QD

R_

D7

QD

R_

D8

QDR_D[0..17]

QD

R_

Q0

QD

R_

A1

5

QD

R_

Q1

QD

R_

Q2

QD

R_

Q3

QD

R_

Q4

QD

R_

Q5

QD

R_

Q7

QD

R_

Q8

QD

R_

Q6

QD

R_

Q9

QD

R_

Q1

0

QD

R_

Q1

2

QD

R_

Q1

4Q

DR

_Q

13

QD

R_

Q1

1

QD

R_

Q1

5QD

R_

K

QD

R_

Q1

6Q

DR

_Q

17

QD

R_

A1

7Q

DR

_A

16

QDR_A[0..17]

QD

R_

A0

QD

R_

A1

QD

R_

D9

QD

R_

A2

QD

R_

A3

QD

R_

D1

7

QD

R_

WR

ITE_

N

QD

R_

VR

EF

QD

R_

CQ

QDR_Q[0..17]

QD

R_

VR

EF

QD

R_

D1

2

QD

R_

VR

EF

VD

DQ

QD

R_

VT

T

QD

R_

VT

T

QD

R_

VT

T

VD

DQ

QD

R_

VT

T

QD

R_

VT

T

VD

DQ

2_

5V

1_

8V

VD

DQ

QD

R_

VD

D

1_

8V

VD

DQ

QD

R_

VD

D

2_

5V

VD

DQ

QD

R_

REA

D_

N[1

2]

QD

R_

WR

ITE_

N[1

2]

QD

R_

K[1

2]

QD

R_

K_

#[1

2]

QD

R_

Q[0

..17

][1

2]

QD

R_

CQ

[12

]

QD

R_

A[0

..17

][1

2]

QD

R_

D[0

..17

][1

2]

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

QD

R2

SR

AM

C

91

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

QD

R2

SR

AM

C

91

4

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

QD

R2

SR

AM

C

91

4

Value should be 5 times

the desired output

Impedance

i.e. 50 ohms = 250 ohms

impedance

0 ohms = min. impedance

When Low

PLL bypassed

Place resistors

as close to

SRAM device

as possible

ALL Memory controller

buses, clocks, and control

traces must be 50 Ohm

Transmission lines

Place resistor pack as close to SRAM

device as possible

All Q lines should be

equal lengths and

leng

th m

atch

ed w

ith

CQ

Place resistors

as close to

SRAM device

as possible

All ADDRESS & DATA

lines should be

equal lengths and

length matched with

the K & K# and

WRITE# and READ#

Place resistor pack as close to

SRAM device as possible

C220

100NF-0603SMT

C220

100NF-0603SMT

C241

100NF-0603SMT

C241

100NF-0603SMT

R1

R1

R1=50 Ohm

RP

1

CT

S-R

T1

40

2B

7

R1

R1

R1=50 Ohm

RP

1

CT

S-R

T1

40

2B

7

A2A2

B2B2

C2C2

D2D2

E2E2

F2F2

G2G2

H2H2

J2J2

A3

A3

B3

B3

C3

C3

D3

D3

E3

E3

F3F3

G3

G3

H3

H3

J3J3

A1

A1

B1

B1

C1

C1

D1

D1

E1

E1

F1F1

G1

G1

H1

H1

J1J1

C216

10NF-0603SMT

C216

10NF-0603SMT

C233

100NF-0603SMT

C233

100NF-0603SMT

R1

81

1K

-06

03

SMT

R1

81

1K

-06

03

SMT

C2

02

10

NF-

06

03

SMT

C2

02

10

NF-

06

03

SMT

C244

10NF-0603SMT

C244

10NF-0603SMT

R1

83

0R

-06

03

SMT

R1

83

0R

-06

03

SMT

C204

10NF-0603SMT

C204

10NF-0603SMT

C217

100NF-0603SMT

C217

100NF-0603SMT

+

C223

47UF-16V_TANTBSMT

+

C223

47UF-16V_TANTBSMT

C245

100NF-0603SMT

C245

100NF-0603SMT

C2

35

1UF-16V-0805SMT

C2

35

1UF-16V-0805SMT

C205

100NF-0603SMT

C205

100NF-0603SMT

C218

10NF-0603SMT

C218

10NF-0603SMT

R182

4_7K-0603SMT

R182

4_7K-0603SMT

C2

03

10

0N

F-0

60

3SM

TC

20

31

00

NF-

06

03

SMT

C246

10NF-0603SMT

C246

10NF-0603SMT

+C

23

4

22UF-16V_TANTBSMT

+C

23

4

22UF-16V_TANTBSMT

C206

10NF-0603SMT

C206

10NF-0603SMT

C219

100NF-0603SMT

C219

100NF-0603SMT

C2

24

1UF-16V-0805SMT

C2

24

1UF-16V-0805SMT

C247

100NF-0603SMT

C247

100NF-0603SMT

R177

51R-0603SMT

R177

51R-0603SMT

C207

100NF-0603SMT

C207

100NF-0603SMT

C221

1UF-16V-0805SMT

C221

1UF-16V-0805SMT

C2

00

10

NF-

06

03

SMT

C2

00

10

NF-

06

03

SMT

C2

27

1UF-16V-0805SMT

C2

27

1UF-16V-0805SMT

R176

51R-0603SMT

R176

51R-0603SMT

C208

10NF-0603SMT

C208

10NF-0603SMT

R17251R-0603SMT

R17251R-0603SMT

+

C226

47UF-16V_TANTBSMT

+

C226

47UF-16V_TANTBSMT

C2

28

10NF-0603SMT

C2

28

10NF-0603SMT

C209

100NF-0603SMT

C209

100NF-0603SMT

R1741K-0603SMT

R1741K-0603SMT

C2

29

100NF-0603SMT

C2

29

100NF-0603SMT

C210

10NF-0603SMT

C210

10NF-0603SMT

R17351R-0603SMT

R17351R-0603SMT

U2

1

LP2

99

6-S

O8

U2

1

LP2

99

6-S

O8

GND 1

SD

2

VS

EN

SE

3V

RE

F4

VD

DQ

5

AVIN6

PVIN7

VT

T8

C236

10NF-0603SMT

C236

10NF-0603SMT

C211

100NF-0603SMT

C211

100NF-0603SMT

C2

30

10NF-0603SMT C2

30

10NF-0603SMT

FB2

BLM

41

PG

47

1SN

1L

FB2

BLM

41

PG

47

1SN

1L

C237

100NF-0603SMT

C237

100NF-0603SMT

C212

10NF-0603SMT

C212

10NF-0603SMT

R178

OPEN-0603SMT

R178

OPEN-0603SMT

C2

31

100NF-0603SMT

C2

31

100NF-0603SMT

C2

01

10

0N

F-0

60

3SM

TC

20

11

00

NF-

06

03

SMT

R1

79 1K-0603SMT

R1

79 1K-0603SMT

C238

10NF-0603SMT

C238

10NF-0603SMT

+

C225

47UF-16V_TANTBSMT

+

C225

47UF-16V_TANTBSMT

QD

RII-

SRA

M

U2

0A

CY

7C

14

13

AV

18

-2M

x18

QD

RII-

SRA

M

U2

0A

CY

7C

14

13

AV

18

-2M

x18

D0

P1

0

D1

N1

1

D2

M1

1

D3

K1

0

D4

J11

D5

G1

1

D6

E1

0

D7

D1

1

D8

C1

1

D9

B3

D1

0C

3

D1

1D

2

D1

2F3

D1

3G

2

D1

4J3

D1

5L3

D1

6M

3

D1

7N

2

NC

B9

NC

C9

NC

D9

NC

E9

NC

F9

NC

G9

NC

J9

NC

K9

NC

L9

NC

M9

NC

N9

NC

P9

NC

B1

0

NC

D1

0

NC

F10

NC

G1

0

NC

L10

NC

N1

0

DLL#H1

NC/SA21A3

SA18 A9BW0B7

BW1A5

NCB5

Q0

P1

1

Q1

M1

0

Q2

L11

Q3

K1

1

Q4

J10

Q5

F11

Q6

E1

1

Q7

C1

0

Q8

B1

1

Q9

B2

Q1

0D

3

Q1

1E

3

Q1

2F2

Q1

3G

3

Q1

4K

3

Q1

5L2

Q1

6N

3

Q1

7P

3

NC

B1

NC

C1

NC

D1

NC

E1

NC

F1

NC

G1

NC

J1

NC

K1

NC

L1

NC

M1

NC

N1

NC

P1

NC

C2

NC

E2

NC

J2

NC

K2

NC

M2

NC

P2

R#A8

W#A4

ZQH11

CQ

A1

1

CQ

#A

1

CP6

C#R6

KB6K#A6

SA0 R3

SA1 R4

SA2 P4

SA3 R5

SA4 P5

SA5 N5

SA6 N6

SA7 N7

SA8 P7

SA9 R7

SA10 P8

SA11 R8

SA12 R9

SA13 B4

SA14 C5

SA15 C7

SA16 B8

SA17 C6

VSS/SA19 A2

VSS/SA20 A10

NC/SA22A7

C213

100NF-0603SMT

C213

100NF-0603SMT

R1

R1

R1=50 Ohm

RP

2 CT

S-R

T1

40

2B

7

R1

R1

R1=50 Ohm

RP

2 CT

S-R

T1

40

2B

7

A2A2

B2B2

C2C2

D2D2

E2E2

F2F2

G2G2

H2H2

J2J2

A3

A3

B3

B3

C3

C3

D3

D3

E3

E3

F3F3

G3

G3

H3

H3

J3J3

A1

A1

B1

B1

C1

C1

D1

D1

E1

E1

F1F1

G1

G1

H1

H1

J1J1

C239

100NF-0603SMT

C239

100NF-0603SMT

FB3

BLM

41

PG

47

1SN

1L

FB3

BLM

41

PG

47

1SN

1L

C214

10NF-0603SMT

C214

10NF-0603SMT

R175 249R-0603SMTR175 249R-0603SMT

C242

10NF-0603SMT

C242

10NF-0603SMT

C222

100NF-0603SMT

C222

100NF-0603SMT

C240

10NF-0603SMT

C240

10NF-0603SMT

R1

80

1K-0603SMTR1

80

1K-0603SMT

C215

100NF-0603SMT

C215

100NF-0603SMT

C232

10NF-0603SMT

C232

10NF-0603SMT

C243

100NF-0603SMT

C243

100NF-0603SMT

QD

R-I

I SR

AM

Po

wer

/Gn

d

U2

0B

CY

7C

14

13

AV

18

-2M

x18

QD

R-I

I SR

AM

Po

wer

/Gn

d

U2

0B

CY

7C

14

13

AV

18

-2M

x18

VD

DQ

G8

VD

DQ

H9

VD

DQ

G4

VD

DQ

H4

VD

DQ

H3

VD

DQ

K4

VD

DQ

H8

VD

DQ

F4

VD

DQ

K8

VD

DQ

L8

VD

DQ

J8

VD

DQ

E4

VD

DQ

F8

VD

DQ

E8

VD

DQ

J4

VD

DQ

L4

VD

DG

5

VD

DH

7

VD

DK

7

VD

DF5

VD

DF7

VD

DK

5

VD

DJ5

VD

DJ7

VD

DG

7

VD

DH

5

VR

EF

H2

VR

EF

H1

0

VSS M4

VSS M5

VSS M6

VSS C8

VSS L5

VSS E7

VSS E5

VSS C4

VSS F6

VSS K6

VSS L6

VSS M7

VSS L7

VSS N8

VSS M8

VSS E6

VSS D7

VSS G6

VSS H6

VSS N4

VSS D6

VSS J6

VSS D8

VSS D4

VSS D5

TCKR2

TDIR11

TDOR1

TMSR10

26

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 13. 10/100/1000 PHY5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

4S

UB

_A I

DM

3P

_ID

M

PULL_DN

2S

UB

_AI

DM

2P

_ ID

M

0S

UB

_AI

DM

1P

_ID

M

PH

Y_

TX

_EN

PH

Y_

TX

_D

3

MD

IA_

BU

S0

ETH

_EG

P5

ETH

_M

AC

_C

LK_

EN

ETH

_C

OL

ETH_EGP5

ETH

_EG

P6

ETH

_EG

P7

ETH

_EG

P4

ETH

_M

DIO

PH

Y_

TX

_D

4

3S

UB

_AI

DM

2N

_ID

M

5S

UB

_AI

DM

3N

_ID

M

7S

UB

_AI

DM

4N

_ID

M6

SU

B_

A ID

M4

P_ I

DM

ETH

_EG

P2

X0

PU

LL_

UP

X1

ETH

_EG

P0

PH

Y_

RX

_D

0P

HY

_R

X_

D1

ETH

_C

RS

PH

Y_

RX

_D

2P

HY

_R

X_

D3

ETH

_R

ESET

_N

PH

Y_

RX

_ER

1S

UB

_A I

DM

1N

_ID

M

PH

Y_

TX

_D

5

MD

IA_

BU

S3

ETH

_M

DC

MD

IA_

BU

S4

MD

IA_

BU

S2

MD

IA_

BU

S7

MD

IA_

BU

S6

MD

IA_

BU

S1

ETH

_R

X_

D2

ETH

_R

X_

D0

ETH

_R

X_

D3

ETH

_R

X_

D1

ETH

_R

X_

ERET

H_

RX

_D

VET

H_

RX

_C

LK

ETH

_T

X_

CLK

PH

Y_

TX

_ER

PH

Y_

TX

_D

6

ETH_CLK_TO_MAC

ETH_EGP6

PH

Y_

TX

_D

7

PH

Y_

RX

_C

LK

ETH

_M

AC

_C

LK_

EN

ETH

_EG

P7

ETH

_R

X_

D[0

..7]

MD

IA_

BU

S5

ETH

_EG

P0

PH

Y_

TX

_D

[0..7

]

PH

Y_

TX

_D

0

PH

Y_

TX

_EN

ETH

_T

X_

ENET

H_

TX

_ER

ETH

_T

X_

D4

ETH

_T

X_

D6

ETH

_T

X_

D5

ETH

_T

X_

D7

ETH

_T

X_

D0

ETH

_T

X_

D1

ETH

_T

X_

D2

ETH

_T

X_

D3

ETH

_G

TX

_C

LKP

HY

_G

TX

_C

LK

PH

Y_

TX

_D

3

PH

Y_

TX

_D

4P

HY

_T

X_

D5

PH

Y_

TX

_D

6P

HY

_T

X_

D7

PH

Y_

TX

_D

0P

HY

_T

X_

D1

PH

Y_

TX

_D

2

PH

Y_

TX

_C

LK

MD

IA_

BU

S[0

..7]

ETH

_EG

P[0

..7]

PH

Y_

TX

_ER

PH

Y_

TX

_D

1P

HY

_T

X_

D2

ETH

_EG

P4

PH

Y_

RX

_D

4P

HY

_R

X_

D5

ETH

_R

X_

D4

PH

Y_

RX

_D

7P

HY

_R

X_

D6

ETH

_R

X_

D7

ETH

_R

X_

D5

ETH

_R

X_

D6

ETH

_EG

P7

PH

Y_

CR

SP

HY

_C

OL

ETH

_R

ESET

_N

ETH

_EG

P[0

..7]

PH

Y_

RX

_D

V

ETH

_EG

P1

ETH

_EG

P3

1_

8V

2_

5V

2_

5V

2_

5V

2_

5V

2_

5V

2_

5V

2_

5V

1_

8V

2_

5V

2_

5V

2_

5V

ETH

_R

X_

D[0

..7]

[12

]

ETH

_EG

P[0

..7]

[2]

ETH

_T

X_

D[0

..7]

[12

]ET

H_

RX

_ER

[2]

ETH

_T

X_

CLK

[12

]

ETH

_G

TX

_C

LK[1

2]

ETH

_R

X_

DV

[12

]

ETH

_M

DIO

[2]

ETH

_C

RS

[12

]

ETH

_M

DC

[2]

ETH

_C

OL

[12

]

ETH

_T

X_

ER[2

]

ETH

_R

X_

CLK

[12

]

ETH

_T

X_

EN[1

2]

ETH

_R

ESET

_N

[2]

ETH

_C

LK_

TO

_M

AC

[12

]

ETH

_M

AC

_C

LK_

EN[2

]

Tit

le

ve

Rt

cej

orP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

10

/10

0/1

00

0 P

HY

C

10

14

Tit

le

ve

Rt

cej

orP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

10

/10

0/1

00

0 P

HY

C

10

14

Tit

le

ve

Rt

cej

orP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

10

/10

0/1

00

0 P

HY

C

10

14

Bypass for VDD_CORE and VDD pins. Bypass every

other VDD pair, alternating 0.1 and 0.01uF caps.

Place termination

resistors TX_D0-7,

TX_ER, TX_EN,

GTX_CLK as close to

FPGA as possible

using 50 ohm

impedence traces.

MDI IO traces must be 50 ohm impedence.

10/100/1000

Giga Phyter V

Place termination

resistors RX_D0-7,

RX_ER, RX_DV, RX_CLK,

TX_CLK, CRS, COL

as close to the

G-PHY as possible

using 50 ohm impedence

traces.

Giga Phyter

Decoupling Caps

Place 49 ohm termination resistors as

close as possible to G-PHY.

The associated 0.01uF capacitor should

be placed close to the 49 ohm resistors.

Place caps close to GPHY

Place these close to G-PHY

Giga Phyter address = 01h

(Hard Reset)

Place xtal

close to

G-PHY

Place R close to CLOCK_IN

Bypass for BG_VDD

MH

1 a

nd

MH

2ar

e 0

.10

0"

dia

me

ter

pla

ted

thro

ug

h h

ole

s

(Do not

populate)

Ethernet RJ45 Connector

Place caps close to RJ45 jack TX1

Place 9.76K resistor as close

to G-PHY as possible

Bypass for IO_VDD pins. Bypass every other

IO_VDD pair, alternating 0.1 and 0.01uF caps.

(Do not

populate)

R2

37

32

4R

-04

02

SMT

04

02

R2

37

32

4R

-04

02

SMT

04

02

12

R2

21

2K

-04

02

SMT

04

02

R2

21

2K

-04

02

SMT

04

02

R1

95

33

R-0

40

2SM

TR

19

53

3R

-04

02

SMT

R2

30

32

4R

-04

02

SMT

04

02

R2

30

32

4R

-04

02

SMT

04

02

12

R2

06

33

R-0

40

2SM

TR

20

63

3R

-04

02

SMT

R23649_9R-0402SMT

R23649_9R-0402SMT

C2

48

10

NF-

04

02

SMT

04

02

C2

48

10

NF-

04

02

SMT

04

02

12

R1

85

10

R-0

40

2SM

T0

40

2R

18

51

0R

-04

02

SMT

04

02

R2

31

32

4R

-04

02

SMT

04

02

R2

31

32

4R

-04

02

SMT

04

02

12

R2

05

2K

-04

02

SMT

04

02

R2

05

2K

-04

02

SMT

04

02

R2

20

33

R-0

40

2SM

TR

22

03

3R

-04

02

SMT

R2

15

47

0R

-06

03

SMT

04

02

R2

15

47

0R

-06

03

SMT

04

02

12

C2

66

10

0N

F-0

40

2SM

T0

40

2

C2

66

10

0N

F-0

40

2SM

T0

40

2

1 2

C2

50

22

UF-

16

V_

TA

NT

BSM

T

tan

tb

C2

50

22

UF-

16

V_

TA

NT

BSM

T

tan

tb1

2

R1

96

33

R-0

40

2SM

TR

19

63

3R

-04

02

SMT

R23349_9R-0402SMT

R23349_9R-0402SMT

R2

01

9_

76

K-0

40

2SM

T

04

02

R2

01

9_

76

K-0

40

2SM

T

04

02

12

R1

93

33

R-0

40

2SM

TR

19

33

3R

-04

02

SMT

C2

72

10

0N

F-0

40

2SM

T0

40

2

C2

72

10

0N

F-0

40

2SM

T0

40

2

1 2

C2

67

10

NF-

04

02

SMT

04

02

C2

67

10

NF-

04

02

SMT

04

02

1 2

R23449_9R-0402SMT

R23449_9R-0402SMT

C2

62

10

NF-

04

02

SMT

04

02

C2

62

10

NF-

04

02

SMT

04

02

1 2

R2

22

2K

-04

02

SMT

04

02

R2

22

2K

-04

02

SMT

04

02

C2

65

10

UF-

Ce

ram

ic X

5R

/08

05

SMT

08

05

C2

65

10

UF-

Ce

ram

ic X

5R

/08

05

SMT

08

05

1 2

C2

73

10

NF-

04

02

SMT

04

02

C2

73

10

NF-

04

02

SMT

04

02

1 2

1 2 3 6 4 5 7 8

RJ45

J35

RJ-

45

Be

lfu

se 0

82

6-1

A1

T-2

3

1 2 3 6 4 5 7 8

RJ45

J35

RJ-

45

Be

lfu

se 0

82

6-1

A1

T-2

3

MD

IA-

10

MD

AC

T1

2M

DIA

+1

1

SH

LD1

19

MD

IB+

4

MD

IB-

5M

DB

CT

6

MD

IC+

3

MD

CC

T1

MD

IC-

2

MD

ID+

8

MD

DC

T7

MD

ID-

9S

HLD

22

0

LED

1-

13

LED

1+

14

LED

2-

15

LED

2+

16

D1

4

LED-SMT1206_GREEN

D1

4

LED-SMT1206_GREEN

R23549_9R-0402SMT

R23549_9R-0402SMT

D1

3

LED-SMT1206_GREEN

D1

3

LED-SMT1206_GREEN

C2

57

10

NF-

04

02

SMT

04

02

C2

57

10

NF-

04

02

SMT

04

02

R2

14

2K

-04

02

SMT

R2

14

2K

-04

02

SMT

C2

68

10

0N

F-0

40

2SM

T0

40

2

C2

68

10

0N

F-0

40

2SM

T0

40

2

1 2

R2

08

33

R-0

40

2SM

TR

20

83

3R

-04

02

SMT

C2

49

22

UF-

16

V_

TA

NT

BSM

T

tan

tb

C2

49

22

UF-

16

V_

TA

NT

BSM

T

tan

tb1

2

C2

58

10

NF-

04

02

SMT

04

02

C2

58

10

NF-

04

02

SMT

04

02

Y6

25

MH

z/H

C4

9U

HC

-49

/U

Y6

25

MH

z/H

C4

9U

HC

-49

/U

C2

63

10

0N

F-0

40

2SM

T0

40

2

C2

63

10

0N

F-0

40

2SM

T0

40

2

1 2

R22449_9R-0402SMT

R22449_9R-0402SMT

R2

19

2K

-04

02

SMT

04

02

R2

19

2K

-04

02

SMT

04

02

C2

56

10

NF-

04

02

SMT

04

02

C2

56

10

NF-

04

02

SMT

04

02

1 2

R1

97

33

R-0

40

2SM

TR

19

73

3R

-04

02

SMT

R2

07

33

R-0

40

2SM

TR

20

73

3R

-04

02

SMT

C2

61

10

0N

F-0

40

2SM

T0

40

2

C2

61

10

0N

F-0

40

2SM

T0

40

2

1 2

R2

16

1M

-04

02

SMT

04

02

R2

16

1M

-04

02

SMT

04

02

2K

-04

02

SMT

04

02

8

C2

51

10

PF-

04

02

SMT

04

02

C2

51

10

PF-

04

02

SMT

04

02

1 2

R1

98

33

R-0

40

2SM

TR

19

83

3R

-04

02

SMT

C2

55

10

NF-

04

02

SMT

04

02

C2

55

10

NF-

04

02

SMT

04

02

1 2

R22549_9R-0402SMT

R22549_9R-0402SMT

R2

09

33

R-0

40

2SM

TR

20

93

3R

-04

02

SMT

R1

84

18

R-0

40

2SM

T0

40

2R

18

41

8R

-04

02

SMT

04

02

C2

64

10

NF-

04

02

SMT

04

02

C2

64

10

NF-

04

02

SMT

04

02

1 2

R2

18

2K

-04

02

SMT

04

02

R2

18

2K

-04

02

SMT

04

02

C2

71

10

NF-

04

02

SMT

04

02

C2

71

10

NF-

04

02

SMT

04

02

1 2

R1

94

33

R-0

40

2SM

TR

19

43

3R

-04

02

SMT

RX_VDD

U2

2

DP

83

86

5

RX_VDD

U2

2

DP

83

86

5

TM

S2

7

TD

O2

8

TD

I3

1

TR

ST

32

VDD25_096

VDD0100

IO_VDD215IO_VDD14

PGM_VDD098

CORE_VDD111

CORE_VDD219

CORE_VDD325

TC

K2

4

IO_VDD321

CORE_VDD435

IO_VDD429

IO_VDD537

CORE_VDD548

IO_VDD642

IO_VDD753

CORE_VDD663

IO_VDD858

CORE_VDD773

IO_VDD969

O_VDD083

IO_VDD1077

CORE_VDD892

IO_VDD1190

RX_DVDD0103

VDD1105

VDD2111

VDD3117

VDD4123

VSS0 99

PGM_VSS0 97

IO_VSS1 5

CORE_VSS1 12

CORE_VSS2 20

IO_VSS2 16

CORE_VSS3 26

IO_VSS3 22

CORE_VSS4 36

IO_VSS4 30

IO_VSS5 38

CORE_VSS5 49

IO_VSS6 43

IO_VSS7 54

CORE_VSS6 64

IO_VSS8 59

CORE_VSS7 74

IO_VSS9 70

O_VSS0 82

IO_VSS10 78

CORE_VSS8 93

IO_VSS11 91

RX_DVSS0 104

VSS1 106

CD_VSS1 107

CD_VSS2 110

VSS2 112

CD2_VSS1 113

CD2_VSS2 116

VSS3 118

CD3_VSS2 122CD3_VSS1 119

VSS4 124

CD4_VSS1 125

CD4_VSS2 128

EG

P0

(N

C_

MO

DE

)1

EG

P1

2

EG

P2

(In

terr

up

t)3

EG

P3

(T

X_

TC

LK)

6

EG

P4

(S

PE

ED

0 /

AC

T_

LED

)7

EG

P5

(S

PE

ED

1 /

LIN

K1

0)

8

EG

P6

(D

UP

LEX

_E

N /

LIN

K1

00

)9

EG

P7

(A

N_

EN

/ L

INK

10

00

)1

0

GP

0 (

PH

YA

D0

/ D

UP

LEX

_LE

D)

13

GP

1 (

PH

YA

D1

)1

4

GP

2 (

PH

YA

D2

)1

7

GP

3 (

PH

YA

D3

)1

8

GP

4 (

PH

YA

D4

)9

5

GP

5 (

MU

LTI_

EN

)9

4

GP

6 (

MD

IX_

EN

)8

9

GP

7 (

MA

C_

CLK

_E

N)

88

RX

D0

/ R

GM

II_R

XD

05

6

RX

D1

/ R

GM

II_R

XD

15

5

RX

D2

/ R

GM

II_R

XD

25

2

RX

D3

/ R

GM

II_R

XD

35

1

RX

D4

50

RX

D5

47

RX

D6

46

RX

D7

45

TX

D0

/ R

GM

II_T

XD

07

6

TX

D1

/ R

GM

II_T

XD

17

5

TX

D2

/ R

GM

II_T

XD

27

2

TX

D3

/ R

GM

II_T

XD

37

1

TX

D4

68

TX

D5

67

TX

D6

66

TX

D7

65

MD

IA_

P1

08

MD

IA_

N1

09

MD

IB_

P1

14

MD

IB_

N1

15

MD

IC_

P1

20

MD

IC_

N1

21

MD

ID_

P1

26

MD

ID_

N1

27

BG

_R

EF

10

2

TM

02

3

RE

SE

T_

N3

3

VD

D_

SE

L3

4

CO

L3

9C

RS

/ R

GM

II_S

EL1

40

RX

_E

R /

RG

MII_

RX

_C

TL

41

RX

_D

V /

RG

MII_

RX

C4

4

RX

_C

LK5

7

TX

_C

LK /

RG

MII_

SE

L06

0

TX

_E

R6

1

TX

_E

N /

RG

MII_

TX

_C

TL

62

GT

X_

CLK

/ R

GM

II_T

XC

79

MD

IO8

0

MD

C8

1

RE

F_S

EL

84

CLK

_T

O_

MA

C8

5

CLO

CK

_IN

86

CLO

CK

_O

UT

87

BG_VDD101

R1

99

33

R-0

40

2SM

TR

19

93

3R

-04

02

SMT

R2

17

47

0R

-06

03

SMT

04

02

R2

17

47

0R

-06

03

SMT

04

02

12

R22649_9R-0402SMT

R22649_9R-0402SMT

R2

13

33

R-0

40

2SM

TR

21

33

3R

-04

02

SMT

R1

86

33

R-0

40

2SM

TR

18

63

3R

-04

02

SMT

C2

60

10

NF-

04

02

SMT

04

02

C2

60

10

NF-

04

02

SMT

04

02

1 2

C25410NF-0402SMT

C25410NF-0402SMT

1 2

MH

2M

HO

LE_

10

.10

0_

PT

H

MH

2M

HO

LE_

10

.10

0_

PT

H

1

R2

00

33

R-0

40

2SM

TR

20

03

3R

-04

02

SMT

R1

92

33

R-0

40

2SM

TR

19

23

3R

-04

02

SMT

C2

52

10

PF-

04

02

SMT

04

02

C2

52

10

PF-

04

02

SMT

04

02

1 2

R2

38

2K

-04

02

SMT

04

02

R2

38

2K

-04

02

SMT

04

02

12

R1

90

33

R-0

40

2SM

TR

19

03

3R

-04

02

SMT

R1

87

33

R-0

40

2SM

TR

18

73

3R

-04

02

SMT

C2

70

10

0N

F-0

40

2SM

T0

40

2

C2

70

10

0N

F-0

40

2SM

T0

40

2

1 2

R22349_9R-0402SMT

R22349_9R-0402SMT

C2

59

10

0N

F-0

40

2SM

T0

40

2

C2

59

10

0N

F-0

40

2SM

T0

40

2

1 2

C2

74

10

NF-

04

02

SMT

04

02

C2

74

10

NF-

04

02

SMT

04

02

1 2

R2

02

33

R-0

40

2SM

TR

20

23

3R

-04

02

SMT

R1

91

33

R-0

40

2SM

TR

19

13

3R

-04

02

SMT

R2

29

2K

-04

02

SMT

04

02

R2

29

2K

-04

02

SMT

04

02

12

MH

1M

HO

LE_

10

.10

0_

PT

H

MH

1M

HO

LE_

10

.10

0_

PT

H

1

R1

88

33

R-0

40

2SM

TR

18

83

3R

-04

02

SMT

R2

11

33

R-0

40

2SM

TR

21

13

3R

-04

02

SMT

R2

03

33

R-0

40

2SM

TR

20

33

3R

-04

02

SMT

C2

69

10

NF-

04

02

SMT

04

02

C2

69

10

NF-

04

02

SMT

04

02

1 2

R2

32

2K

-04

02

SMT

04

02

R2

32

2K

-04

02

SMT

04

02

12

C2

53

1U

F-1

6V

-08

05

SMT

08

05

C2

53

1U

F-1

6V

-08

05

SMT

08

05

1 2

R1

89

33

R-0

40

2SM

TR

18

93

3R

-04

02

SMT

R2

27

2K

-04

02

SMT

04

02

R2

27

2K

-04

02

SMT

04

02

12

R2

12

33

R-0

40

2SM

TR

21

23

3R

-04

02

SMT

R2

28

32

4R

-04

02

SMT

04

02

R2

28

32

4R

-04

02

SMT

04

02

12

R2

04

33

R-0

40

2SM

TR

20

43

3R

-04

02

SMT

27

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 14. RLDRAM

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VR

EF_

B

RLD

RA

M_

REF

#

RLD

RA

M_

QK

0

RLD

RA

M_

D3

RLD

RA

M_

D2

RLD

RA

M_

D1

RLD

RA

M_

D0

RLD

RA

M_

D8

RLD

RA

M_

D7

RLD

RA

M_

D6

RLD

RA

M_

D5

RLD

RA

M_

D4

RLD

RA

M_

D1

7R

LDR

AM

_D

16

RLD

RA

M_

D1

5R

LDR

AM

_D

14

RLD

RA

M_

D1

3R

LDR

AM

_D

12

RLD

RA

M_

D1

1R

LDR

AM

_D

10

RLD

RA

M_

D9

RLD

RA

M_

QK

1

RLD

RA

M_

QV

LD

RLD

RA

M_

CS#

RLD

RA

M_

WE#

RLD

RA

M_

A8

RLD

RA

M_

A6

RLD

RA

M_

A5

RLD

RA

M_

A4

RLD

RA

M_

A3

RLD

RA

M_

A7

RLD

RA

M_

A2

RLD

RA

M_

A1

RLD

RA

M_

A0

RLD

RA

M_

DM

RLD

RA

M_

A1

6R

LDR

AM

_A

15

RLD

RA

M_

A1

4R

LDR

AM

_A

13

RLD

RA

M_

A1

2R

LDR

AM

_A

11

RLD

RA

M_

A1

0R

LDR

AM

_A

9

RLD

RA

M_

A1

8R

LDR

AM

_A

19

RLD

RA

M_

A2

0R

LDR

AM

_A

21

RLD

RA

M_

A2

2

RLD

RA

M_

CK

#R

LDR

AM

_C

K

RLD

RA

M_

DK

#R

LDR

AM

_D

K

RLD

RA

M_

REF

#

RLD

RA

M_

BA

2

RLD

RA

M_

CS#

RLD

RA

M_

WE#

RLD

RA

M_

DM

RLD

RA

M_

BA

2R

LDR

AM

_B

A1

RLD

RA

M_

BA

0

RLD

RA

M_

A1

7R

LDR

AM

_Q

8R

LDR

AM

_Q

9R

LDR

AM

_Q

10

RLD

RA

M_

Q1

1R

LDR

AM

_Q

12

RLD

RA

M_

Q1

3R

LDR

AM

_Q

14

RLD

RA

M_

Q1

5

RLD

RA

M_

Q1

RLD

RA

M_

Q1

6R

LDR

AM

_Q

17

RLD

RA

M_

Q2

RLD

RA

M_

Q3

RLD

RA

M_

Q4

RLD

RA

M_

Q5

RLD

RA

M_

Q6

RLD

RA

M_

Q7

RLD

RA

M_

Q0

RLD

RA

M_

A1

9R

LDR

AM

_A

18

RLD

RA

M_

A1

7R

LDR

AM

_A

16

RLD

RA

M_

A1

5R

LDR

AM

_A

14

RLD

RA

M_

A1

3R

LDR

AM

_A

12

RLD

RA

M_

A1

1R

LDR

AM

_A

10

RLD

RA

M_

A9

RLD

RA

M_

A8

RLD

RA

M_

A6

RLD

RA

M_

A5

RLD

RA

M_

A4

RLD

RA

M_

A3

RLD

RA

M_

A7

RLD

RA

M_

A2

RLD

RA

M_

A1

RLD

RA

M_

A0

VR

EF_

RLD

VR

EF_

B_

W

RLD

RA

M_

BA

1R

LDR

AM

_B

A0

RLD

RA

M_

A2

0R

LDR

AM

_A

21

RLD

RA

M_

A2

2

2_

5V

RLD

RA

M_

VT

T

1_

8V

RLD

RA

M_

VT

T

RLD

RA

M_

VEX

T

RLD

RA

M_

VD

D

RLD

RA

M_

VEX

T

2_

5V

RLD

RA

M_

VEX

T

RLD

RA

M_

VD

D

1_

8V

RLD

RA

M_

VD

D

RLD

RA

M_

VD

DQ

1_

8V

RLD

RA

M_

VD

DQ

RLD

RA

M_

VEX

T

RLD

RA

M_

VD

DQ

RLD

RA

M_

VD

D

RLD

RA

M_

VD

DQ

RLD

RA

M_

VD

DQ

RLD

RA

M_

VT

T

RLD

RA

M_

QK

0[1

2]

RLD

RA

M_

D[0

:17

][1

2]

RLD

RA

M_

QV

LD[1

2]

RLD

RA

M_

CK

[12

]

RLD

RA

M_

DK

#[1

2]

RLD

RA

M_

REF

#[1

2]

RLD

RA

M_

BA

1[1

2]

RLD

RA

M_

WE#

[12

]

RLD

RA

M_

CK

#[1

2]

RLD

RA

M_

DK

[12

]

RLD

RA

M_

BA

2[1

2]

RLD

RA

M_

CS#

[12

]

RLD

RA

M_

BA

0[1

2]

RLD

RA

M_

DM

[12

]

RLD

RA

M_

QK

1[1

2]

RLD

RA

M_

Q[0

:17

][1

2]

RLD

RA

M_

A[0

:19

][1

2]

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

RLD

RA

M

C

11

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

RLD

RA

M

C

11

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

RLD

RA

M

C

11

14

Place resistors as close to RLDRAM device as possible.

Place SP Testpoints (.025 square pads)

around RLDRAM BGA

as close as possible to edge balls.

C307

100NF-0603SMT

C307

100NF-0603SMT

R2

47

22

0R

-06

03

SMT

R2

47

22

0R

-06

03

SMT

+

C297

47UF-16V_TANTBSMT

+

C297

47UF-16V_TANTBSMT

R1

R1

R1=50 Ohm

RP

4C

TS-

RT

14

02

B7

R1

R1

R1=50 Ohm

RP

4C

TS-

RT

14

02

B7

A2A2

B2B2

C2C2

D2D2

E2E2

F2F2

G2G2

H2H2

J2J2

A3

A3

B3

B3

C3

C3

D3

D3

E3

E3

F3F3

G3

G3

H3

H3

J3J3

A1

A1

B1

B1

C1

C1

D1

D1

E1

E1

F1F1

G1

G1

H1

H1

J1J1

R2

40

1K

_A

DJ/

SMT

3M

MR

24

01

K_

AD

J/SM

T3

MM

C314

100NF-0603SMT

C314

100NF-0603SMT

C290

10NF-0603SMT

C290

10NF-0603SMT

+

C284

47UF-16V_TANTBSMT +

C284

47UF-16V_TANTBSMT

C3

04

1UF-16V-0805SMT

C3

04

1UF-16V-0805SMT

FB5

BLM

41

PG

47

1SN

1L

FB5

BLM

41

PG

47

1SN

1L

C285

1UF-16V-0805SMT

C285

1UF-16V-0805SMT

C2

99

1UF-16V-0805SMT

C2

99

1UF-16V-0805SMT

C315

10NF-0603SMT

C315

10NF-0603SMT

U2

4

LP2

99

6-S

O8

U2

4

LP2

99

6-S

O8

GND 1

SD

2

VS

EN

SE

3V

RE

F4

VD

DQ

5

AVIN6PVIN7

VT

T8

C292

10NF-0603SMT

C292

10NF-0603SMT

R2

46

OP

EN-0

60

3SM

TR

24

6O

PEN

-06

03

SMT

SP2

SP2

1

+C

29

8

22UF-16V_TANTBSMT

+C

29

8

22UF-16V_TANTBSMT

C283

100NF-0603SMT

C283

100NF-0603SMT

C291

100NF-0603SMT

C291

100NF-0603SMT

C316

100NF-0603SMT

C316

100NF-0603SMT

C280

10NF-0603SMT

C280

10NF-0603SMT

+C

30

3

22UF-16V_TANTBSMT

+C

30

3

22UF-16V_TANTBSMT

C2

88

1UF-16V-0805SMT

C2

88

1UF-16V-0805SMT

C309

100NF-0603SMT

C309

100NF-0603SMT

C3

13

1UF-16V-0805SMT

C3

13

1UF-16V-0805SMT

C3

10

1UF-16V-0805SMT

C3

10

1UF-16V-0805SMT

C308

100NF-0603SMT

C308

100NF-0603SMT

R2

42

0R

-06

03

SMT

R2

42

0R

-06

03

SMT

C282

10NF-0603SMT

C282

10NF-0603SMT

SP3

SP3

1

+C

31

2

22UF-16V_TANTBSMT

+C

31

2

22UF-16V_TANTBSMT

+C

28

9

100UF-FKSMT+C

28

9

100UF-FKSMT

C277

100NF-0603SMT

C277

100NF-0603SMT

C281

100NF-0603SMT

C281

100NF-0603SMT

+

C311

47UF-16V_TANTBSMT

+

C311

47UF-16V_TANTBSMT

C2

94

1UF-16V-0805SMT

C2

94

1UF-16V-0805SMT

SP4

SP4

1

C287

100NF-0603SMT

C287

100NF-0603SMT

C279

10NF-0603SMT

C279

10NF-0603SMT

SP1

SP1

1

R1

R1

R1=50 Ohm

RP

3C

TS-

RT

14

02

B7

R1

R1

R1=50 Ohm

RP

3C

TS-

RT

14

02

B7

A2A2

B2B2

C2C2

D2D2

E2E2

F2F2

G2G2

H2H2

J2J2

A3

A3

B3

B3

C3

C3

D3

D3

E3

E3

F3F3

G3

G3

H3

H3

J3J3

A1

A1

B1

B1

C1

C1

D1

D1

E1

E1

F1F1

G1

G1

H1

H1

J1J1

+

C295

47UF-16V_TANTBSMT

+

C295

47UF-16V_TANTBSMT

C278

100NF-0603SMT

C278

100NF-0603SMT

R2

45

0R

-06

03

SMT

R2

45

0R

-06

03

SMT

SP5

SP5

1FB

6

BLM

41

PG

47

1SN

1L

FB6

BLM

41

PG

47

1SN

1L

R2

41

1K-0603SMT

R2

41

1K-0603SMT

SP6

SP6

1

C305

100NF-0603SMT

C305

100NF-0603SMTRLDRAM-II

CIO/SIO

144-BALL FBGA

U2

3

RLD

RA

M_

II_C

IO_

SIO

_0

RLDRAM-II

CIO/SIO

144-BALL FBGA

U2

3

RLD

RA

M_

II_C

IO_

SIO

_0

VR

EF

A1

VR

EF

V1

ZQ V2

NFU

1J1

NFU

2J2

VD

DQ

C4

VD

DQ

C9

VD

DQ

E4

VD

DQ

E9

VD

DQ

P4

VD

DQ

P9

VD

DQ

T4

VD

DQ

T9

VD

DK

10

VD

DK

9

VD

DK

4

VD

DK

3

VD

DB

1

VD

DG

4

VD

DG

9

VD

DJ3

VD

DJ4

VD

DJ9

VD

DJ1

0

VD

DM

9

VD

DM

4

VD

DU

1

VD

DU

12

VD

DB

12

VS

SV

9

VS

SV

4

VS

SR

1

VS

SL1

0

VS

SL9

VS

SL4

VS

SL3

VS

SA

2

VS

SA

4

VS

SA

9

VS

SD

12

VS

SH

3

VS

SH

4

VS

SH

9

VS

SH

10

VS

SR

12

VS

SQ

U9

VS

SQ

U4

VS

SQ

B4

VS

SQ

B9

VS

SQ

D4

VS

SQ

D9

VS

SQ

F4

VS

SQ

F9

VS

SQ

N4

VS

SQ

N9

VS

SQ

R4

VS

SQ

R9

TD

IV

12

TD

OV

11

TM

SA

11

TC

KA

12

VT

TT

12

VT

TT

1

VT

TC

12

VT

TC

1

VE

XT

V1

0

VE

XT

V3

VE

XT

A1

0

VE

XT

A3

Q1

7U

3

Q1

6T

3

Q1

5P

3

Q1

4N

3

Q1

3U

10

Q1

2T

10

Q1

1R

10

Q1

0P

10

Q9

N1

0

Q8

F3

Q7

E3

Q6

D3

Q5

C3

Q4

B3

Q3

F10

Q2

E1

0

Q1

C1

0

Q0

B1

0

QK

0D

11

QK

0#

D1

0Q

K1

#R

3Q

K1

R2

A0

G1

2

A1

G1

1

A2

G1

0

A3

H1

2

A4

H1

1

A5

F1

A6

G2

A7

G3

A8

G1

A9

H2

A1

0M

12

A1

1M

11

A1

2M

10

A1

3L1

2

A1

4L1

1

A1

5P

1

A1

6M

2

A1

7M

3

A1

8N

1

A1

9N

12

A2

0E

12

A2

1E

1

A2

2D

1

D0

B1

1

D1

C1

1

D2

E1

1

D3

F11

D4

B2

D5

C2

D6

D2

D7

E2

D8

F2

D9

N1

1

D1

0P

11

D1

1R

11

D1

2T

11

D1

3U

11

D1

4N

2

D1

5P

2

D1

6T

2

D1

7U

2

RE

F#L1

CS

#L2

WE

#M

1

DM

P1

2

CK

#K

12

CK

J12

B2

H1

B1

K1

1

B0

J11

DK

K1

DK

#K

2

QV

LDF1

2

C293

100NF-0603SMT

C293

100NF-0603SMT

SP7

SP7

1

R2

44

OP

EN-0

60

3SM

TR

24

4O

PEN

-06

03

SMT

FB4

BLM

41

PG

47

1SN

1L

FB4

BLM

41

PG

47

1SN

1L

C300

100NF-0603SMT

C300

100NF-0603SMT

C306

10NF-0603SMT

C306

10NF-0603SMT

SP8

SP8

1

C2

76

1UF-16V-0805SMT

C2

76

1UF-16V-0805SMT

R2434_7K-0603SMT

R2434_7K-0603SMT

C301

10NF-0603SMT

C301

10NF-0603SMT

+C

28

6

10UF-16V_TANTBSMT

+C

28

6

10UF-16V_TANTBSMT

+C

27

5

22UF-16V_TANTBSMT

+C

27

5

22UF-16V_TANTBSMT

C2

96

1UF-16V-0805SMT

C2

96

1UF-16V-0805SMT

R2

39

1K-0603SMT

R2

39

1K-0603SMT

C302

100NF-0603SMT

C302

100NF-0603SMT

28

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 15. FPGA Banks

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QD

R_

REA

D_

N

QD

R_

WR

ITE_

N

QD

R_

A4

QD

R_

A0

QD

R_

A1

QD

R_

A2

QD

R_

A3

QD

R_

A5

QD

R_

A6

QD

R_

A7

QD

R_

A8

QD

R_

A9

QD

R_

A1

0

QD

R_

A1

1

QD

R_

A1

2

QD

R_

A1

3

QD

R_

A1

4

QD

R_

A1

5

QD

R_

A1

7Q

DR

_A

16

QD

R_

D1

2

QD

R_

D1

0

QD

R_

D1

1

QD

R_

D1

3Q

DR

_D

14

QD

R_

D1

5Q

DR

_D

16

QD

R_

D3

QD

R_

D5

QD

R_

D0

QD

R_

D1

QD

R_

D1

7

QD

R_

D2

QD

R_

D4

QD

R_

D6

QD

R_

D9

QD

R_

D7

QD

R_

D8

QDR_Q[0..17]

QD

R_

Q0

QD

R_

Q1

QD

R_

Q2

QD

R_

Q3

QD

R_

Q4

QD

R_

Q5

QD

R_

Q7

QD

R_

Q8

QD

R_

Q6

QD

R_

Q9

QD

R_

Q1

0

QD

R_

Q1

2

QD

R_

Q1

4Q

DR

_Q

13

QD

R_

Q1

1

QD

R_

Q1

5Q

DR

_Q

16

QD

R_

Q1

7

QD

R_

KQ

DR

_K

#

QDR_D[0..17]

LOO

P_

P2

LOO

P_

N2

LOO

P_

P3

LOO

P_

N3

LOO

P_

P1

LOO

P_

N1

LOO

P_

P0

LOO

P_

N0

LOO

P_

P0

LOO

P_

N0

LOO

P_

P1

LOO

P_

N1

DIF

FR_

3

DIF

FR_

3

LVD

S_O

UT

PLV

DS_

OU

TN

SC_

QD

R_

VR

EF

SC_

QD

R_

VR

EF

SC_

QD

R_

VR

EF

LOO

P_

N2

LOO

P_

P2

LOO

P_

N3

LOO

P_

P3

LVD

S_IN

PLV

DS_

INN

LVD

S_P

RO

BEN

LVD

S_P

RO

BEP

LA_

12

LA_

14

LA_

11

LA_

13

LA_

7

LA_

5

LA_

10

LA_

9

LA_

6

LA_

4

LA_

2LA

_1

LA_

8

LA_

0

LA_

3

LA_

15

LA_

31

LA_

30

LA_

25

LA_

27

LA_

22

LA_

29

LA_

21

LA_

24

LA_

20

LA_

28

LA_

26

LA_

19

LA_

17

LA_

18

LA_

16

LA_

23

RLD

RA

M_

A1

9R

LDR

AM

_A

18

RLD

RA

M_

A1

7R

LDR

AM

_A

16

RLD

RA

M_

A1

5R

LDR

AM

_A

14

RLD

RA

M_

A1

3R

LDR

AM

_A

12

RLD

RA

M_

A1

1R

LDR

AM

_A

10

RLD

RA

M_

A9

RLD

RA

M_

A8

RLD

RA

M_

A6

RLD

RA

M_

A5

RLD

RA

M_

A4

RLD

RA

M_

A3

RLD

RA

M_

A7

RLD

RA

M_

A2

RLD

RA

M_

A1

RLD

RA

M_

A0

RLD

RA

M_

Q1

RLD

RA

M_

D0

RLD

RA

M_

D4

RLD

RA

M_

D1

7R

LDR

AM

_D

16

RLD

RA

M_

D1

5R

LDR

AM

_D

14

RLD

RA

M_

D1

2R

LDR

AM

_D

11

RLD

RA

M_

D1

3

RLD

RA

M_

D1

0

RLD

RA

M_

D1

RLD

RA

M_

Q1

5

RLD

RA

M_

Q2

RLD

RA

M_

Q3

RLD

RA

M_

Q0

RLD

RA

M_

Q4

RLD

RA

M_

Q1

1

RLD

RA

M_

Q5

RLD

RA

M_

Q1

0

RLD

RA

M_

Q6

RLD

RA

M_

Q1

7

RLD

RA

M_

Q7

RLD

RA

M_

Q1

6

RLD

RA

M_

Q8

RLD

RA

M_

Q9

RLD

RA

M_

Q1

2

RLD

RA

M_

Q1

3R

LDR

AM

_Q

14

RLD

RA

M_

BA

0R

LDR

AM

_B

A1

RLD

RA

M_

BA

2

RLD

RA

M_

CK

RLD

RA

M_

CK

#

RLD

RA

M_

CS#

RLD

RA

M_

DM

RLD

RA

M_

QV

LD

RLD

RA

M_

WE#

RLD

RA

M_

REF

#

SC_

RLD

RA

M_

VR

EFSC

_R

LDR

AM

_V

REF

RLD

RA

M_

DK

#R

LDR

AM

_D

K

RLD

RA

M_

D2

RLD

RA

M_

D3

RLD

RA

M_

D8

RLD

RA

M_

D7

RLD

RA

M_

D9

RLD

RA

M_

D6

RLD

RA

M_

D5

LA_

CLK

2LA

_C

LK1

LA_

CLK

2LA

_C

LK1

LA_

2

LA_

1LA

_0

LA_

3

LA_

7

LA_

5

LA_

10

LA_

9

LA_

6

LA_

4

LA_

8

LA_

12

LA_

14

LA_

11

LA_

13

LA_

22

LA_

23

LA_

19

LA_

20

LA_

21

LA_

15

LA_

17

LA_

18

LA_

16

LA_

24

LA_

31

LA_

25

LA_

27

LA_

29

LA_

30

LA_

26

LA_

28

SWIT

CH

5SW

ITC

H6

SWIT

CH

8

SWIT

CH

3SW

ITC

H2

SWIT

CH

4

SWIT

CH

1

SWIT

CH

7

QD

R_

A4

QD

R_

A5

QD

R_

A6

QD

R_

A7

QD

R_

A8

QD

R_

A9

QD

R_

A1

0Q

DR

_A

11

QD

R_

A1

2Q

DR

_A

13

QD

R_

A1

4Q

DR

_A

15

QD

R_

A1

7Q

DR

_A

16

QDR_A[0..17]

QD

R_

A0

QD

R_

A1

QD

R_

A2

QD

R_

A3

SC_

QD

R_

VR

EF

SC_

QD

R_

VR

EF

LED

5LE

D6

LED

1LE

D2

LED

3LE

D4

LED

7

LED

8

RLD

RA

M_

QK

0R

LDR

AM

_Q

K1

QD

R_

CQ

ETH

_C

LK_

TO

_M

AC

ETH

_R

X_

D1

ETH

_R

X_

D3

ETH

_R

X_

D0

ETH

_R

X_

D2

ETH

_T

X_

D4

ETH

_T

X_

D6

ETH

_T

X_

D5

ETH

_T

X_

D7

ETH

_T

X_

D0

ETH

_T

X_

D1

ETH

_T

X_

D2

ETH

_T

X_

D3

ETH

_T

X_

ENET

H_

TX

_C

LKET

H_

GT

X_

CLK

ETH

_R

X_

DV

ETH

_C

OL

ETH

_C

RS

ETH

_R

X_

CLK

ETH

_R

X_

D6

ETH

_R

X_

D4

ETH

_R

X_

D7

ETH

_R

X_

D5

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

SGN

D

QD

R_

REA

D_

N[9

]

QD

R_

WR

ITE_

N[9

]

QD

R_

D[0

..17

][9

]

QD

R_

Q[0

..17

][9

]

QD

R_

K[9

]Q

DR

_K

_#

[9]

SC_

QD

R_

VR

EF[3

]

LVD

S_IN

P[1

3]

LVD

S_IN

N[1

3]

LVD

S_P

RO

BEN

[13

]LV

DS_

PR

OB

EP[1

3]

LA_

[0..3

1]

[13

]

RLD

RA

M_

Q[0

:17

][1

1]

RLD

RA

M_

A[0

:19

][1

1]

RLD

RA

M_

BA

0[1

1]

RLD

RA

M_

BA

1[1

1]

RLD

RA

M_

BA

2[1

1]

RLD

RA

M_

CK

[11

]R

LDR

AM

_C

K#

[11

]

RLD

RA

M_

CS#

[11

]

RLD

RA

M_

DM

[11

]

RLD

RA

M_

QV

LD[1

1]

RLD

RA

M_

WE#

[11

]

RLD

RA

M_

REF

#[1

1]

SC_

RLD

RA

M_

VR

EF[3

]

RLD

RA

M_

DK

#[1

1]

RLD

RA

M_

DK

[11

]

RLD

RA

M_

D[0

:17

][1

1]

LA_

CLK

2[1

3]

LA_

CLK

1[1

3]SW

ITC

H[1

..8]

[13

]

QD

R_

A[0

..17

][9

]

LVD

S_O

UT

N[1

3]

LVD

S_O

UT

P[1

3]

PC

IE_

CLK

N[5

]P

CIE

_C

LKP

[5]

FPG

A_

REF

CLK

P_

R[8

]FP

GA

_R

EFC

LKN

_R

[8]

LED

[1..8

][1

3]

RLD

RA

M_

QK

0[1

1]

RLD

RA

M_

QK

1[1

1]

QD

R_

CQ

[9]

ETH

_C

LK_

TO

_M

AC

[10

]FP

GA

_R

EFC

LKP

_L

[8]

FPG

A_

REF

CLK

N_

L[8

]

ETH

_R

X_

D[0

..7]

[10

]

ETH

_T

X_

D[0

..7]

[10

]

ETH

_T

X_

CLK

[10

] ETH

_G

TX

_C

LK[1

0]

ETH

_T

X_

EN[1

0]ET

H_

RX

_D

V[1

0]

ETH

_C

RS

[10

]ET

H_

CO

L[1

0]

ETH

_R

X_

CLK

[10

]

OSC

_IN

_3

[7]

OSC

_IN

_4

[7]

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

FPG

A B

anks

C

12

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

FPG

A B

anks

C

12

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

FPG

A B

anks

C

12

14

LOOP[2:3],

Not

Available in SCM15

SCM15 QDR MACO PREFERRED PINS

MUST USE LVCMOS18 BUFFER TYPESFOR LOGIC ANALYZER

LEDs

and

Switches

Available

in SCM15

& SCM25

SCM25 RLDRAM MACO PREFERRED PINS

BANK 2, 3, 4, 5, 6

VCCIO = 1.8V

BANK 7

VCCIO = 2.5V

PHY to MAC Interface/

Available in SCM15 & SCM25

Off Page Connections

R2

85

0R

-06

03

SMT

R2

85

0R

-06

03

SMT

R2501_1K-0603SMT

R2501_1K-0603SMT

R2

48

BO

UR

NS-

32

24

W-2

02

E-2

K

R2

48

BO

UR

NS-

32

24

W-2

02

E-2

K

SC-900FPBGA

LEFT

Bank 7

Bank 6

U1

M SC2

5-9

00

fpB

GA

SC-900FPBGA

LEFT

Bank 7

Bank 6

U1

M SC2

5-9

00

fpB

GA

PL5

5C

/LLC

_D

LLT

_IN

_E

/LLC

_D

LLT

_FB

_F

AB

6

PL5

5D

/LLC

_D

LLC

_IN

_E

/LLC

_D

LLC

_FB

_F

AC

5

PL5

7C

/LLC

_P

LLT

_IN

_B

/LLC

_P

LLT

_FB

_A

AC

6

PL5

7D

/LLC

_P

LLC

_IN

_B

/LLC

_P

LLC

_FB

_A

AC

7

PL3

0C

/PC

LKT

6_

3P

4

PL5

6A

AE

3

PL1

6C

/DE

BU

G_

BU

S1

3J6

PL1

6D

J5

PL1

7C

/ULC

_P

LLT

_IN

_B

/ULC

_P

LLT

_FB

_A

K4

PL1

7D

/ULC

_P

LLC

_IN

_B

/ULC

_P

LLC

_FB

_A

J4

PL1

8C

/DE

BU

G_

BU

S1

2K

5

PL1

8D

/VR

EF2

_7

/DE

BU

G_

BU

S6

K6

PL2

2C

E1

PL2

2D

D1

PL2

1A

L5

PL2

1B

M5

PL1

6A

/ULC

_P

LLT

_IN

_A

/ULC

_P

LLT

_FB

_B

/DE

BU

G_

BU

S1

1D

3

PL1

6B

/ULC

_P

LLC

_IN

_A

/ULC

_P

LLC

_FB

_B

/DE

BU

G_

BU

S1

0D

2

PL1

7A

/ULC

_D

LLT

_IN

_C

/ULC

_D

LLT

_FB

_D

/DE

BU

G_

BU

S9

E3

PL1

7B

/ULC

_D

LLC

_IN

_C

/ULC

_D

LLC

_FB

_D

/DE

BU

G_

BU

S8

E2

PL1

8A

/ULC

_D

LLT

_IN

_D

/ULC

_D

LLT

_FB

_C

F3

PL1

8B

/ULC

_D

LLC

_IN

_D

/ULC

_D

LLC

_FB

_C

G3

PL2

0A

G2

PL2

0B

G1

PL2

5A

/TE

ST

CFG

NK

3

PL2

5B

/DE

BU

G_

BU

S7

L3

PL2

2A

F2

PL2

2B

F1

PL2

9A

/PC

LKT

6_

0N

2

PL2

9B

/PC

LKC

6_

0N

1

PL3

0A

N3

PL3

0B

P3

PL3

1A

P2

PL3

1B

R2

PL3

4A

P1

PL3

4B

R1

PL3

5A

T2

PL3

5B

U2

PL4

7A

Y2

PL4

7B

AA

2

PL4

8B

AC

1P

L48

AA

B1

PL5

6B

AF3

PL2

5C

/VR

EF1

_7

/DE

BU

G_

BU

S5

L6

PL2

5D

/DIF

FR_

7/D

EB

UG

_B

US

4M

6

PL3

5C

T6

PL2

9C

/PC

LKT

6_

1R

7

PL2

9D

/PC

LKC

6_

1R

6

PL3

1C

/PC

LKT

6_

2T

3

PL3

1D

/PC

LKC

6_

2R

3

PL3

4C

/VR

EF1

_6

R5

PL3

4D

R4

PL4

7C

Y3

PL4

7D

W3

PL4

9A

Y5

PL4

9B

Y6

PL5

1A

AD

2

PL5

1B

AE

2

PL5

2A

AC

3

PL5

2B

AD

3

PL5

3A

AC

4

PL5

3B

AD

4

PL5

5A

AF1

PL5

5B

AG

1

PL5

7A

/LLC

_D

LLT

_IN

_F/

LLC

_D

LLT

_FB

_E

AF2

PL5

7B

/LLC

_D

LLC

_IN

_F/

LLC

_D

LLC

_FB

_E

AG

2

PL5

1D

/VR

EF2

_6

AB

5

PL4

8C

W5

PL2

6B

/PC

LKC

7_

1/D

EB

UG

_B

US

2K

1P

L26

A/P

CLK

T7

_1

/DE

BU

G_

BU

S3

J1

PL2

7A

/PC

LKT

7_

0/D

EB

UG

_B

US

1L1

PL2

7B

/PC

LKC

7_

0/D

EB

UG

_B

US

0M

1

PL2

7C

/PC

LKT

7_

2/D

EB

UG

_B

US

14

P8

PL2

7D

/PC

LKC

7_

2/D

EB

UG

_B

US

15

R8

PL3

6A

U3

PL3

6B

V3

PL3

8A

T1

PL3

8B

U1

PL3

9A

T5

PL3

9B

T4

PL4

0A

U4

PL4

0B

U5

PL4

2A

V1

PL4

2B

W1

PL4

2C

U6

PL4

2D

/DIF

FR_

6V

6

PL4

3A

V2

PL4

3B

W2

PL4

3C

V5

PL4

3D

V4

PL4

4A

Y1

PL4

4B

AA

1

R2

49

0R

-06

03

SMT

R2

49

0R

-06

03

SMT

SC-900FPBGA

Bottom

Bank 5

Bank 4

U1

J

SC2

5-9

00

fpB

GA

SC-900FPBGA

Bottom

Bank 5

Bank 4

U1

J

SC2

5-9

00

fpB

GA

PB

4C

AD

6

PB

5A

AJ2

PB

5B

AK

2

PB

5C

AD

7

PB

7A

AF7

PB

7B

AF6

PB

8A

AH

4

PB

8B

AG

5

PB

9A

AF8

PB

9B

AG

8

PB

11

BA

J3

PB

11

CA

F9

PB

11

DA

E1

0

PB

12

AA

K3

PB

16

BA

K5

PB

28

BA

K1

1

PB

29

AA

H1

5

PB

29

BA

G1

5

PB

31

AA

H1

2

PB

31

BA

J13

PB

31

CA

D1

5

PB

31

DA

E1

5

PB

32

AA

K1

2

PB

32

BA

K1

3

PB

33

AA

J14

PB

33

BA

J15

PB

35

AA

K1

4

PB

37

AA

K1

6

PB

41

BA

K1

9

PB

3A

/LLC

_P

LLT

_IN

_A

/LLC

_P

LLT

_FB

_B

AH

1

PB

4A

/LLC

_D

LLT

_IN

_D

/LLC

_D

LLT

_FB

_C

AG

3

PB

4B

/LLC

_D

LLC

_IN

_D

/LLC

_D

LLC

_FB

_C

AH

2

PB

23

B/P

CLK

C5

_0

AJ1

2

PB

5D

/VR

EF1

_5

AD

8

PB

3B

/LLC

_P

LLC

_IN

_A

/LLC

_P

LLC

_FB

_B

AJ1

PB

3C

/LLC

_D

LLT

_IN

_C

/LLC

_D

LLT

_FB

_D

AF4

PB

3D

/LLC

_D

LLC

_IN

_C

/LLC

_D

LLC

_FB

_D

AE

5

PB

11

AA

H3

PB

35

BA

K1

5

PB

28

AA

K1

0P

B2

5B

/PC

LKC

5_

2A

G1

4P

B2

5A

/PC

LKT

5_

2A

H1

4

PB

12

BA

J4

PB

13

AA

E1

1

PB

13

BA

F10

PB

15

AA

H7

PB

15

BA

H8

PB

15

CA

E1

2

PB

15

DA

E1

3

PB

16

AA

K4

PB

17

AA

J5

PB

17

BA

J6

PB

19

AA

J7

PB

19

BA

J8

PB

20

A/P

CLK

T5

_3

AH

10

PB

20

B/P

CLK

C5

_3

AH

11

PB

20

C/P

CLK

T5

_4

AF1

3

PB

20

D/P

CLK

C5

_4

AE

14

PB

21

A/P

CLK

T5

_5

AK

6

PB

21

B/P

CLK

C5

_5

AK

7

PB

21

C/D

IFFR

_5

AF1

4

PB

21

DA

F15

PB

23

A/P

CLK

T5

_0

AJ1

1

PB

23

CA

G1

3

PB

23

D/V

RE

F2_

5A

H1

3

PB

24

B/P

CLK

C5

_1

AK

9P

B2

4A

/PC

LKT

5_

1A

K8

PB

52

C/P

CLK

T4

_4

AE

19

PB

49

DA

F19

PB

47

B/P

CLK

C4

_1

AG

18

PB

57

BA

E2

3P

B5

7A

AD

23

PB

56

CA

H2

1P

B5

6B

AH

23

PB

56

AA

H2

2P

B5

5B

AG

22

PB

53

BA

F21

PB

53

AA

E2

1

PB

37

BA

K1

7

PB

38

AA

J16

PB

38

BA

J17

PB

38

CA

E1

6

PB

39

AA

H1

6

PB

39

BA

G1

6

PB

38

DA

F16

PB

42

AA

H1

7

PB

41

AA

K1

8

PB

42

BA

H1

8

PB

42

CA

F17

PB

42

DA

G1

7

PB

43

AA

J18

PB

43

BA

J19

PB

46

A/P

CLK

T4

_2

AK

20

PB

46

B/P

CLK

C4

_2

AK

21

PB

47

A/P

CLK

T4

_1

AF1

8

PB

49

A/P

CLK

T4

_0

AJ2

0

PB

49

C/V

RE

F2_

4A

G1

9

PB

51

A/P

CLK

T4

_5

AK

22

PB

51

B/P

CLK

C4

_5

AK

23

PB

51

C/D

IFFR

_4

AH

19

PB

51

DA

H2

0

PB

52

D/P

CLK

C4

_4

AE

20

PB

52

B/P

CLK

C4

_3

AK

25

PB

52

A/P

CLK

T4

_3

AK

24

PB

59

AA

H2

4

PB

59

BA

H2

5

PB

69

C/L

RC

_D

LLT

_IN

_D

/LR

C_

DLL

T_

FB_

CA

G2

8

PB

69

D/L

RC

_D

LLC

_IN

_D

/LR

C_

DLL

C_

FB_

CA

G2

9

PB

64

BA

F25

PB

64

AA

G2

5

PB

69

B/L

RC

_P

LLC

_IN

_A

/LR

C_

PLL

C_

FB_

BA

H3

0

PB

67

AA

J28

PB

67

BA

H2

8

PB

67

C/V

RE

F1_

4A

E2

4

PB

67

DA

E2

5

PB

68

CA

E2

6

PB

68

DA

D2

5

PB

60

AA

K2

8

PB

63

AA

F24

PB

63

BA

G2

4

PB

60

BA

K2

9

PB

60

CA

E2

2

PB

61

AA

H2

6

PB

61

BA

H2

7

PB

68

A/L

RC

_D

LLT

_IN

_C

/LR

C_

DLL

T_

FB_

DA

J29

PB

68

B/L

RC

_D

LLC

_IN

_C

/LR

C_

DLL

C_

FB_

DA

H2

9

PB

69

A/L

RC

_P

LLT

_IN

_A

/LR

C_

PLL

T_

FB_

BA

J30

PB

65

AA

G2

6

PB

65

BA

F27

PB

55

AA

G2

1

PB

49

B/P

CLK

C4

_0

AJ2

1

SC-900FPBGA

RIGHT

Bank 2

BANK 3

U1

N SC2

5-9

00

fpB

GA

SC-900FPBGA

RIGHT

Bank 2

BANK 3

U1

N SC2

5-9

00

fpB

GA

PR

40

AR

27

PR

40

BT

27

PR

42

AV

28

PR

42

BW

28

PR

43

AT

30

PR

43

BU

30

PR

43

CV

26

PR

43

DW

26

PR

44

AV

29

PR

44

BW

29

PR

47

AV

30

PR

47

BW

30

PR

47

CY

27

PR

47

DW

27

PR

48

AY

30

PR

48

BA

A3

0

PR

49

AA

A2

5

PR

49

BA

B2

5

PR

51

AA

D3

0

PR

51

BA

E3

0

PR

52

AA

B2

8

PR

52

BA

C2

8

PR

53

AA

D2

9

PR

53

BA

E2

9

PR

55

AA

F30

PR

55

BA

G3

0

PR

55

C/L

RC

_D

LLT

_IN

_E

/LR

C_

DLL

T_

FB_

FA

B2

6

PR

55

D/L

RC

_D

LLC

_IN

_E

/LR

C_

DLL

C_

FB_

FA

C2

6

PR

56

AA

C2

7

PR

56

BA

D2

8

PR

57

C/L

RC

_P

LLT

_IN

_B

/LR

C_

PLL

T_

FB_

AA

D2

6

PR

57

D/L

RC

_P

LLC

_IN

_B

/LR

C_

PLL

C_

FB_

AA

C2

5

PR

25

D/D

IFFR

_2

M2

6

PR

42

D/D

IFFR

_3

V2

5

PR

48

CY

25

PR

42

CU

25

PR

29

C/P

CLK

T3

_1

R2

6

PR

29

D/P

CLK

C3

_1

R2

5

PR

16

A/U

RC

_P

LLT

_IN

_A

/UR

C_

PLL

T_

FB_

BD

28

PR

16

B/U

RC

_P

LLC

_IN

_A

/UR

C_

PLL

C_

FB_

BE

28

PR

17

A/U

RC

_D

LLT

_IN

_C

/UR

C_

DLL

T_

FB_

DD

29

PR

17

B/U

RC

_D

LLC

_IN

_C

/UR

C_

DLL

C_

FB_

DD

30

PR

18

A/U

RC

_D

LLT

_IN

_D

/UR

C_

DLL

T_

FB_

CG

28

PR

18

B/U

RC

_D

LLC

_IN

_D

/UR

C_

DLL

C_

FB_

CF2

8

PR

20

AG

27

PR

20

BH

27

PR

21

AL2

7

PR

21

BM

27

PR

22

AE

29

PR

22

BE

30

PR

25

AF2

9

PR

25

BG

29

PR

25

C/V

RE

F1_

2M

25

PR

26

A/P

CLK

T2

_1

H3

0

PR

26

B/P

CLK

C2

_1

J30

PR

27

A/P

CLK

T2

_0

K3

0

PR

27

B/P

CLK

C2

_0

L30

PR

16

CH

26

PR

16

DG

26

PR

18

CL2

5

PR

18

D/V

RE

F2_

2L2

6

PR

22

CJ2

8

PR

22

DH

28

PR

27

D/P

CLK

C2

_2

N2

7

PR

57

A/L

RC

_D

LLT

_IN

_F/

LRC

_D

LLT

_FB

_E

AF2

9

PR

57

B/L

RC

_D

LLC

_IN

_F/

LRC

_D

LLC

_FB

_E

AF2

8

PR

27

C/P

CLK

T2

_2

P2

6

PR

17

D/U

RC

_P

LLC

_IN

_B

/UR

C_

PLL

C_

FB_

AK

26

PR

17

C/U

RC

_P

LLT

_IN

_B

/UR

C_

PLL

T_

FB_

AK

25

PR

29

A/P

CLK

T3

_0

P2

8

PR

29

B/P

CLK

C3

_0

R2

8

PR

30

AN

28

PR

30

BN

29

PR

31

AP

29

PR

31

BR

29

PR

34

AT

28

PR

34

BU

28

PR

34

C/V

RE

F1_

3T

26

PR

35

AM

29

PR

35

BN

30

PR

36

AT

29

PR

36

BU

29

PR

38

AP

30

PR

38

BR

30

PR

39

AU

27

PR

39

BV

27

PR

30

C/P

CLK

T3

_3

P2

7

PR

31

C/P

CLK

T3

_2

L29

PR

31

D/P

CLK

C3

_2

M3

0

PR

34

DU

26

PR

35

CT

24

PR

51

D/V

RE

F2_

3A

B2

7

29

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 16. I2C RS232 Test

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

RS2

32

_R

XD

RS2

32

_T

XD

SDA

SCL

2_

5V

PT

EMP

SCL

SDA

LA_

12

LA_

15

LA_

14

LA_

11

LA_

13

LA_

7

LA_

5

LA_

10

LA_

9

LA_

1

LA_

6

LA_

4

LA_

2

LA_

8

LA_

0LA

_C

LK1

LA_

3

LA_

31

LA_

30

LA_

25

LA_

27

LA_

22

LA_

29

LA_

21

LA_

24

LA_

20

LA_

28

LA_

26

LA_

19

LA_

17

LA_

18

LA_

16

LA_

CLK

2

LA_

23

SWIT

CH

5SW

ITC

H6

SWIT

CH

8

SWIT

CH

3SW

ITC

H2

SWIT

CH

4

SWIT

CH

1

RED

1

BLU

E2

SWIT

CH

7

LED

1

LED

7

LED

4

LED

6

LED

8

LED

1

LED

2

LED

3

LED

4

LED

5

LED

6

LED

7

LED

8

LCD

_R

SLC

D5

LCD

_E

LCD

6LC

D_

DB

1LC

D7

LCD

_D

B3

LCD

8LC

D_

DB

5LC

D9

LCD

_D

B7

LCD

10

LCD

_R

/WLC

D0

LCD

_D

B0

LCD

1LC

D_

DB

2LC

D2

LCD

_D

B4

LCD

3LC

D_

DB

6LC

D4

AN

OD

E

LCD

[0..1

0]

LVD

S_P

RO

BEN

LVD

S_P

RO

BEP

LVD

S_IN

P

LVD

S_IN

N

LVD

S_O

UT

P

LVD

S_O

UT

N

LED

2Y

ELLO

W1

GR

EEN

1B

LUE1

RED

2

LED

3

LED

5

GR

EEN

2

YEL

LOW

2

3_

3V

3_

3V

2_

5V

12

_0

V

12

_0

V

1_

8V

12

_0

V

12

_0

V

12

_0

V1

2_

0V

12

_0

V

12

_0

V

12

_0

V

SDA

[2]

SCL

[2]

RS2

32

_R

XD

[2]

RS2

32

_T

XD

[2]

LA_

CLK

2[1

2]

LA_

[0..3

1]

[12

]

LA_

CLK

1[1

2]

SWIT

CH

[1..8

][1

2]

LED

[1..8

][1

2]

LCD

[0..1

0]

[2]

PT

EMP

[2]

LVD

S_P

RO

BEN

[12

]

LVD

S_IN

P[1

2]

LVD

S_IN

N[1

2]

LVD

S_O

UT

P[1

2]

LVD

S_O

UT

N[1

2]

LVD

S_P

RO

BEP

[12

]

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

I2C

,RS2

32

,Tes

t

C

13

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

I2C

,RS2

32

,Tes

t

C

13

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC-9

00

fpB

GA

x1

PC

I EX

PR

ESS

Car

d1

.0

I2C

,RS2

32

,Tes

t

C

13

14

Address-1001100

STAT

USLE

DS

LOGI

C AN

ALYZ

ER P

ROBE

SWIT

CHESEEPR

OM

TEMP

SEN

SE

I2C

RS23

2

Backlight

Adjustment

Contrast

Adjustment

LCD Connector

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED8

D15

D16

D17

D18

D19

D20

D21

D22

Layout LEDs along

Backpanel PCB edge

G

D1

7

LED

-SM

T1

20

6_

GR

EEN

G

D1

7

LED

-SM

T1

20

6_

GR

EEN

RN

2A

EXB

2H

V1

03

JV1

0K

RN

2A

EXB

2H

V1

03

JV1

0K

11

6

+C

32

5

10UF-16V_TANTBSMT

+C

32

5

10UF-16V_TANTBSMT

89

Y

D2

0

LED

-SM

T1

20

6_

YEL

LOW

Y

D2

0

LED

-SM

T1

20

6_

YEL

LOW

R273

0R-0603SMT

R273

0R-0603SMT

G

D2

1

LED

-SM

T1

20

6_

GR

EEN

G

D2

1

LED

-SM

T1

20

6_

GR

EEN

RN

2H

EXB

2H

V1

03

JV1

0K

RN

2H

EXB

2H

V1

03

JV1

0K

89

R2

57

68

0R

-06

03

SMT

R2

57

68

0R

-06

03

SMT

J38

Joh

nso

n 1

42

-07

11

-20

1J38

Joh

nso

n 1

42

-07

11

-20

11

2

C3

22

22

00

PF-

06

03

SMT

C3

22

22

00

PF-

06

03

SMT

J41

LCD

_C

on

ne

cto

r

J41

LCD

_C

on

ne

cto

r

AN

OD

E1

CA

TH

OD

E2

VS

S3

RS

6V

O5

VD

D4

R/W

7E

8

DB

09

DB

11

0

DB

21

1D

B3

12

DB

41

3D

B5

14

DB

61

5D

B7

16

SW4

TD

A0

8H

0SK

1

SW4

TD

A0

8H

0SK

1

11

22

33

44

55

66

77

88

99

10

10

11

11

12

12

13

13

14

14

15

15

16

16

R2

68

47

0R

-12

06

SMT

R2

68

47

0R

-12

06

SMT

R2

58

68

0R

-06

03

SMT

R2

58

68

0R

-06

03

SMT

R272

0R-0603SMT

R272

0R-0603SMT

RN

3A

EXB

2H

V4

72

JV4

.7K

RN

3A

EXB

2H

V4

72

JV4

.7K

116

R265

10K-0603SMT

R265

10K-0603SMT

R2

55

47

0R

-12

06

SMT

R2

55

47

0R

-12

06

SMT

J39

Joh

nso

n 1

42

-07

11

-20

1J39

Joh

nso

n 1

42

-07

11

-20

11

2

R2

59

68

0R

-06

03

SMT

R2

59

68

0R

-06

03

SMT

R2

71

47

0R

-12

06

SMT

R2

71

47

0R

-12

06

SMT

RN

2E

EXB

2H

V1

03

JV1

0K

RN

2E

EXB

2H

V1

03

JV1

0K

51

2

R2

62

20

0R

-08

05

SMT

R2

62

20

0R

-08

05

SMT

314

RN

2F

EXB

2H

V1

03

JV1

0K

RN

2F

EXB

2H

V1

03

JV1

0K

61

1

Q1

12

N2

22

2/S

OT

23

Q1

12

N2

22

2/S

OT

23

3

1

2

U2

6

MA

X6

69

2

U2

6

MA

X6

69

2

VC

C1

DX

P2

DX

N3

OV

ER

TN

4G

ND

5A

LER

TN

6S

MD

AT

7S

MC

LK8

R2

60

68

0R

-06

03

SMT

R2

60

68

0R

-06

03

SMT

J40

Joh

nso

n 1

42

-07

11

-20

1J40

Joh

nso

n 1

42

-07

11

-20

11

2

VR

22

0K

PO

T M

ura

ta P

V3

7W

20

3C

01

PV

37

W

VR

22

0K

PO

T M

ura

ta P

V3

7W

20

3C

01

PV

37

W

1 3

2

R2

74

10

0R

-06

03

SMT

R2

74

10

0R

-06

03

SMT

U2

5

MA

X3

23

2T

SSO

P1

6

U2

5

MA

X3

23

2T

SSO

P1

6

GN

D1

5V

CC

16

R1

IN1

3

R2

IN8

T2

IN1

0T

1IN

11

C1

+1

C1

-3

C2

+4

C2

-5

R1

OU

T1

2

R2

OU

T9

T1

OU

T1

4

T2

OU

T7

V+

2

V-

6

B

D1

8LE

D-S

MT

12

06

_B

LUE

B

D1

8LE

D-S

MT

12

06

_B

LUE

Q1

32

N2

22

2/S

OT

23

Q1

32

N2

22

2/S

OT

23

3

1

2

215

R2

61

68

0R

-06

03

SMT

R2

61

68

0R

-06

03

SMT

R2

69

10

0K

-06

03

SMT

R2

69

10

0K

-06

03

SMT

Q1

22

N2

22

2/S

OT

23

Q1

22

N2

22

2/S

OT

23

3

1

2

C3

18

10

0N

F-0

40

2SM

T0

40

2

C3

18

10

0N

F-0

40

2SM

T0

40

2

C3

17

10

0N

F-0

40

2SM

T0

40

2

C3

17

10

0N

F-0

40

2SM

T0

40

2

413

C3

23

10

0N

F-0

60

3SM

T

C3

23

10

0N

F-0

60

3SM

T

VR

12

0K

PO

T M

ura

ta P

V3

7W

10

1C

01

PV

37

W

VR

12

0K

PO

T M

ura

ta P

V3

7W

10

1C

01

PV

37

W

1 3

2

DP

2D

P2

1

2

3

RN

2G

EXB

2H

V1

03

JV1

0K

RN

2G

EXB

2H

V1

03

JV1

0K

71

0

R2

52

47

0R

-12

06

SMT

R2

52

47

0R

-12

06

SMT

+C

32

6

10UF-16V_TANTBSMT

+C

32

6

10UF-16V_TANTBSMT

R2

51

47

0R

-12

06

SMT

R2

51

47

0R

-12

06

SMT

U2

7

24

AA

10

25

-ISM

U2

7

24

AA

10

25

-ISM

GN

D4

VC

C8

SD

A5

SC

L6

A0

1

A1

2

A2

3W

P7

Q8

2N

22

22

/SO

T2

3Q

82

N2

22

2/S

OT

23

3

1

2

Y

D1

6

LED

-SM

T1

20

6_

YEL

LOW

Y

D1

6

LED

-SM

T1

20

6_

YEL

LOW

R2

67

47

0R

-12

06

SMT

R2

67

47

0R

-12

06

SMT

LA1

2_

76

70

04

LA1

2_

76

70

04

5V

1S

CL

2

GN

D3

SD

A4

CLK

15

CLK

6

77

88

99

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

R

D1

5

LED

-SM

T1

20

6_

RED

R

D1

5

LED

-SM

T1

20

6_

RED

C3

19

10

0N

F-0

40

2SM

T0

40

2

C3

19

10

0N

F-0

40

2SM

T0

40

2

R264

10K-0603SMT

R264

10K-0603SMT

R

D1

9

LED

-SM

T1

20

6_

RED

R

D1

9

LED

-SM

T1

20

6_

RED

R2

54

47

0R

-12

06

SMT

R2

54

47

0R

-12

06

SMT

Q9

2N

22

22

/SO

T2

3Q

92

N2

22

2/S

OT

23

3

1

2

611

R2

66

68

0R

-06

03

SMT

R2

66

68

0R

-06

03

SMT

C321

100NF-0603SMT

C321

100NF-0603SMT

R263

10K-0603SMT

R263

10K-0603SMT

R277

0R-0805SMT

R277

0R-0805SMTR

N2

C

EXB

2H

V1

03

JV1

0K

RN

2C

EXB

2H

V1

03

JV1

0K

31

4Q

10

2N

22

22

/SO

T2

3Q

10

2N

22

22

/SO

T2

3

3

1

2

J37

Joh

nso

n 1

42

-07

11

-20

1J37

Joh

nso

n 1

42

-07

11

-20

11

2

R2

53

68

0R

-06

03

SMT

R2

53

68

0R

-06

03

SMT

U2

8

LD1

08

5C

DT

50

-DP

AK

U2

8

LD1

08

5C

DT

50

-DP

AK

GND 1

VO

UT

2V

IN3

512

C3

27

10

0N

F-0

60

3SM

T0

60

3

C3

27

10

0N

F-0

60

3SM

T0

60

3

Q1

42

N2

22

2/S

OT

23

Q1

42

N2

22

2/S

OT

23

3

1

2

J36

HEA

DER

5X

2

J36

HEA

DER

5X

2

2 4 6 8 10

1 3 5 7 9

R276

OPEN-0805SMT

R276

OPEN-0805SMT

B

D2

2LE

D-S

MT

12

06

_B

LUE

B

D2

2LE

D-S

MT

12

06

_B

LUE

R2

56

68

0R

-06

03

SMT

R2

56

68

0R

-06

03

SMT

Q1

52

N2

22

2/S

OT

23

Q1

52

N2

22

2/S

OT

23

3

1

2

C3

20

10

0N

F-0

40

2SM

T0

40

2

C3

20

10

0N

F-0

40

2SM

T0

40

2

710

RN

2D

EXB

2H

V1

03

JV1

0K

RN

2D

EXB

2H

V1

03

JV1

0K

41

3

C3

24

10

0N

F-0

60

3SM

T

C3

24

10

0N

F-0

60

3SM

T

R2

70

47

0R

-12

06

SMT

R2

70

47

0R

-12

06

SMT

R2

75

10

0R

-06

03

SMT

R2

75

10

0R

-06

03

SMT

RN

2B

EXB

2H

V1

03

JV1

0K

RN

2B

EXB

2H

V1

03

JV1

0K

21

5

30

LatticeSC PCI Express x1Lattice Semiconductor Evaluation Board User’s Guide

Figure 17. VSS Decoupling5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VD

DO

B

2_

5V

VC

C_

CO

RE

2_

5V

VC

CIO

1

1_

8V

SC_

RLD

RA

M_

VT

T

SC_

QD

R_

VT

T

2_

5V

1_

2V

DD

AVD

DIB

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

VSS

/Dec

ou

plin

g

C

14

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

VSS

/Dec

ou

plin

g

C

14

14

Tit

le

ve

Rt

cej

o rP

ezi

S

te

eh

S:

eta

Do

f

SC P

CI E

XP

RES

S C

ard

1.0

VSS

/Dec

ou

plin

g

C

14

14

ALL CAPS PLACED UNDER BGA

VCCAUX

VCCIO1

3.3V or

2.5V

VCCIO2

VCCIO3

VCCIO4

VCCIO6

VCCIO7

VDDOB

VDDAX25

VDDRX

VDDTX

VDDP

VCC CORE

HSTL

VTT

VCCIO5

VCC12

VDDIB

TWO HOLES NEEDED FOR

FACEPLATE ATTACHMENT

PER PCIe Spec

C4

15

10

00

PF-

04

02

SMT

C4

15

10

00

PF-

04

02

SMT

C4

32

10

00

PF-

04

02

SMT

C4

32

10

00

PF-

04

02

SMT

C4

77

10

00

PF-

04

02

SMT

C4

77

10

00

PF-

04

02

SMT

C4

64

10

00

PF-

04

02

SMT

C4

64

10

00

PF-

04

02

SMT

C4

74

10

00

PF-

04

02

SMT

C4

74

10

00

PF-

04

02

SMT

C4

50

10

00

PF-

04

02

SMT

C4

50

10

00

PF-

04

02

SMT

C3

49

10

00

PF-

04

02

SMT

C3

49

10

00

PF-

04

02

SMT

C4

16

10

00

PF-

04

02

SMT

C4

16

10

00

PF-

04

02

SMT

C3

96

10

00

PF-

04

02

SMT

C3

96

10

00

PF-

04

02

SMT

C3

56

10

00

PF-

04

02

SMT

C3

56

10

00

PF-

04

02

SMT

C3

61

10

00

PF-

04

02

SMT

C3

61

10

00

PF-

04

02

SMT

C4

04

10

00

PF-

04

02

SMT

C4

04

10

00

PF-

04

02

SMT

C3

82

10

00

PF-

04

02

SMT

C3

82

10

00

PF-

04

02

SMT

C4

22

10

00

PF-

04

02

SMT

C4

22

10

00

PF-

04

02

SMT

C3

55

10

00

PF-

04

02

SMT

C3

55

10

00

PF-

04

02

SMT

C4

19

10

00

PF-

04

02

SMT

C4

19

10

00

PF-

04

02

SMT

C4

76

10

00

PF-

04

02

SMT

C4

76

10

00

PF-

04

02

SMT

C4

91

10

00

PF-

04

02

SMT

C4

91

10

00

PF-

04

02

SMT

C4

08

10

00

PF-

04

02

SMT

C4

08

10

00

PF-

04

02

SMT

C4

83

10

00

PF-

04

02

SMT

C4

83

10

00

PF-

04

02

SMT

C3

88

22

PF-

04

02

SMT

C3

88

22

PF-

04

02

SMT

C4

23

10

00

PF-

04

02

SMT

C4

23

10

00

PF-

04

02

SMT

C4

49

10

00

PF-

04

02

SMT

C4

49

10

00

PF-

04

02

SMT

C3

75

10

00

PF-

04

02

SMT

C3

75

10

00

PF-

04

02

SMT

C3

42

10

00

PF-

04

02

SMT

C3

42

10

00

PF-

04

02

SMT

C3

62

10

00

PF-

04

02

SMT

C3

62

10

00

PF-

04

02

SMT

C3

86

22

PF-

04

02

SMT

C3

86

22

PF-

04

02

SMT

C3

30

10

00

PF-

04

02

SMT

C3

30

10

00

PF-

04

02

SMT

C3

79

10

00

PF-

04

02

SMT

C3

79

10

00

PF-

04

02

SMT

C4

27

10

00

PF-

04

02

SMT

C4

27

10

00

PF-

04

02

SMT

C3

37

10

00

PF-

04

02

SMT

C3

37

10

00

PF-

04

02

SMT

C3

44

10

00

PF-

04

02

SMT

C3

44

10

00

PF-

04

02

SMT

C4

90

10

00

PF-

04

02

SMT

C4

90

10

00

PF-

04

02

SMT

C4

70

10

00

PF-

04

02

SMT

C4

70

10

00

PF-

04

02

SMT

C4

17

10

00

PF-

04

02

SMT

C4

17

10

00

PF-

04

02

SMT

C3

94

10

00

PF-

04

02

SMT

C3

94

10

00

PF-

04

02

SMT

C4

12

10

00

PF-

04

02

SMT

C4

12

10

00

PF-

04

02

SMT

C3

31

10

00

PF-

04

02

SMT

C3

31

10

00

PF-

04

02

SMT

C3

43

10

00

PF-

04

02

SMT

C3

43

10

00

PF-

04

02

SMT

C4

06

10

00

PF-

04

02

SMT

C4

06

10

00

PF-

04

02

SMT

C4

75

10

00

PF-

04

02

SMT

C4

75

10

00

PF-

04

02

SMT

C3

51

10

00

PF-

04

02

SMT

C3

51

10

00

PF-

04

02

SMT

C4

10

10

00

PF-

04

02

SMT

C4

10

10

00

PF-

04

02

SMT

C4

78

10

00

PF-

04

02

SMT

C4

78

10

00

PF-

04

02

SMT

C3

63

10

00

PF-

04

02

SMT

C3

63

10

00

PF-

04

02

SMT

C4

29

10

00

PF-

04

02

SMT

C4

29

10

00

PF-

04

02

SMT

C4

59

10

00

PF-

04

02

SMT

C4

59

10

00

PF-

04

02

SMT

C4

33

10

00

PF-

04

02

SMT

C4

33

10

00

PF-

04

02

SMT

C4

88

10

00

PF-

04

02

SMT

C4

88

10

00

PF-

04

02

SMT

C3

95

10

00

PF-

04

02

SMT

C3

95

10

00

PF-

04

02

SMT

C3

90

10

00

PF-

04

02

SMT

C3

90

10

00

PF-

04

02

SMT

C4

02

10

00

PF-

04

02

SMT

C4

02

10

00

PF-

04

02

SMT

C4

46

10

00

PF-

04

02

SMT

C4

46

10

00

PF-

04

02

SMT

C4

14

10

00

PF-

04

02

SMT

C4

14

10

00

PF-

04

02

SMT

C4

11

10

00

PF-

04

02

SMT

C4

11

10

00

PF-

04

02

SMT

C4

05

10

00

PF-

04

02

SMT

C4

05

10

00

PF-

04

02

SMT

C4

61

10

00

PF-

04

02

SMT

C4

61

10

00

PF-

04

02

SMT

C4

31

10

00

PF-

04

02

SMT

C4

31

10

00

PF-

04

02

SMT

C3

89

10

00

PF-

04

02

SMT

C3

89

10

00

PF-

04

02

SMT

C4

62

10

00

PF-

04

02

SMT

C4

62

10

00

PF-

04

02

SMT

C3

33

10

00

PF-

04

02

SMT

C3

33

10

00

PF-

04

02

SMT

C3

58

10

00

PF-

04

02

SMT

C3

58

10

00

PF-

04

02

SMT

C4

58

10

00

PF-

04

02

SMT

C4

58

10

00

PF-

04

02

SMT

C4

01

10

00

PF-

04

02

SMT

C4

01

10

00

PF-

04

02

SMT

C4

54

10

00

PF-

04

02

SMT

C4

54

10

00

PF-

04

02

SMT

C4

30

10

00

PF-

04

02

SMT

C4

30

10

00

PF-

04

02

SMT

C3

57

10

00

PF-

04

02

SMT

C3

57

10

00

PF-

04

02

SMT

C4

80

10

00

PF-

04

02

SMT

C4

80

10

00

PF-

04

02

SMT

C3

38

10

00

PF-

04

02

SMT

C3

38

10

00

PF-

04

02

SMT

C3

85

10

00

PF-

04

02

SMT

C3

85

10

00

PF-

04

02

SMT

C4

24

10

00

PF-

04

02

SMT

C4

24

10

00

PF-

04

02

SMT

C4

20

10

00

PF-

04

02

SMT

C4

20

10

00

PF-

04

02

SMT

C4

37

10

00

PF-

04

02

SMT

C4

37

10

00

PF-

04

02

SMT

C4

63

10

00

PF-

04

02

SMT

C4

63

10

00

PF-

04

02

SMT

C3

84

10

00

PF-

04

02

SMT

C3

84

10

00

PF-

04

02

SMT

C4

57

10

00

PF-

04

02

SMT

C4

57

10

00

PF-

04

02

SMT

C4

94

10

00

PF-

04

02

SMT

C4

94

10

00

PF-

04

02

SMT

C4

72

10

00

PF-

04

02

SMT

C4

72

10

00

PF-

04

02

SMT

C3

36

10

00

PF-

04

02

SMT

C3

36

10

00

PF-

04

02

SMT

C4

98

10

00

PF-

04

02

SMT

C4

98

10

00

PF-

04

02

SMT

MH

3

M H

OLE

2

MH

3

M H

OLE

2

C3

87

10

00

PF-

04

02

SMT

C3

87

10

00

PF-

04

02

SMT

C3

34

10

00

PF-

04

02

SMT

C3

34

10

00

PF-

04

02

SMT

C4

93

10

00

PF-

04

02

SMT

C4

93

10

00

PF-

04

02

SMT

C3

65

10

00

PF-

04

02

SMT

C3

65

10

00

PF-

04

02

SMT

C4

34

10

00

PF-

04

02

SMT

C4

34

10

00

PF-

04

02

SMT

C4

65

10

00

PF-

04

02

SMT

C4

65

10

00

PF-

04

02

SMT

C3

74

10

00

PF-

04

02

SMT

C3

74

10

00

PF-

04

02

SMT

C3

66

10

00

PF-

04

02

SMT

C3

66

10

00

PF-

04

02

SMT

MH

4

M H

OLE

2

MH

4

M H

OLE

2

C4

09

10

00

PF-

04

02

SMT

C4

09

10

00

PF-

04

02

SMT

C4

87

10

00

PF-

04

02

SMT

C4

87

10

00

PF-

04

02

SMT

C3

83

10

00

PF-

04

02

SMT

C3

83

10

00

PF-

04

02

SMT

C4

69

10

00

PF-

04

02

SMT

C4

69

10

00

PF-

04

02

SMT

C3

99

10

00

PF-

04

02

SMT

C3

99

10

00

PF-

04

02

SMT

C3

80

10

00

PF-

04

02

SMT

C3

80

10

00

PF-

04

02

SMT

C3

69

10

00

PF-

04

02

SMT

C3

69

10

00

PF-

04

02

SMT

C3

41

10

00

PF-

04

02

SMT

C3

41

10

00

PF-

04

02

SMT

C4

86

10

00

PF-

04

02

SMT

C4

86

10

00

PF-

04

02

SMT

C3

81

10

00

PF-

04

02

SMT

C3

81

10

00

PF-

04

02

SMT

C4

56

10

00

PF-

04

02

SMT

C4

56

10

00

PF-

04

02

SMT

C4

92

10

00

PF-

04

02

SMT

C4

92

10

00

PF-

04

02

SMT

C3

52

10

00

PF-

04

02

SMT

C3

52

10

00

PF-

04

02

SMT

MH

5

M H

OLE

2

MH

5

M H

OLE

2

C3

64

10

00

PF-

04

02

SMT

C3

64

10

00

PF-

04

02

SMT

C3

59

10

00

PF-

04

02

SMT

C3

59

10

00

PF-

04

02

SMT

C3

73

10

00

PF-

04

02

SMT

C3

73

10

00

PF-

04

02

SMT

C4

13

10

00

PF-

04

02

SMT

C4

13

10

00

PF-

04

02

SMT

C4

81

10

00

PF-

04

02

SMT

C4

81

10

00

PF-

04

02

SMT

C3

97

10

00

PF-

04

02

SMT

C3

97

10

00

PF-

04

02

SMT

C4

82

10

00

PF-

04

02

SMT

C4

82

10

00

PF-

04

02

SMT

C4

03

10

00

PF-

04

02

SMT

C4

03

10

00

PF-

04

02

SMT

C4

95

10

00

PF-

04

02

SMT

C4

95

10

00

PF-

04

02

SMT

C3

53

10

00

PF-

04

02

SMT

C3

53

10

00

PF-

04

02

SMT

C3

68

10

00

PF-

04

02

SMT

C3

68

10

00

PF-

04

02

SMT

C4

55

10

00

PF-

04

02

SMT

C4

55

10

00

PF-

04

02

SMT

C3

47

10

00

PF-

04

02

SMT

C3

47

10

00

PF-

04

02

SMT

C4

68

10

00

PF-

04

02

SMT

C4

68

10

00

PF-

04

02

SMT

C4

89

10

00

PF-

04

02

SMT

C4

89

10

00

PF-

04

02

SMT

C4

73

10

00

PF-

04

02

SMT

C4

73

10

00

PF-

04

02

SMT

C3

67

10

00

PF-

04

02

SMT

C3

67

10

00

PF-

04

02

SMT

C4

53

10

00

PF-

04

02

SMT

C4

53

10

00

PF-

04

02

SMT

C3

77

10

00

PF-

04

02

SMT

C3

77

10

00

PF-

04

02

SMT

C3

54

10

00

PF-

04

02

SMT

C3

54

10

00

PF-

04

02

SMT

C3

46

10

00

PF-

04

02

SMT

C3

46

10

00

PF-

04

02

SMT

C3

93

10

00

PF-

04

02

SMT

C3

93

10

00

PF-

04

02

SMT

C4

79

10

00

PF-

04

02

SMT

C4

79

10

00

PF-

04

02

SMT

C4

35

10

00

PF-

04

02

SMT

C4

35

10

00

PF-

04

02

SMT

C3

35

10

00

PF-

04

02

SMT

C3

35

10

00

PF-

04

02

SMT

C3

78

10

00

PF-

04

02

SMT

C3

78

10

00

PF-

04

02

SMT

C3

98

10

00

PF-

04

02

SMT

C3

98

10

00

PF-

04

02

SMT

C3

28

10

00

PF-

04

02

SMT

C3

28

10

00

PF-

04

02

SMT

C3

76

10

00

PF-

04

02

SMT

C3

76

10

00

PF-

04

02

SMT

C3

45

10

00

PF-

04

02

SMT

C3

45

10

00

PF-

04

02

SMT

C4

66

10

00

PF-

04

02

SMT

C4

66

10

00

PF-

04

02

SMT

C4

07

10

00

PF-

04

02

SMT

C4

07

10

00

PF-

04

02

SMT

C4

36

10

00

PF-

04

02

SMT

C4

36

10

00

PF-

04

02

SMT

VSS

SC-900FPBGA

U1

F

SC2

5-9

00

fpB

GA

VSS

SC-900FPBGA

U1

F

SC2

5-9

00

fpB

GA

GNDAJ10

GNDAJ27

GNDAK26

GNDAJ22

GNDAF20

GNDAJ25

GNDAF23

GNDAF22

GNDAE27

GNDAA27

GNDAB29

GNDY29

GNDY26

GNDAC30

GNDF27

GNDE27

GNDF30

GNDP25

GNDH29

GNDK29

GNDR24

GNDM28

GNDJ27

GNDN26

GNDE20

GNDE21

GNDF21

GNDF23

GNDD21

GNDD20

GNDG23

GNDE18

GNDC20

GNDC11

GNDA12

GNDF8

GNDE11

GNDG8

GNDD11

GNDD10

GNDH7

GNDF10

GNDE10

GN

DY

19

GN

DY

20

GN

DN

15

GN

DN

16

GN

DN

17

GN

DN

18

GN

DN

19

GN

DN

20

GN

DP

11

GN

DP

12

GN

DP

13

GN

DP

14

GN

DP

15

GN

DP

16

GN

DP

17

GN

DP

18

GN

DP

19

GN

DP

20

GN

DR

10

GN

DR

11

GN

DR

12

GN

DR

13

GN

DR

14

GN

DR

15

GN

DR

16

GN

DR

17

GN

DR

18

GN

DR

19

GN

DR

20

GN

DR

21

GN

DT

10

GN

DT

11

GN

DT

12

GN

DT

13

GN

DT

14

GN

DT

15

GN

DT

16

GN

DT

17

GN

DT

18

GN

DT

19

GN

DT

20

GN

DT

21

GN

DU

11

GN

DU

12

GN

DU

13

GN

DU

14

GN

DU

15

GN

DU

16

GN

DU

17

GN

DU

18

GN

DU

19

GN

DU

20

GN

DV

11

GN

DV

12

GN

DV

13

GN

DV

14

GN

DV

15

GN

DV

16

GN

DV

17

GN

DV

18

GN

DV

19

GN

DV

20

GN

DW

11

GN

DW

12

GN

DW

13

GN

DW

14

GN

DW

15

GN

DW

16

GN

DW

17

GN

DW

18

GN

DW

19

GN

DW

20

GN

DY

11

GN

DY

12

GN

DY

13

GN

DY

14

GN

DY

15

GN

DY

16

GN

DY

17

GN

DY

18

GN

DM

19

GN

DM

20

GN

DA

1

GN

DA

30

GND AA15

GND AA16

GND AK1

GND AK30

GND K15

GND K16

GND L11

GND L12

GND L13

GND L14

GND L15

GND L16

GND L17

GND L18

GND L19

GND L20

GND M11

GND M12

GND M13

GND M14

GND M15

GND M16

GND M17

GND M18

GND N12

GND N13

GND N11

GND N14

GNDAB4

GNDAG9

GNDK2

GNDAE1

GNDL4

GNDH1

GNDAG12

GNDAA5

GNDAE8

GNDAA3

GNDAG6

GNDG4

GNDAH5

GNDY4

GNDH3

GNDAE6

GNDN5

GNDAF11

GNDM3

GNDM2

GNDP6

GNDAC2

C4

52

10

00

PF-

04

02

SMT

C4

52

10

00

PF-

04

02

SMT

C4

97

10

00

PF-

04

02

SMT

C4

97

10

00

PF-

04

02

SMT

C3

91

10

00

PF-

04

02

SMT

C3

91

10

00

PF-

04

02

SMT

C4

67

10

00

PF-

04

02

SMT

C4

67

10

00

PF-

04

02

SMT

C4

00

10

00

PF-

04

02

SMT

C4

00

10

00

PF-

04

02

SMT

C3

29

10

00

PF-

04

02

SMT

C3

29

10

00

PF-

04

02

SMT

C4

28

10

00

PF-

04

02

SMT

C4

28

10

00

PF-

04

02

SMT

C3

71

10

00

PF-

04

02

SMT

C3

71

10

00

PF-

04

02

SMT

C4

60

10

00

PF-

04

02

SMT

C4

60

10

00

PF-

04

02

SMT

C3

50

10

00

PF-

04

02

SMT

C3

50

10

00

PF-

04

02

SMT

C4

26

10

00

PF-

04

02

SMT

C4

26

10

00

PF-

04

02

SMT

C4

85

10

00

PF-

04

02

SMT

C4

85

10

00

PF-

04

02

SMT

C3

39

10

00

PF-

04

02

SMT

C3

39

10

00

PF-

04

02

SMT

C4

71

10

00

PF-

04

02

SMT

C4

71

10

00

PF-

04

02

SMT

C4

25

10

00

PF-

04

02

SMT

C4

25

10

00

PF-

04

02

SMT

C4

84

10

00

PF-

04

02

SMT

C4

84

10

00

PF-

04

02

SMT

C4

47

10

00

PF-

04

02

SMT

C4

47

10

00

PF-

04

02

SMT

C3

40

10

00

PF-

04

02

SMT

C3

40

10

00

PF-

04

02

SMT

C4

99

10

00

PF-

04

02

SMT

C4

99

10

00

PF-

04

02

SMT

C4

18

10

00

PF-

04

02

SMT

C4

18

10

00

PF-

04

02

SMT

C3

92

10

00

PF-

04

02

SMT

C3

92

10

00

PF-

04

02

SMT

C4

48

10

00

PF-

04

02

SMT

C4

48

10

00

PF-

04

02

SMT

C3

32

10

00

PF-

04

02

SMT

C3

32

10

00

PF-

04

02

SMT

C3

70

10

00

PF-

04

02

SMT

C3

70

10

00

PF-

04

02

SMT

C4

21

10

00

PF-

04

02

SMT

C4

21

10

00

PF-

04

02

SMT

C4

51

10

00

PF-

04

02

SMT

C4

51

10

00

PF-

04

02

SMT

C4

96

10

00

PF-

04

02

SMT

C4

96

10

00

PF-

04

02

SMT

C3

48

10

00

PF-

04

02

SMT

C3

48

10

00

PF-

04

02

SMT

C3

60

10

00

PF-

04

02

SMT

C3

60

10

00

PF-

04

02

SMT

C3

72

10

00

PF-

04

02

SMT

C3

72

10

00

PF-

04

02

SMT