Introduction to Sequential Logic Design

Flip-flops

PrevLatchesS-RS-bar-R-barS-R with enable signalD

FF vs. LatchLatches and flip-flops (FFs) are the basic building blocks of sequential circuits.

latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs, independent of a clocking signal.flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.

Edge triggered D Flip-FlopA D FF combines a pair of D latches. Master/slaveD FFPositive-edge-triggered D FFNegative-edge-triggered D FFEdge-Triggered D FF with EnableScan FF

Positive-Edge-triggered D flip-flop

Positive-Edge-triggered D flip-flop

Edge-triggered D flip-flop behavior

Edge-triggered D flip-flop behavior

Edge-triggered D flip-flop behavior

D flip-flop timing parametersPropagation delay (from CLK)Setup time (D before CLK)Hold time (D after CLK)

D FF with asynchronous inputsForce the D FF to a particular state independent of the CLK and D inputs. PR (Preset) and CLR (Clear)

Negative-edge triggered D FFSimply inverts the clock input. Active low.

Negative-edge triggered D FFSimply inverts the clock input. Active low.

J-K flip-flops

T (toggle) flip-flopsA T FF changes state on every tick of the clock. (be toggled on every tick)Q has precisely half the frequency of the T.Important for countersPositive-edge-triggered T FF

How to build T FF using J-K FF and D FF?

T (toggle) flip-flops with enableHow to build a T FF with enable using? D FF J-K FF

T (toggle) flip-flops with enable

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