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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces
Lecture #26Case Studies :
XAUI, PCI-ExpressJared Zerbe4/22/04
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AgendaProject phase-II discussionCase studies
XAUIPCI Express
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Project Phase-IIAssignments clear?Impact from circuits yet?Significant issues?
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XAUIXAUI = 10G Attachment Unit InterfaceOrigins in 10G Ethernet 802.3ae
Extended into backplane spaceDefines device characteristics
BUTAlso defines loss characteristics & system parametersAlso budgets system voltage & timingA lot of the terminology used has become common ; a mixture from different backgrounds, i.e. SONET, etc.
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Where XAUI Fits
Clearly an extension, but one of the first good definitions of a serial link architecture & requirements
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XAUI Architecture – Basic QualitiesBundle of 4 pairs @ 2.5Gb/s/pair (delivered) = 10Gb/s8b10b coding => raw line rates are 3.125Gb/sAC coupled for interoperability (at receiver)100Ω differentialCan practically achieve eyes with 1 or 2 tap TXeqPlesiochronous between quads; +/- 100ppm in systemLane deskewing handled at an upper layer (XGXS)BER is defined as < 10-12
Spec includes methods for testing compliance (!)
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XAUI Driver Characteristics
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XAUI Driver Template
Specified at both Tx & Rx ends (implied channel)Accounts for both attenuation and uncompensated ISI
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XAUI Receiver Characteristics
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XAUI Jitter ToleranceJitter seperated into 3 pieces
DJ : Deterministic jitter (includes residual ISI, duty-cycle error, etc.)RJ : Random jitter – uncorrelated with any sourceSJ : Sinusoidal jitter
Doesn’t necessarily exist in a real system, but used in tolerance as a way of making sure system can track low frequency wander, Vdd effects
XAUI jitter tolerence specsReceiver must be able to tolerate this much jitterDJ : 0.37UIp-p
DJ+RJ : 0.55UIp-p
SJ : additional SJ (on top of DJ+RJ) to limit of mask…
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XAUI Jitter Tolerance : SJ Mask
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XAUI Example System BudgetingSupposed to represent a system with 50cm of FR4
Sound familiar?
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Example XAUI Implementation
Wadhwa, CICC 2003, 0.13µ CMOS
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AgendaProject phase-II discussionCase studies
XAUIPCI Express
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History : PCI Bus Factoids
PCI = Peripheral Component Interconnect Original PCI Bus standardized in 1992Characteristics
32-bits @ 33 MHz (BW = 133MB/sec)Single-ended, Synch., Multi-drop parallel bus Requires clock/data trace matching
Evolved to several variations: PCI-X, CompactPCI, etc.
I/O
Data
Clock
Data
I/O I/O
Data
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Synchronous Busses Need Trace Matching
At high speed, timing skews are a major issue
Serpentines on PCB needed to address this
May be OK upto 1 Gbps
Serpentines to Match lengths
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Bus Evolution
Common clock Embedded clockSingle-ended signals Differential signalsParallel SerialMulti-drop Point-to-point
PCI-Express2.5 Gb/s/lane
2005+
10 GHz
1978
8 MHz
133 MHz
133 MHz
800 MHz
500 MHz
2.5 GHz
2.5 GHz68xxx
MPC 603/740/7400Pentium/PII/PIII
PCIPC100/PC133
Infiniband2.5 Gb/s
2000
1998 2003
PCI-X133
DDR 333/400
Pentium 4533
Athlon533
2000 2005
2001RapidIO
Pos Phy 4Hypertransport
Courtesy Agilent
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PCI Express: Based on Serial LinksPCI Express: Based on Serial Links
Serial Link(SerDes)
Characteristics1x, 2x,…, 32x @2.5 Gbps(BW = up to 8 GB/sec)Point-to-point differential signalingNo separate clock signal (embedded clks)Link-end RefClks can be independentNo trace matching required between lanes
Data +Clock
Data
RefClock_1
DataI/O I/O
RefClock_2
BenefitsBandwidth scalabilityHigher line speeds
Lower costHigher speed &manufacturable
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PCI Express : Where it fits
USB 2.0USB 2.0
PCIPCI
MemoryBridge
CPU
Graphics Memory
HDD
SIO
PCI Express
PCIExpress
Serial ATA
Add-ins
Add-ins
Add-ins
I/OBridge
Bandwidth Scalability Cheaper connectors & smaller board areasNext gen PCI Express* expected to support 5-6.25Gbps
Legacy support w/ PCISoftware/driver level
Advanced capabilitiesEase-of-use (plug&play)Power managementFeatures for communications systems
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PCI Express – Basic QualitiesSimilar
8b10b coding => raw line is 2.5Gb/s; delivered is 2GAC coupled for interoperability (at transmitter)100Ω differential
DifferentUnit is a single TX/RX differential pair @ 2.5Gb/s/pair
Support for x1, x2, x4, x8 in specificationsPlesiochronous at +/- 300ppmSupport for spread-spectrum-clockingGen-II plan for performance scaling to 6GBecon detect, power states to allow lower off currentBuilt-in requirement for de-emphasis (TxEq)Lane deskewing handled at an upper layer (XGXS)
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The Packet Paradigm Pushing Into PCsTrigger events routinely require sequencing across
multiple events and bussesD
evic
eI
DeviceII
Switch
Switch
Courtesy Agilent
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“Read” & “Write” Cycles replaced by Packets
Frame Sequence#
Header Data CRC FrameDev
ice
A Device B
Frame Sequence#DataCRC Frame
Request
Requester Header FormatFor 64-bit addressing of memory
Header
Completion
Completion Header Format
Header
Courtesy Agilent
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PCI Express : Transmitter Specification
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PCI Express : Transmitter Equalization
Simple single-tap equalizer defined as de-emphasis for subsequent identical bits (CIDs)
Defined as driven at 3.5dB below first bit
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PCI Express : Everything else about the TX too!
Many other specs involving idle, tRF, etc.A more complete spec needed for true multi-vendor compatibility
But basic performance requirements not all that different from XAUI
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TX Compliance
Not that new… but TxEq is well definedNote also : bits no longer have flat spots!
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PCI Express : Receiver Specification
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RX Compliance
Input is now 175mV (p-p diff) x 0.4UITX Transition bit is 800mV x 0.7UITX De-emphasized bit is 566mV x 0.7UIQ : What does this mean viz. loss at Nyquist?
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Reg
iste
r
PLL
ParallelInterface Serializer
Reg
iste
r
SerialData
Clock RecoveryDeserializer
Additional Features for PCI Express PHY
New Features required for Hot-Plug capability, Power MgmtTransmitter Tri-state (‘Electrical Idle’) CapabilityReceiver termination is to ground instead of Vdd‘Rx Detect’ feature before transmission
Beacon Generate/Detect Feature for Remote System WakeupExhaustive Power Management features
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To support Hot plug
A special circuit inside Tx periodically checks for the presenceof Rx loadInternal Rx-Detect output
50 ΩVTT
Zo = 50 Ω
Zo = 50 Ω
RxTx
GND
Tx-Idle & Receiver Detect Feature
RxDet
Tx TristateEnable
Rx Present
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To support Power Management
Beacon => “Wake Up” call while in powerdownSpecial circuit in Tx for Beacon Transmit & in Rx for Beacon DetectOperate from VDDAUX supply
50 ΩVTT
Zo = 50 Ω
Zo = 50 Ω
RxTx
GND
Beacon Detect
BeaconDet
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Example PMA Block DiagramSerializerTransmit Data
System Clock
Transmit(2.5 Gbps)
ParallelInterface
DeserializerReceive(2.5 Gbps)
Clock Rec’vry
Receive Clock(Parallel data rate)
Receive Data
PLLReference Clock
(Parallel data rate)
Clock÷ N
SerialDataParallel
Data
Allows future BW headroom e.g. Next Gen PCI Exp link at 5 GbpsPMA has special features to support Hot-Plug, Power Mgmt. making it suitable for Mainstream applications
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Elastic Buffer (RefClk +300 ppm)
System 1 System 2
Clk1
(100 MHz + 30KHz)
Clk 2
(100MHz)
@ 2.50075 Gb/s
@ 2.5Gb/s
Recovered Clk
= RefClk + 75 KHz
Elastic Buffer
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Elastic Buffer (RefClk -300 ppm)
System 1 System 2
Clk1
(100 MHz - 30KHz)
Clk 2
(100MHz)
Recovered Clk
= RefClk - 30 KHz
Elastic Buffer
@ 2.49925 Gb/s
@ 2.5Gb/s
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Elastic Buffer Mech. (Skip Sequence)
CSSS D[n] D[n-1] D[n-2] D[n-3]D[3] D[2] D[1] D[0]
Data PacketData Packet 1 Skip Sequence
CSSS D[n] D[n-1] D[n-2] D[n-3]D[2] D[1] D[0]
CSS D[n] D[n-1] D[n-2] D[n-3]D[4] D[3] D[2] D[1] D[0]
S
Add Skip (Local RefClk > Remote RefClk)
Delete Skip (Local RefClk < Remote RefClk
Data Flow
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Lane de-skewing FunctionDone in MAC layer – to accommodate variable lane-width feature of PCI Express (e.g. x1, x4, etc)
PCSLane 1
MA
C
D[3] D[2] D[1] D[0]
D[3] D[2] D[1] D[0]
D[2] D[1] D[0]
D[2] D[1] D[0]
Rd Ptr 1
Rd Ptr 2
Rd Ptr 3
Rd Ptr 3
PCSLane 2
PCSLane 3
PCSLane 4
During Init. Rd Ptrs. In MAC for each lane are set appropriately so that D[0] bytes for all lanes are read simultaneously
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MAC
SERDES Elastic
Buffer8B/10B
Decoder
Framer
8B/10BEncoder K/D
K/D
Transmit
Receive
RxClk
SysClk
FmOffset
RxData
TxData
SysClk
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Rx+
Rx-
Tx+
Tx-
Command/Status Control
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PMA PCS
Putting it all together
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Measurement to PCI Express MaskMeasurement to PCI Express Mask
Worst Non-Transition Signal Eye at Tx Worst Transition Signal Eye at Tx
Separate tests used as a way of testing EQSeparate tests used as a way of testing EQHow will we test more complicated EQ?How will we test more complicated EQ?
This was pretty darn simpleThis was pretty darn simple
