of 19
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Lecture 3:
CMOS
Transistor
Theory
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 2
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics Gate and Diffusion Capacitance
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 3
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance
I = C (DV/Dt) -> Dt = (C/I) DV
Capacitance and current determine speed
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 4
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
MOS Capacitor
Gate and body form MOScapacitor
Operating modes
Accumulation
Depletion Inversion
(b)
+-
0 < Vg < Vt
depletion region
(c)
+-
Vg > Vt
depletion region
inversion region
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 5
Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs Vgd = Vg Vd Vds = Vd Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+-
+
-
+
-
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 6
nMOS Cutoff
No channel
Ids 0
+-
Vgs
= 0
n+ n+
+-
Vgd
p-type body
b
g
s d
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 7
nMOS Linear
Channel forms
Current flows from d to s
e- from s to d
Ids increases with Vds Similar to linear resistor
+-
Vgs
> Vt
n+ n+
+-
Vgd
= Vgs
+
-
Vgs
> Vt
n+ n+
+
-
Vgs
> Vgd
> Vt
Vds = 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 8
nMOS Saturation
Channel pinches off
Ids independent of Vds We say current saturates
Similar to current source
+-
Vgs
> Vt
n+ n+
+-
Vgd
< Vt
Vds > Vgs-Vt
p-type body
b
g
s d Ids
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 9
I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?
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CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 10
Channel Charge
MOS structure looks like parallel plate capacitorwhile operating in inversions
Gate oxide channel
Qchannel
= CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9)
polysilicon
gate
Cox = eox / tox
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 11
Carrier velocity
Charge is carried by e-
Electrons are propelled by the lateral electric fieldbetween source and drain
E = Vds/L
Carrier velocity vproportional to lateral E-field
v= mE m called mobility
Time for carrier to cross channel:
t= L / v
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 12
nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time teach carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QIt
W VC V V V
L
VV V V
m
ox=
WC
L m
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 13
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt Now drain voltage no longer increases current
2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 14
nMOS I-V Summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
Shockley1st order transistor models
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 15
Example
We will be using a 0.6 mm process for your project From AMI Semiconductor
tox = 100
m = 350 cm2
/V*s Vt = 0.7 V
Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2 l
14
2
8
3.9 8.85 10350 120 A/V
100 10ox
W W WC
L L L m
0 1 2 3 4 50
0.5
1
1.5
2
2.5
Vds
Ids
(mA)
Vgs
= 5
Vgs
= 4
Vgs
= 3
Vgs
= 2
Vgs
= 1
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 16
pMOS I-V
All dopings and voltages are inverted for pMOS Source is the more positive terminal
Mobility mp is determined by holes
Typically 2-3x lower than that of electrons mn 120 cm2/Vs in AMI 0.6 mm process
Thus pMOS must be wider to
provide same current
In this class, assumemn / mp = 2
-5 -4 -3 -2 -1 0-0.8
-0.6
-0.4
-0.2
0
Ids(m
A)
Vgs
= -5
Vgs
= -4
Vgs
= -3
Vgs
= -2
Vgs
= -1
Vds
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 17
Capacitance
Any two conductors separated by an insulator havecapacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 18
Gate Capacitance
Approximate channel as connected to source Cgs = eoxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/mm
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, eox
= 3.9e0)
polysilicon
gate
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CMOS VLSI DesignCMOS VLSI Design4th Ed.
3: CMOS Transistor Theory 19
Diffusion Capacitance
Csb, Cdb Undesirable, calledparasiticcapacitance
Capacitance depends on area and perimeter
Use small diffusion nodes Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process
