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Lecture 1 Computer Abstractions and Technology
Lecture 1
Computer Abstractions and Technology
Computers are pervasive Computers in automobiles Smart phones Internet
Search Engines Appliances
Microwave oven Refrigerator …
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Your car has many computers 50~100 computers inside each car
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Smart phones are all computers 2 billion smart phone users in 2016
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The Processor Market
Internet is a network of computers Google’s huge data centers for searching
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#1 supercomputer as of June 2017 Sunway TaihuLight
> 10M cores > 15 MW
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Many computers are hidden
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Classes of Computers Desktop computers
General purpose, variety of software Server computers
High capacity, performance, reliability Range from small servers to building sized
Embedded computers Hidden as components of systems Stringent power/performance/cost constraints
Personal Mobile Devices Clusters/warehouse scale computers
Supercomputers
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The Computer Revolution Progress in computer technology
Underpinned by Moore’s Law The number of transistors on integrated circuits
doubles approximately every two years
§1.1 Introduction
Moore’s Law
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Technology Trends Electronics
technology continues to evolve Increased capacity
and performance Reduced cost
Year Technology Relative performance/cost1951 Vacuum tube 11965 Transistor 351975 Integrated circuit (IC) 9001995 Very large scale IC (VLSI) 2,400,0002013 Ultra large scale IC 250,000,000,000
DRAM capacity
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What You Will Learn from This Course
Programs are translated into the machine language How the hardware executes them
The hardware/software interface What determines program performance
And how it can be improved How hardware designers improve
performance
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What Affect Performance? Processor and memory system
Determine how fast instructions are executed I/O system (including OS)
Determines how fast I/O operations are executed Algorithm and data structure
Determines number of operations executed Programming language, compiler, architecture
Determine number of machine instructions executed per operation
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Below Your Program Application software
Written in high-level language System software
Compiler: translates HLL code to machine code
Operating System: service code Handling input/output Managing memory and storage Scheduling tasks & sharing resources
Hardware Processor, memory, I/O controllers
§1.3 Below
Your Program
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Levels of Program Code High-level language
Level of abstraction closer to problem domain
Provides for productivity and portability
Assembly language Textual representation of
instructions Hardware representation
Binary digits (bits) Encoded instructions and
data
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Components of a Computer Same components for
all kinds of computer (e.g., desktop, server, embedded) Input Output Memory Control Datapath
§1.4 Under the C
overs
The BIG Picture
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Anatomy of a Computer
Output device
Input device
Input device
Network cable
Typical Input/Output User-interface devices
Display, keyboard, mouse Storage devices
Hard disk, CD/DVD, flash Network adapters
For communicating with other computers
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Networks Communication and resource sharing Local area network (LAN): Ethernet
Within a building Wide area network (WAN): the Internet Wireless network: WiFi, Bluetooth
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Opening the Box
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Place for Data Volatile main memory
Loses instructions and data when power off
Non-volatile secondary memory Magnetic disk (hard disk drive) Solid-state drive (flash memory) Optical disk (CDROM, DVD)
The Processor
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Inside the Processor (CPU) Datapath: performs operations on data
A collection of functional units that perform data processing operations
Control: sequences datapath, memory, ... Different data items go through different
components Cache memory
Small fast SRAM memory for immediate access to data
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Inside the Processor AMD Barcelona: 4 processing cores
Datapath: assembly line
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Datapath in processor
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Memory hierarchy Pyramid
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iPhone-external Front Back Side
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iPhone-external Bottom
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iPhone-internal
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Memory module is under the processor using “package-on-package”
iPhone-internal
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Defining Performance Which airplane has the best performance?
0 100 200 300 400 500
DouglasDC-8-50
BAC/SudConcorde
Boeing 747
Boeing 777
Passenger Capacity
0 2000 4000 6000 8000 10000
Douglas DC-8-50
BAC/SudConcorde
Boeing 747
Boeing 777
Cruising Range (miles)
0 500 1000 1500
DouglasDC-8-50
BAC/SudConcorde
Boeing 747
Boeing 777
Cruising Speed (mph)
0 100000 200000 300000 400000
Douglas DC-8-50
BAC/SudConcorde
Boeing 747
Boeing 777
Passengers x mph
§1.6 Perform
ance
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Relative Performance Define Performance = 1/Execution Time “X is n times faster than Y”
n XY
YX
time Executiontime ExecutionePerformancePerformanc
Example: time taken to run a program 10s on A, 15s on B Execution TimeB / Execution TimeA
= 15s / 10s = 1.5 So A is 1.5 times faster than B
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Measuring Execution Time Elapsed time
Total response time, including all aspects Processing, I/O, OS overhead, idle time
Determines system performance CPU time
Time spent processing a given job Excludes I/O time, other jobs’ shares
Comprises user CPU time and system CPU time
Different programs are affected differently by CPU and system performance
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CPU Clocking Operation of digital hardware governed by a
constant-rate clock
Clock (cycles)
Data transferand computation
Update state
Clock period
Clock period: duration of a clock cycle e.g., 250ps = 0.25ns = 250×10–12s
Clock frequency (rate): cycles per second e.g., 4.0GHz = 4000MHz = 4.0×109Hz
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CPU Time
Performance improved by Reducing number of clock cycles Increasing clock rate
RateClockCycles Clock CPU
Time Cycle ClockCycles Clock CPUTime CPU
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CPU Time Example Computer A: 2GHz clock, 10s CPU time Designing Computer B
Aim for 6s CPU time Can do faster clock, but causes 1.2 × clock cycles
How fast must Computer B clock be?
4GHz6s
10246s
10201.2Rate Clock
10202GHz10s
Rate ClockTime CPUCycles Clock
6sCycles Clock1.2
Time CPUCycles ClockRate Clock
99
B
9
AAA
A
B
BB
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Instruction Count and CPI
Instruction Count for a program Determined by program, ISA and compiler
Average cycles per instruction (CPI) Determined by CPU hardware Different instructions have different CPI
Average CPI affected by instruction mix
Rate ClockCPICount nInstructio
Time Cycle ClockCPICount nInstructioTime CPU
nInstructio per CyclesCount nInstructioCycles Clock
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CPI Example Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same ISA Which is faster, and by how much?
1.2500psI600psI
ATime CPUBTime CPU
600psI500ps1.2IBTime CycleBCPICount nInstructioBTime CPU
500psI250ps2.0IATime CycleACPICount nInstructioATime CPU
A is faster…
…by this much
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CPI in More Detail If different instruction classes take different
numbers of cycles
n
1iii )Count nInstructio(CPICycles Clock
Weighted average CPI
n
1i
ii Count nInstructio
Count nInstructioCPICount nInstructio
Cycles ClockCPI
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CPI Example Alternative compiled code sequences using
instructions in classes A, B, C
Class A B CCPI for class 1 2 3IC in sequence 1 2 1 2IC in sequence 2 4 1 1
Sequence 1: IC = 5 Clock Cycles
= 2×1 + 1×2 + 2×3= 10
Avg. CPI = 10/5 = 2.0
Sequence 2: IC = 6 Clock Cycles
= 4×1 + 1×2 + 1×3= 9
Avg. CPI = 9/6 = 1.5
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Performance Summary
Performance depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, Tc
The BIG Picture
Period ClockCPInsInstructioTime CPU
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Power Trends
In CMOS IC technology
§1.7 The Pow
er Wall
FrequencyVoltageload CapacitivePowerDynamic 2
×1000×30 5V → 1V
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Power Wall We can’t reduce voltage further
Transistor becomes too leaky We can’t increase the frequency further
Factorial increase of frequency exponentially increases the power
We can’t remove more heat Chips start melting
How else can we improve performance?
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Uniprocessor Performance§1.8 The S
ea Change: The S
witch to M
ultiprocessors
Constrained by power, instruction-level parallelism, memory latency
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Multiprocessors Multicore microprocessors
More than one processor per chip Requires explicitly parallel programming
Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer
Hard to do Programming for performance Load balancing Optimizing communication and synchronization
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Concluding Remarks Cost/performance is improving
Due to underlying technology development Instruction set architecture
i.e., Assembly instructions The hardware/software interface
Execution time: the best performance measure
Power is a limiting factor Use parallelism to improve performance
§1.11 Concluding R
emarks
