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Lab Phases: Trees
Array representation: [1,2,3,4,5,6,7,0,0,0,0,0,0,0,0]
•Phase 7 – Tree Height
•Phase 8 – Tree Traversal[1,2,5,0,0,4,0,0,3,6,0,0,7,0,0]
1 2 3 4 5 6 7
What needs to be done to “Process” an Instruction?
• Check the PC• Fetch the instruction from memory• Decode the instruction and set control lines appropriately• Execute the instruction
– Use ALU– Access Memory– Branch
• Store Results• PC = PC + 4, or PC = branch target
Logic Design Basics
• Information encoded in binary– Low voltage = 0, High voltage = 1– One wire per bit– Multi-bit data encoded on multi-wire buses
• Combinational element– Operate on data– Output is a function of input
• State (sequential) elements– Store information
Combinational Elements
• AND-gate– Y = A & BAB
Y
I0I1
YMux
S
Multiplexer Y = S ? I1 : I0
A
B
Y+
A
B
YALU
F
Adder Y = A + B
Arithmetic/Logic Unit Y = F(A, B)
S-R Latch
Characteristic Table Excitation TableS R Q_next Action Q Q_next S R
0 0 Q hold 0 0 0 X
0 1 0 reset 0 1 1 0
1 0 1 set 1 0 0 1
1 1 X N/A 1 1 X 0
D Flip-Flop
• Feed D and ~D to a gated S-R Latch to create a one input synchronous SR-Latch
We’ll call it a D Flip-Flop, just to be difficult.
D Flip-Flop
• D – input signal• E – enable signal,
sometimes called clock or control
E/C D Q ~Q Notes
0 X Q_prev ~Q_prev
1 0 0 1
1 1 1 0
D Flip-Flop
• D – input signal• E – enable signal,
sometimes called clock or control
E/C D Q ~Q Notes
0 X Q_prev ~Q_prev No change
1 0 0 1 Reset
1 1 1 0 Set
Sequential Elements• Register: stores data in a circuit
– Uses a clock signal to determine when to update the stored value
– Edge-triggered: update when Clk changes from 0 to 1
D
Clk
QClk
D
Q
Sequential Elements• Register with write control
– Only updates on clock edge when write control input is 1
– Used when stored value is required later
D
Clk
Q
Write
Write
D
Q
Clk
Clocking Methodology• Combinational logic transforms data during
clock cycles– Between clock edges– Input from state elements, output to state
element– Longest delay determines clock period
Building a Datapath
• Datapath– Elements that process data and addresses
in the CPU• Registers, ALUs, mux’s, memories, …
• We will build a MIPS datapath incrementally– Refining the overview design
Load/Store Instructions• Read register operands• Calculate address• Load: Read memory and update register• Store: Write register value to memory
Performance Issues
• Longest delay determines clock period– Critical path: load instruction– Instruction memory register file ALU data
memory register file
• Not feasible to vary period for different instructions
• Violates design principle– Making the common case fast
• We will improve performance by pipelining
Pipelining Analogy• Pipelined laundry: overlapping execution
– Parallelism improves performance
§4.5 An O
verview of P
ipelining Four loads: Speedup
= 8/3.5 = 2.3 Non-stop:
Speedup= 2n/0.5n + 1.5 ≈ 4= number of stages
MIPS Pipeline
• Five stages, one step per stage1. IF: Instruction fetch from memory2. ID: Instruction decode & register read3. EX: Execute operation or calculate address4. MEM: Access memory operand5. WB: Write result back to register
Pipeline Performance• Assume time for stages is
– 100ps for register read or write– 200ps for other stages
• Compare pipelined datapath with single-cycle datapath
Instr Instr fetch Register read
ALU op Memory access
Register write
Total time
lw 200ps 100 ps 200ps 200ps 100 ps 800ps
sw 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps
Pipeline Speedup
• If all stages are balanced– i.e., all take the same time
– Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
• If not balanced, speedup is less• Speedup due to increased throughput
– Latency (time for each instruction) does not decrease