Lecture 3

MSP430 Families ���� Overview

Atul Lele

Ramakrishna Reddy

19th August 2011

Outline

• Summary from previous session/s.

• Agenda for this session.

– Overview of different MSP430 families

– Overview of different peripherals

• Wrap-Up.• Wrap-Up.

• Q&A

Summary from previous

session/s

Summary from previous session/s

• Low Power Embedded Systems and Applications

• MSP430 Architecture, Instruction Set, Clock System, Memory mapMemory map

Agenda for this session

Agenda for this session

• TI Embedded Processing Portfolio

• MSP430 Generations

• MSP430 Roadmap

• F2xx Key Features

• F4xx Key Features• F4xx Key Features

• F5xx Key Features

• MSP430 Peripherals’ Overview

TI Embedded Processing Portfolio

32-bitReal-time

C2000™

Fixed & Floating Point

Up to 150 MHz

Flash32 KB to 512 KB

32-bit ARM

Stellaris M3

Industry StdLow Power

Up to 100 MHz

Flash8kB to 256kB

USB (H/D/OTG),

16-bit

Microcontrollers

MSP430

Ultra-Low Power

Up to 25 MHz

Flash1 KB to 256 KB

DSP

C647x, C64x+, C55x

Leadership DSP Performance

24,000 MMACS

Up to 3 MBL2 Cache

ARM+

ARM9Cortex A-8

Industry-Std Core,High-Perf GPP

Accelerators

MMU

DSP

C64x+ plusARM9/Cortex A-8

Industry-Std Core +DSP for Signal Proc.

4800 MMACs/1.07 DMIPS/MHz

MMU, Cache

ARM + DSP

ARM-Based

PWM, ADC, CAN, SPI, I2C

Motor Control, Digital Power,

Lighting

$1.50 to $20.00

USB (H/D/OTG),ENET(PHY, 1588), ADC, PWM, QVGA

Host Control

$2.00 to $8.00

Analog I/O, ADCLCD, USB, RF

Measurement,Sensing, General

Purpose

$0.49 to $9.00

1G EMAC, SRIO,DDR2, PCI-66

Comm, WiMAX, Industrial/

Medical Imaging

$4.00 to $99.00+

USB, LCD,MMC, EMAC

Linux/WinCE User Apps

$8.00 to $35.00

VPSS, USB, EMAC, MMC

Linux/Win +Video, Imaging,

Multimedia

$12.00 to $65.00

Software & Dev. Tools

MSP430 Generations2xx 4xx 5xx

CPU Clock (Max) 16MHz 8 & 16 MHz 25MHz

Flash/RAM (Largest comparable device) 120KB / 4KB (F24xx) 120KB / 4KB

(FG46xx) 256KB / 16KB (F54xx)

Active Current (3.0V)

µA/MIPS

1MHz 515 µA 600 µA 220µA

8MHz 525 µA/MIPS 600 µA/MIPS 165 µA/MIPS

16MHz 569 µA/MIPS N/A 188 µA/MIPS

25MHz N/A N/A 224 µA/MIPS

Standby Current (LPM3) 0.3 – 1.1µA 0.7 – 1.3µA 2.6µA (w/ active true RTC)

Power Down Current (LPM4/5) 0.1µA 0.1µA 1.6µA (LPM4) / 0.1µA

Lowest active

power in the

industry

Power Down Current (LPM4/5) 0.1µA 0.1µA 1.6µA (LPM4) / 0.1µA (LPM5)

Wake-up Time From LPM3 1µs 6µs 5µs

Flash ISP Minimum DVCC 2.2V 2.7V 1.8V

Port I/O Interrupt Capability P1/P2 P1/P2P1/P2 (F5438)

Add’l pins in future devices

Prog. Port Pin Drive Strength N/A N/A All port pins

Prog. Pull-ups/-downs All port pins N/A All port pins

Available MCLK Sources DCO, VLO, LFXT1, XT2

FLL, LFXT1, XT2 FLL, VLO, REFO, XT1, XT2

FLL Reference Clocks N/A LFXT1 REFO, XT1, XT2

Lowest active

power in the

industry

Lowest stand-by

and fastest wakeup

Write to Flash at min Vcc

MSP430 Roadmap

100+ devices

2xx-Catalog• 16 MIPS• 120 kB Flash• 8 kB RAM• 500 nA Standby• 1.8 – 3.6V

F = Flash

F23x0

The New Generation

5xx-6xx• 25MIPS• 256 kB Flash

• 16 kB RAM

Performance

Gateway

Device

F23x-F24x

F261x

F241x

FR1000

F22xx

F23x0F541x

F543x

CC430RF

F550x USB

F552xUSB

75+ devices

1xx-Catalog• 8MIPS• 60 kB Flash• 10 kB RAM• 1.8 – 3.6 V

F = Flash

C = ROM

FR = FRAM

100+ devices

4xx: LCD• 16 MIPS• 120 kB Flash• 8 kB RAM• LCD Controller, 160

segments• 1.8 – 3.6V

• 16 kB RAM

• 1.8 – 3.6V• FRAM, USB, RF• 6xx: LCD Controller• 160 uAuAuAuA/MIPS

F20xx

F21x1

F21x2

F22xx

F13x-F14x

F15x-F16x

F541x

F/C11xx

F12xx

Fx42x0

Fx42x

F44x

Fx43x

F/CG461x

FE42x2F/C41x

F47x4

Fx47x

F41x2

F471xx

F2xx Key Features

• <1µA standby LPM3

• <1µs 0-16MHz

• Zero-power BOR

• Failsafe oscillator

• Enhanced watchdog

• Pull-up / down resistors

• Hack proof boot loader• Hack proof boot loader

• 2.2V Flash ISP

• Extended temp 105°C

• Same instruction set architecture

F4xx Key Features

• <1µA standby LPM3

• <1µs 0-16MHz

• 4-120 KB Flash

• Built-in LCD Driver

• Zero-power BOR

• Pull-up / down resistors

• 2.7V Flash ISP

• Same instruction set architecture

F5xx Key Features

Ultra-Low Power– 160 µA/MIPS– 2.5 µA standby mode– Integrated LDO, BOR, WDT+, RTC– 12 MHz @ 1.8V– Wake up from standby in <5 µs

Increased Performance– Up to 25 MHz– 1.8V ISP Flash erase and write– Fail-safe, flexible clocking system– Fail-safe, flexible clocking system– User-defined Bootstrap Loader– Up to 1MB linear memory addressing

Innovative Features– Multi-channel DMA supports datamovement in standby mode– Industry leading code density– More design options including USB, RF, encryption, LCD interface

MSP430 Peripheral Overview

1xx 2xx 4xx 5xxBasic Clock System Basic Clock System + FLL, FLL+ Unified Clock System

Core voltage same as supply voltage (1.8-3.6V)

Core voltage same as supply voltage (1.8-3.6V)

Core voltage same as supply voltage (1.8-3.6V)

Programmable core voltage with integrated PMM (1.8-3.6V)

16-bit CPU 16-bit CPU, CPUX 16-bit CPU, CPUX 16-bit CPUXv2

GPIO GPIO w/ pull-up and pull-down

GPIO, LCD Controller GPIO w/pull-up and pull-down, drive strength

N/A N/A N/A CRC16

Software RTC Software RTC Software RTC with Basic Timer, Basic Timer + RTC

True 32-bit RTC w/Alarms

USART USCI, USI USART, USCI USCI, USB, RF

DMA up to 3-ch DMA up to 3-ch DMA up to 3-ch DMA up to 8-ch

MPY16 MPY16 MPY16, MPY32 MPY32

ADC10,12 ADC10,12, SD16 ADC12, SD16, OPA ADC12_A

4-wire JTAG 4-wire JTAG, 2-wireSpy Bi-Wire (Some devices)

4-wire JTAG 4-wire JTAG, 2-wire Spy Bi-Wire

Wrap-Up

• TI Embedded Processing Portfolio

• MSP430 Generations

• MSP430 Roadmap

• F2xx Key Features

• F4xx Key Features• F4xx Key Features

• F5xx Key Features

• MSP430 Peripherals’ Overview

Back-Up

16-bit RISC CPU� Efficient, ultra-low power CPU

� C-compiler friendly

� RISC architecture

� 27 core instructions

� 24 emulated instructions

� 7 addressing modes

� Constant generator

� Single-cycle register operations

� Direct memory-to-memory transfers without intermediate transfers without intermediate register holding

� Bit, byte and word processing

� 20-bit addressing on MSP430X for Flash >64KB

� 16-bit data bus allows direct manipulation of word-wide arguments

� Orthogonal architecture with every instruction usable with every addressing mode

Clock System

LFXT Oscillator

XT2 Oscillator

DCO

Naming convention

MSP430 16-bit FamilyMixed Signal Processor

MSP430 16-bit FamilyMixed Signal Processor

MSP430

MSX430

PMS430

Standard

Experimental

Prototype

MSP430 F 11 2 1 A I DW

Revision NumberRevision Number

Temperature RangeTemperature Range

I

C

Industrial

(-40°C…+85°C)

Commercial

(0°C…+70°C)Memory TypeMemory Type

F

C

Flash

ROMPackage TypePackage Type

Device ConfigurationDevice Configuration

41_

43_

42_

44_

Basic version

12-bit ADC

3 x 16-bit Σ∆Σ∆Σ∆Σ∆−−−−ADCs

12-bit SAR ADC +

MPY, USART, …

With LCD Driver

W42_

G42_

E42_

Water Meter

Glucose Meter

Electricity Meter

11_1

12_

11_2

12_2

13_

14_

14_1

15_

16_

16_1

Basic version

+USART

ADC10

ADC10+USART

ADC12+USART

ADC12+USART+MPY

14_ without ADC12

+I2C+SVS+DMA+DAC

+I2C+SVS+DMA+DAC

16_ + more RAM

Without LCD Driver

Flash SizeFlash Size

0

1

2

3

4

5

6

7

8

9

1K

2K

4K

8K

12K

16K

24K

32K

48K

60K

C ROMPackage TypePackage Type

PW

DW

DGV

RGE

RHE

RTD

PM

RAG

PN

PZ

Y

TSSOP 20/28

SOP 20/28

TVSOP 20

QFN 24

QFN 32

QFN 64

LQFP 64

TQFP 64

LQFP 80

LQFP 100

waffle pack

Flash Memory Controller

• The MSP430 flash memory is bit, byte, and word addressable and

programmable. The flash memory module has an integrated controller that

controls programming and erase operations. The controller has three or four

registers (see the device-specific data sheet), a timing generator, and a

voltage generator to supply program and erase voltages.

MSP430 flash memory features include:

• Internal programming voltage generation• Internal programming voltage generation

• Bit, byte, or word programmable

• Ultralow-power operation

• Segment erase and mass erase

• Marginal 0 and marginal 1 read mode.

- Implemented in MSP430FG47x,MSP430F47x, MSP430F47x3/4, and MSP430F471xx devices only (see the device-specific data sheet.

Supply Voltage Supervisor (SVS)

The supply voltage supervisor (SVS) is used to monitor the AVCC supply

voltage or an external voltage. The SVS can be configured to set a flag or

generate a POR reset when the supply voltage or external voltage drops

below a user-selected threshold.

The SVS features include:

• AVCC monitoring

• Selectable generation of POR

• Output of SVS comparator accessible by software

• Low-voltage condition latched and accessible by software

• 14 selectable threshold levels

• External channel to monitor external voltage

Multiplier – 16 bit & 32 bit

The 32-bit hardware multiplier is a peripheral and is not part of the MSP430

CPU. This means its activities do not interfere with the CPU activities. The

multiplier registers are peripheral registers that are loaded and read with CPU

instructions.

The hardware multiplier supports: (Blue are applicable for 16 and 32 bit)

• Unsigned multiply• Unsigned multiply

• Signed multiply

• Unsigned multiply accumulate

• Signed multiply accumulate

• 8-bit, 16-bit, 24-bit and 32-bit operands

• Saturation

• Fractional numbers

• 8-bit and 24-bit multiplications without requiring a “sign extend” instruction

DMA Controller

The direct memory access (DMA) controller transfers data from one address to another, without CPU

intervention, across the entire address range. E.g. The DMA controller can move data from the ADC12

conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral

modules. It can also reduce system power consumption by allowing the CPU to remain in a low-power

mode without having to awaken to move data to or from a peripheral.

The DMA controller features include:

• Up to three independent transfer channels

• Configurable DMA channel priorities• Configurable DMA channel priorities

• Requires only two MCLK clock cycles per transfer

• Byte or word and mixed byte/word transfer capability

• Block sizes up to 65535 bytes or words

• Configurable transfer trigger selections

• Selectable edge or level-triggered transfer

• Four addressing modes

• Single, block, or burst-block transfer modes

Digital IO

MSP430 devices have up to ten digital I/O ports implemented, P1 to P10. Each

port has eight I/O pins.

Every I/O pin is individually configurable for input or output direction, and each I/O

line can be individually read from or written to.

Ports P1 and P2 have interrupt capability. Each interrupt for the P1 and P2 I/O

lines can be individually enabled and configured to provide an interrupt on a

rising edge or falling edge of an input signal. rising edge or falling edge of an input signal.

All P1 I/O lines source a single interrupt vector, and all P2 I/O lines source a

different, single interrupt vector.

The digital I/O features include:

• Independently programmable individual I/Os

• Any combination of input or output

• Individually configurable P1 and P2 interrupts

• Independent input and output data registers

Watchdog (WDT+)

The primary function of the watchdog timer (WDT) module is to perform a

controlled system restart after a software problem occurs. If the selected time

interval expires, a system reset is generated. If the watchdog function is not

needed in an application, the module can be configured as an interval timer

and can generate interrupts at selected time intervals.

Features of the watchdog timer module include:Features of the watchdog timer module include:

• Four software-selectable time intervals

• Watchdog mode

• Interval mode

• Access to WDT control register is password protected

• Control of RST/NMI pin function

• Selectable clock source

• Can be stopped to conserve power

• Clock fail-safe feature in WDT+

Basic Timer 1

• The Basic Timer1 supplies LCD timing and low frequency time intervals. The Basic Timer1 is two independent 8-bit timers that can also be cascaded to form one 16-bit timer function.

• Some uses for the Basic Timer1 include:

– Real-time clock (RTC) function

– Software time increments

• Basic Timer1 features include:• Basic Timer1 features include:

– Selectable clock source

– Two independent, cascadable 8-bit timers

– Interrupt capability

– LCD control signal generation

RTC – Real Time Clock

The Real-Time Clock (RTC) module can be used as a general-purpose 32-bit timer or as a RTC with calendar function.

RTC features include:

• Calender and clock mode

• 32-bit counter mode with selectable clock sources• 32-bit counter mode with selectable clock sources

• Automatic counting of seconds, minutes, hours, day of week, day of month, month and year in calender mode.

• Interrupt capability

• Selectable BCD format

Timer-A

• Timer_A is a 16-bit timer/counter with three or five capture/compare registers.

• Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

• Timer_A features include:• Timer_A features include:

– Asynchronous 16-bit timer/counter with four operating modes

– Selectable and configurable clock source

– Three or five configurable capture/compare registers

– Configurable outputs with PWM capability

– Asynchronous input and output latching

– Interrupt vector register for fast decoding of all Timer_A interrupts

Timer-B

Timer_B is a 16-bit timer/counter with three or seven capture/compare

registers. Timer_B can support multiple capture/compares, PWM outputs,

and interval timing. Timer_B also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and

from each of the capture/compare registers.

• Timer_B features include:

– Asynchronous 16-bit timer/counter with four operating modes and four

selectable lengths

– Selectable and configurable clock source

– Three or seven configurable capture/compare registers

– Configurable outputs with PWM capability

– Double-buffered compare latches with synchronized loading

– Interrupt vector register for fast decoding of all Timer_B interrupts

USART - UARTIn asynchronous mode, the USART connects the MSP430 to an external

system

via two external pins, URXD and UTXD. UART mode is selected when the SYNC

bit is cleared.

• UART mode features include:

– 7- or 8-bit data with odd parity, even parity, or non-parity

– Independent transmit and receive shift registers– Independent transmit and receive shift registers

– Separate transmit and receive buffer registers

– LSB-first data transmit and receive

– Built-in idle-line and address-bit communication protocols for

– multiprocessor systems

– Receiver start-edge detection for auto-wake up from LPMx modes

– Programmable baud rate with modulation for fractional baud rate support

– Status flags for error detection and suppression and address detection

– Independent interrupt capability for receive and transmit

USART - SPI

In synchronous mode, the USART connects the MSP430 to an external

system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is

selected when the SYNC bit is set and the I2C bit is cleared.

• SPI mode features include:

– 7-bit or 8-bit data length

– 3-pin and 4-pin SPI operation

– Master or slave modes

– Independent transmit and receive shift registers

– Separate transmit and receive buffer registers

– Selectable UCLK polarity and phase control

– Programmable UCLK frequency in master mode

– Independent interrupt capability for receive and transmit

USCI

The universal serial communication interface (USCI) modules support

multiple serial communication modes. Different USCI modules support

different modes. Each different USCI module is named with a different

letter. If one device has two USCI_A modules, they are named USCI_A0

and USCI_A1.

• The USCI_Ax modules support:– UART mode

– Pulse shaping for IrDA communications

– Automatic baud rate detection for LIN communications

– SPI mode

• The USCI_Bx modules support:– I2C mode

– SPI mode

USCI - UARTIn asynchronous mode, the USCI_Ax modules connect the MSP430 to an

external system via two external pins, UCAxRXD and UCAxTXD. UART

mode is selected when the UCSYNC bit is cleared.

• UART mode features include:

• 7- or 8-bit data with odd, even, or non-parity

• Independent transmit and receive shift registers

• Separate transmit and receive buffer registers

• LSB-first or MSB-first data transmit and receive• LSB-first or MSB-first data transmit and receive

• Built-in idle-line and address-bit communication protocols for

• multiprocessor systems

• Receiver start-edge detection for auto-wake up from LPMx modes

• Programmable baud rate with modulation for fractional baud rate support

• Status flags for error detection and suppression

• Status flags for address detection

• Independent interrupt capability for receive and transmit

UART - SPIIn synchronous mode, the USCI connects the MSP430 to an external

system via three or four pins: UCxSIMO, UCxSOMI, UCxCLK, and

UCxSTE. SPI mode is selected when the UCSYNC bit is set and SPI

mode (3-pin or 4-pin) is selected with the UCMODEx bits.

• SPI mode features include:

– 7- or 8-bit data length

– LSB-first or MSB-first data transmit and receive

– 3-pin and 4-pin SPI operation– 3-pin and 4-pin SPI operation

– Master or slave modes

– Independent transmit and receive shift registers

– Separate transmit and receive buffer registers

– Continuous transmit and receive operation

– Selectable clock polarity and phase control

– Programmable clock frequency in master mode

– Independent interrupt capability for receive and transmit

– Slave operation in LPM4

UART – I2CIn I2C mode, the USCI module provides an interface between the MSP430 and

I2C-compatible devices connected by way of the two-wire I2C serial bus.

External components attached to the I2C bus serially transmit and/or receive

serial data to/from the USCI module through the 2-wire I2C interface.

• The I2C mode features include:

– Compliance to the Philips Semiconductor I2C specification v2.1

– 7-bit and 10-bit device addressing modes

– General call

– START/RESTART/STOP

– Multi-master transmitter/receiver mode

– Slave receiver/transmitter mode

– Standard mode up to 100 kbps and fast mode up to 400 kbps support

– Programmable UCxCLK frequency in master mode

– Designed for low power

– Slave receiver START detection for auto-wake up from LPMx modes

– Slave operation in LPM4

OA – Operational Amplifiers

• The OA op amps support front-end analog signal conditioning prior to analog-to-digital conversion.

• Features of the OA include:

– Single supply, low-current operation

– Rail-to-rail output

– Software selectable rail-to-rail input– Software selectable rail-to-rail input

– Programmable settling time vs power consumption

– Software selectable configurations

– Software selectable feedback resistor ladder for PGA implementations

Comparator A and A+

The comparator_A module supports precision slope analog-to-digital

conversions, supply voltage supervision, and monitoring of external

analog signals.

• Features of Comparator_A include:

– Inverting and non-inverting terminal input multiplexer

– Software selectable RC-filter for the comparator output

– Output provided to Timer_A capture input

– Software control of the port input buffer

– Interrupt capability

– Selectable reference voltage generator

– Comparator and reference generator can be powered down

– Input Multiplexer

LCD, LCD_A – LCD Controller

The LCD controller directly drives LCD displays by creating the ac segment

and common voltage signals automatically. The MSP430 LCD controller can

support static, 2-mux, 3-mux, and 4-mux LCDs.

• The LCD controller features are:

– Display memory

– Automatic signal generation

– Configurable frame frequency– Configurable frame frequency

– Blinking capability

– Support for 4 types of LCDs:

• Static

• 2-mux, 1/2 bias

• 3-mux, 1/3 bias

• 4-mux, 1/3 bias

– Regulated Charge Pump

ADC10The ADC10 module supports fast, 10-bit analog-to-digital conversions. The

module implements a 10-bit SAR core, sample select control, reference

generator, and data transfer controller (DTC).

The DTC allows ADC10 samples to be converted and stored anywhere in

memory without CPU intervention. The module can be configured with user

software to support a variety of applications.

• ADC10 features include:

• Greater than 200 ksps maximum conversion rate

• Monotonic10-bit converter with no missing codes

• Sample-and-hold with programmable sample periods• Sample-and-hold with programmable sample periods

• Conversion initiation by software or Timer_A

• Software selectable on-chip reference voltage generation (1.5 V or 2.5 V)

• Software selectable internal or external reference

• Up to twelve external input channels

• Conversion channels for internal temperature sensor, VCC, and external

• References

• Selectable conversion clock source

• Single-channel, repeated single-channel, sequence, and repeated sequence conversion modes

• ADC core and reference voltage can be powered down separately

• Data transfer controller for automatic storage of conversion results

ADC12• The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module

implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

• ADC12 features include:

– Greater than 200-ksps maximum conversion rate

– Monotonic 12-bit converter with no missing codes

– Sample-and-hold with programmable sampling periods controlled by software or timers.

– Conversion initiation by software, Timer_A, or Timer_B

– Software selectable on-chip reference voltage generation (1.5 V or 2.5 V)

– Software selectable internal or external reference

– Eight individually configurable external input channels (twelve on MSP430FG43x and MSP430FG461x devices)

– Conversion channels for internal temperature sensor, AVCC, and external references

– Independent channel-selectable reference sources for both positive and negative references

– Selectable conversion clock source

– Single-channel, repeat-single-channel, sequence, and repeat-sequence conversion modes

– ADC core and reference voltage can be powered down separately

– Interrupt vector register for fast decoding of 18 ADC interrupts

– 16 conversion-result storage registers

SD16

• The SD16 module consists of up to three independent sigma-delta analog-to-digital converters and an internal voltage reference. Each channel has up to 8 fully differential multiplexed analog input pairs including a built-in temperature sensor. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to 256. Additional filtering can be done in software.

• Features of the SD16 include:• Features of the SD16 include:

– 16-bit sigma-delta architecture

– Up to three independent, simultaneously sampling ADC channels

– Up to eight multiplexed differential analog inputs per channel

– Software selectable on-chip reference voltage generation (1.2 V)

– Software selectable internal or external reference

– Built-in temperature sensor accessible by all channels

– Up to 1.048576-MHz modulator input frequency

– Selectable low-power conversion mode

SD16A

• Features of the SD16_A include:– 16-bit sigma-delta architecture

– Up to seven independent, simultaneously-sampling ADC channels.

– Up to eight multiplexed differential analog inputs per channel

– Software selectable on-chip reference voltage generation (1.2 V)

– Software selectable internal or external reference

– Built-in temperature sensor accessible by all channels

– Up to 1.1-MHz modulator input frequency

– High impedance input buffer

– Selectable low-power conversion mode

DAC12

• The DAC12 module is a 12-bit voltage-output DAC. The DAC12 can be configured in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.

• Features of the DAC12 include:

– 12-bit monotonic output– 12-bit monotonic output

– 8-bit or 12-bit voltage output resolution

– Programmable settling time vs power consumption

– Internal or external reference selection

– Straight binary or 2s compliment data format

– Self-calibration option for offset correction

– Synchronized update capability for multiple DAC12s

SCAN-IF (Scan Interface)• The Scan IF module is used to automatically measure linear or

rotational motion with the lowest possible power consumption. The Scan IF consists of three blocks: the analog front end (AFE), the processing state machine (PSM), and the timing state machine (TSM). The analog front end stimulates the sensors, senses the signal levels and converts them into their digital representation. The digital signals are passed into the processing state machine. The processing state machine is used to analyze and count rotation or motion. The timing state machine controls the analog front end and the processing state machine.machine.

• The Scan IF features include:– Support for different types of LC sensors

– Measurement of sensor signal envelope

– Measurement of sensor signal oscillation amplitude

– Support for resistive sensors such as Hall-effect or giant magneto-resistive (GMR) sensors

– Direct analog input for A/D conversion

– Direct digital input for digital sensors such as optical decoders

– Support for quadrature decoding

EEM – Embedded Emulation ModuleEvery MSP430 flash-based microcontroller implements an embedded

emulation module (EEM). It is accessed and controlled through JTAG.

In general, the following features are available:

• Nonintrusive code execution with real-time breakpoint control

• Single step, step into, and step over functionality

• Full support of all low-power modes

• Support for all system frequencies, for all clock sources

• Up to eight (device dependent) hardware triggers/breakpoints on memory address bus (MAB) or memory data bus (MDB)address bus (MAB) or memory data bus (MDB)

• Up to two (device dependent) hardware triggers/breakpoints on CPU register write accesses

• MAB, MDB ,and CPU register access triggers can be combined to form up to eight (device dependent) complex triggers/breakpoints

• Trigger sequencing

• Storage of internal bus and control signals using an integrated trace buffer

• Clock control for timers, communication peripherals, and other modules on a global device level or on a per-module basis during an emulation stop