Lecture 9: Combinational Circuit Design

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 2

Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 3

Example 1module mux(input s, d0, d1,

output y);

assign y = s ? d1 : d0;

endmodule

1) Sketch a design using AND, OR, and NOT gates.

D0S

D1S

Y

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 4

Example 22) Sketch a design using NAND, NOR, and NOT gates.

Assume ~S is available.

Y

D0S

D1S

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 5

Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic

– Remember DeMorgan’s Law

Y Y

Y

D

Y

(a) (b)

(c) (d)

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 6

Example 33) Sketch a design using one compound gate and one

NOT gate. Assume ~S is available.

Y

D0SD1S

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 7

Compound Gates Logical Effort of compound gates

ABCD

Y

ABC

Y

A

BC

C

A B

A

B

C

D

A

C

B

D

2

21

4

44

2

2 2

2

4

4 4

4

gA = 6/3

gB = 6/3

gC = 5/3

p = 7/3

gA = 6/3

gB = 6/3

gC = 6/3

p = 12/3

gD = 6/3

YA

A Y

gA = 3/3

p = 3/3

2

1YY

unit inverter AOI21 AOI22

A

C

DE

Y

B

Y

B C

A

D

E

A

B

C

D E

gA = 5/3

gB = 8/3

gC = 8/3

gD = 8/3

2

2 2

22

6

6

6 6

3

p = 16/3

gE = 8/3

Complex AOI

Y A B C Y A B C D Y A B C D E Y A

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 8

Example 4 The multiplexer has a maximum input capacitance of

16 units on each input. It must drive a load of 160 units. Estimate the delay of the two designs.

2 2 4

(4 / 3) (4 / 3) 16 / 9

160 / 9

ˆ 4.2

ˆ 12.4

N

P

G

F GBH

f F

D Nf P

Y

D0S

D1S

Y

D0SD1S

H = 160 / 16 = 10 B = 1 N = 2

4 1 5

(6 / 3) (1) 2

20

ˆ 4.5

ˆ 14

N

P

G

F GBH

f F

D Nf P

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 9

6

6 6

6

10

10Y

24

12

10

10

8

8

88

8

8

88

25

25

2525Y

16 16160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36

Example 5 Annotate your designs with transistor sizes that

achieve this delay.

Y

8

8

88

8

8

88

25

25

2525Y

16 160 * (4/3) / 4.2 = 50

YY

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 10

Input Order Our parasitic delay model was too simple

– Calculate parasitic delay for Y falling• If A arrives latest? 2• If B arrives latest? 2.33

6C

2C2

2

22

B

Ax

Y

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 11

Inner & Outer Inputs Inner input is closest to output (A) Outer input is closest to rail (B)

If input arrival time is known– Connect latest input to inner terminal

2

2

22

A

B

Y

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 12

Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical

– Use smaller transistor on A (less capacitance)– Boost size of noncritical input– So total resistance is same

gA = 10/9

gB = 2

gtotal = gA + gB = 28/9

Asymmetric gate approaches g = 1 on critical input But total logical effort goes up

Areset

Y

4

4/3

22

reset

A

Y

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 13

Symmetric Gates Inputs can be made perfectly symmetric

A

B

Y2

1

1

2

1

1

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 14

Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical

– Downsize noncritical nMOS transistor

Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.

– gu = 2.5 / 3 = 5/6

– gd = 2.5 / 1.5 = 5/3

1/2

2A Y

1

2A Y

1/2

1A Y

HI-skewinverter

unskewed inverter(equal rise resistance)

unskewed inverter(equal fall resistance)

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 15

HI- and LO-Skew Def: Logical effort of a skewed gate for a particular

transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.

Skewed gates reduce size of noncritical transistors– HI-skew gates favor rising output (small nMOS)– LO-skew gates favor falling output (small pMOS)

Logical effort is smaller for favored direction But larger for the other direction

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 16

1/2

2A Y

Inverter

1

1

22

B

AY

B

A

NAND2 NOR2

1/21/2

4

4

HI-skew

LO-skew1

1A Y

2

2

11

B

AY

B

A

11

2

2

gu = 5/6gd = 5/3gavg = 5/4

gu = 4/3gd = 2/3gavg = 1

gu = 1gd = 2gavg = 3/2

gu = 2gd = 1gavg = 3/2

gu = 3/2gd = 3gavg = 9/4

gu = 2gd = 1gavg = 3/2

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

4

4

unskewedgu = 1gd = 1gavg = 1

gu = 4/3gd = 4/3gavg = 4/3

gu = 5/3gd = 5/3gavg = 5/3

Y

1/2

2A Y

Inverter

1

1

22

B

AY

B

A

NAND2 NOR2

1/21/2

4

4

HI-skew

LO-skew1

1A Y

2

2

11

B

AY

B

A

11

2

2

gu = 5/6gd = 5/3gavg = 5/4

gu = 4/3gd = 2/3gavg = 1

gu = gd =gavg =

gu = gd = gavg =

gu = gd = gavg =

gu = gd =gavg =

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

4

4

unskewedgu = 1gd = 1gavg = 1

gu = 4/3gd = 4/3gavg = 4/3

gu = 5/3gd = 5/3gavg = 5/3

Y

1/2

2A Y

Inverter

B

AY

B

A

NAND2 NOR2

HI-skew

LO-skew1

1A Y

B

AY

B

A

gu = 5/6gd = 5/3gavg = 5/4

gu = 4/3gd = 2/3gavg = 1

gu = gd =gavg =

gu =gd = gavg =

gu =gd =gavg =

gu =gd =gavg =

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

4

4

unskewedgu = 1gd = 1gavg = 1

gu = 4/3gd = 4/3gavg = 4/3

gu = 5/3gd = 5/3gavg = 5/3

Y

Catalog of Skewed Gates

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 17

Asymmetric Skew Combine asymmetric and skewed gates

– Downsize noncritical transistor on unimportant input

– Reduces parasitic delay for critical input

Areset

Y

4

4/3

21

reset

A

Y

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 18

Best P/N Ratio We have selected P/N ratio for unit rise and fall

resistance ( = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter

– Delay driving identical inverter

– tpdf = (P+1)

– tpdr = (P+1)(/P)

– tpd = (P+1)(1+/P)/2 = (P + 1 + + /P)/2

– dtpd / dP = (1- /P2)/2 = 0

– Least delay for P =

1

PA

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 19

Inverter NAND2 NOR2

1

1.414A Y

2

2

22

B

AY

B

A

11

2

2

fastest P/N ratio gu = 1.15

gd = 0.81gavg = 0.98

gu = 4/3gd = 4/3gavg = 4/3

gu = 2gd = 1gavg = 3/2

Y

Inverter NAND2 NOR2

1

1.414A Y

2

2

22

B

AY

B

A

11

2

2

fastest P/N ratio gu =

gd = gavg =

gu = gd =gavg =

gu = gd = gavg =

Y

P/N Ratios In general, best P/N ratio is sqrt of equal delay ratio.

– Only improves average delay slightly for inverters– But significantly decreases area and power

CMOS VLSI DesignCMOS VLSI Design 4th Ed.10: Combinational Circuits 20

Observations For speed:

– NAND vs. NOR– Many simple stages vs. fewer high fan-in stages– Latest-arriving input

For area and power:– Many simple stages vs. fewer high fan-in stages