ECE 468: Analog and Mixed Signal VLSI Design
Lecture-1
VLSI Technology, and Device Models and Characterization
Masud H. ChowdhuryElectrical and Computer Engineering
University of Illinois at Chicago
2
Silicon VLSI TechnologyIngredient:
– Silicon – Polysilicon– Oxide (SiO2)– Impurities (Diffusion and Implant)– Metal (Cu, Al)
Devices and Components:– pn-junction Diode – BJT (NPN and PNP)– MOSFET (NMOS and PMOS)– JFET– Resistor, Inductor and Capacitor
Layers:– Diffusion and Well– Poly and Metal (Metal 1, Metal2 …….)– Buried Channel– Contact and Via
3
BJT and MOSFET
n p nE
B
C
p n pE
B
C
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
n
GateSource Drain
bulk Si
p+ p+
4
Device ModelingWhat is Modeling?
Device models represent the functional relationship among the terminal electrical variables of the devicesThe electrical characteristics and the corresponding models depend upon a set of parameters
What are parameters and variables used in the modeling?Geometrical or process variables
width, length, thickness, etc. of the devicesDesign variables dependent on device physics
intrinsic and parasitic capacitance, resistance, conductance, etc
Why Device Models are Needed?Design and analysis of integrated circuits depend on utilizing suitable modelsAccuracy of the analysis and simulation depend on the accuracy of the modelsHigher accuracy requirement leads to higher complexity of the models
5
Device ModelingSetting the parameters and variables?
Circuit designers can control and set the design parametersCircuit designers can not change most of the process parameters once the process has been specified. However, their observation and experience can be shared with process engineers to help specify the process to be used for a particular design
Accuracy of the Models:For most physical device only a good approximation of the actual relationship of the electrical variables can be obtained.Tradeoffs must be made between the quality of approximation and its complexityThe required accuracy and the intended use of the models are factors the engineers consider when making these tradeoffs
What are the types of modeling?Device modeling can be of two types
DC model or large signal model - normally used in digital design and analysisAC model or small signal model – normally used in analog design and analysis
6
Device ModelingDC or Large Signal Models:
Large signal models are developed to calculate total currents and voltages in the transistor circuitsThese models are mathematical or numerical relationships that relate actual terminal voltages and currents of the device at DC and low frequenciesThese models are valid for a wide range of terminal voltages and currents, and at frequencies where the difference between the actual and DC solution is deemed negligible for the problem under investigation
AC or Small Signal Models:Most circuits perform their task over a limited excitation range, which is typically specified in terms of a maximum input signal excursion about some nominal point. The points (nodal voltages and branch currents) about which the circuit operates are termed bias points or quiescent points (Q-points).Internal to the circuits these input variations cause excursion around the quiescent point. Often these inputs are sinusoids of small amplitude compared to the supply voltages providing power to the circuitAn analysis how these small sinusoids propagate through the circuit is termed small signal analysis or ac analysis.How small the signals should be to be considered small signals depend on the circuit topology, device characteristics, and Q-point.
7
Device ModelingUse of Device Models:
Large signal models are generally used in digital design where the devices normally act as switches.Analog circuits often operate with very small signals compared to bias voltages and currents in the circuit. In these circumstances small signal models can be used to calculate circuit gain and terminal impedances without the necessity of including the bias quantities.Often analog designers require both small and large signal characteristics. The performance specification of analog design can be expressed in terms of small signal characteristics, whereas knowledge of the large signal characteristics is necessary for biasing (setting the quiescent point)To simplify the calculation of circuit gain and terminal impedances, small signal models of MOSFET can be used
8
BJT for Analog and MOSFET for Digital – Why?MOSFET for Digital IC:
Provide very high densityLow power consumption
Quiescent power dissipated by the base current of BJT limited the integration density as IC became more complexVacuum tubes were replaced due to high power consumption. For the same reason BJT started loosing favor as compared MOSFETMOSFET offers the advantage of almost zero control current while idleLow power consumption of MOSFET allows very high integration
Improvement of silicon processes made MOSFETs more popular due to simpler fabrication process, and lower cost and area per device
BJT for Analog IC:For stand alone analog IC BJT still offers many advantagesTransconductance per unit bias current is much higher in BJTFor many systems where analog techniques are used in some parts of the integrated circuits, and digital on other parts, BJTs are often preferred for analog part and MOSFETs for the digital part.
9
MOSFET in Analog DesignFor lower cost and better portability, higher integration density and lower power consumption have become two most important design matrices for current integrated circuit designs.To achieve these goals process technologies to provide both BJT and MOSFET in the same process have been developedHowever, these mixed process technologies are complex and more expensive than pure MOS processes.This economic consideration drive integrated circuit manufacturers to use all MOS processes in many practical cases
10
Large Signal Behaviors and Models of MOSFETConsider the NMOS transistor with the given biasing condition:
The width (X) and the charge (Q) per unit area of the depletion layer under the oxide is given by
φ is the potential in the depletion region at the oxide-silicon interface, ε is the permittivity of silicon, and NA is the doping density
When the surface potential reaches a critical value ( twice the Fermi level φf) a phenomenon known as inversion occurs.
In the presence of the inversion layer and without a substrate bias the depletion layer has a constant charge density Qb0
With positive substrate bias VSB the charge density will be Qb
2/12
⎟⎟⎠
⎞⎜⎜⎝
⎛=
AqNX εφ
n +n +
p -su b s tra te
DSG
B
V G S
+
-
D e p le tio nR e g io n
n -c h a n n e l
fAb qNQ φε 220 = )2(2 SBfAb VqNQ += φε
εφAA qNXqNQ 2==
11
Large Signal Behaviors and Models of MOSFETThe gate source voltage required to produce an inversion layer is called the threshold voltage (Vt) given by:
Let us now consider the bias condition as shown below:Cut-off Region: • ID = 0 for VGS ≤ Vt• MOSFET is OFFPinch-off Condition: • VGS > Vt• VDS = (VGS – Vt) = VDSAT
n +n +
p -su b s tra te
DSG
B
V G S
+
-
D e p le tio nR e g io n
n -c h a n n e l
ox
oxox
Aox
fSBftt
tCand
NqC
Here
VVV
ε
εγ
φφγ
=
=
−++=
21
)22(0
n+n+
p-substrate
DS
GVGS
yL
V(y) +–
VDS ID
12
Large Signal Behaviors and Models of MOSFETLinear or Resistive Region:
– With VGS > VT, and VDS < VGS - VT, current ID can be given by
Saturation Region:– With VGS > VT, and VDS >= VGS – VT , current ID is given by
( )
areaunitper cap.oxidethicknessoxide&oxidegateofperm.
mobilityelectron channeltheoflength&channeltheofwidth
trancond.process
2)(
'
2'
===
===
==
⎥⎦
⎤⎢⎣
⎡−−=
ox
oxox
n
ox
oxnoxnn
DSDSTGSnD
ct
LWt
ck
Here
VVVVL
WkI
εμ
εμμ
[ ]2'
)(2 TGS
nD VV
LWkI −=
13
Large Signal Behaviors and Models of MOSFET• Channel Length Modulation Effect:
– Ideal model predicts that drain current is independent of VDS in the pinch-off region
– However, the depletion layer between the physical pinch-off point and the drain expands with the increase of VDS
– If this depletion-layer width is Xd, the effective channel length is Leff = L – Xd
– Consequently, the effective length of the channel is decreased leading to higher drain current as shown below.
– Since XD (and Leff) is function of VDS in saturation, ID varies with VDS. This effect is called channel length modulation. This effect can be observed as shown below:
( )2'
2 tGSeff
D VVLWkI −=
Depletion layer expands with VDS
DS
d
eff
D
DS
efftGS
effDS
D
dVdX
LI
dVdL
VVLWk
VI
=−−=∂∂ 2
2
'
)(2
14
Large Signal Behaviors and Models of MOSFET• Channel Length Modulation Effect:
– For MOSFET device a special parameter known as Early voltage (VA), is defined as follows:
– The parameter used for characterizing channel length modulation (λ) is the reciprocal VA:
– After including the effect of channel length modulation in the I-V model the saturation current can be expressed as follows:
– The above results can be used to form a large signal model of an NMOS device– Here ID is given by the models derived above
1
/
−
⎟⎟⎠
⎞⎜⎜⎝
⎛=
∂∂=
DS
deff
DSD
DA dV
dXLVI
IV
AV1
=λ
)1()(2
1)(2
2'
2'
DStGSA
DStGSD VVV
LWk
VVVV
LWkI λ+−=⎟⎟
⎠
⎞⎜⎜⎝
⎛+−=
15
Small Signal Element - Transconductance• Consider the MOS transistor with the bias voltage as shown: • The quiescent drain current ID is in saturation if VGS>Vt and VDD>VGS-Vt
• If a small signal input voltage vi is applied in series with VGS and produce a small variation in drain current id, the total current: Id = ID + id
• Transconductance: – The transconductance quantifies the drain current variation with a gate-source
voltage variation while keeping the drain-source voltage constant:
– gm is proportional square root of the bias current– gm depends on device geometry
DtGSm
DS
DStGSGS
Dm
ILWkVV
LWkg
Vfor
VVVLWk
VIg
''
'
2)(
1
)1)((
=−=
<<
+−=∂∂
=
λ
λ
16
Small Signal Element - Transconductance• Transconductance:
• Another important factor is the ratio of the transconductance to the bias current:
– Typically overdrive Vov for MOSFET is chosen to be high to make the transistor faster, leading to low transconductance per given bias current
– For analog application of MOS devices low transconductance-to-current ratio is a challenge, because high quality analog circuits require high value of this ratio
DtGSm
DS
DStGSGS
Dm
IL
WkVVL
Wkg
Vfor
VVVL
WkVIg
''
'
2)(
1
)1)((
=−=
<<
+−=∂∂
=
λ
λ
MOSFETofdriveoverVVVVI
gov
ovtGSD
m ⇒=−
= .......22
17
Limitation of Small Signal Analysis• Transconductance:
– The transconductance calculated in the above expression is valid for small-signal analysis only
– To determine the limitation of this analysis let us consider the total current in the above circuit:
– If the magnitude of the small-signal input vi is less than 20% of Vov, the small signal analysis is accurate within about 10%.
DtGSm IL
WkVVL
Wkg '' 2)( =−=
[ ]
[ ]
imd
ovi
tGS
iitGSd
iitGSDdD
iitGStGStiGSd
vgiVthanlessmuchisvinputsignalsmalltheofmagnitudetheif
VVvvVV
LWki
vvVVL
WkIiI
vvVVVVL
WkVvVL
WkI
≈
−
⎥⎦
⎤⎢⎣
⎡−
+−=
+−+=+
+−+−=−+=
2
)(21)(
)(22
)(2)(2
)(2
'
2'
22'
2'
18
Small Signal Elements – Intrinsic Cgs and CgdGate-to-Channel Capacitance:• The intrinsic capacitance due to MOS gate and channel structure can be approximated as
a simple parallel plate capacitance given by Cgc = CoxWL• The gate of a MOSFET is separated from the channel by a thin oxide, which has a per
unit area capacitance equal to Cox = εox/tox
• However, the bottom plate of this capacitor depends on the mode of the operation of the transistor. So the capacitance varies in both magnitude and in its division, depending on the operation region and terminal voltage
• In linear region a conducting channel exists from source to drain. Symmetry dictates that the capacitance is evenly distributed between drain and source. Hence
Cgs = Cgd = CoxWL/2• In saturation the channel is pinched-off at the drain end. The capacitance Cgd between
gate and drain is approximately zero. All the capacitance is therefore between gate and source, which is approximately given by: Cgs = (2/3)CoxWL
S D
G
CGC
S D
G
CGCS D
G
CGC
19
Input and Output Resistance• Input Resistance:
– MOSFET gate is insulated from the channel.– At low frequency gate current is almost zero– Consequently, the input resistance is almost infinite
• Output Resistance:– Due to channel length modulation drain current (ID) in saturation region increases with
the increase of drain voltage (VDS).– Small signal output resistance is defined as:
– After simplification we get:
– Here ro is the small signal output resistance
DSDS
DD
DSD
VVII
bygivenbecanVchangeatodueIcurrentdraininchangeThe
Δ∂∂
=Δ
ΔΔ
oDD
A
D
DS rII
VI
V===
ΔΔ
λ1
D
DSo I
VrΔΔ
=
20
Basic Small Signal Model• Combination of the above elements produces the small signal model for an
NMOS transistor in saturation or active region.• This model is called hybrid-π model• This model predicts that when gate-source voltage is increased the incremental
current id flowing from drain to source increases.• Since DC current ID also flows from drain to source in an NMOS, increasing the
gate-source voltage also increases the total current Id.
• This model is also valid for PMOS model. – Here also the incremental current id flowing from drain to source increases with gate-
source voltage.– However, the DC current ID in PMOS flows from source to drain, since source acts as
the source for holes. Therefore, id flows in the opposite direction of ID, reducing the total drain current Id.
21
Including Non Ideal Behavior in Small Signal Model• Body Effect
• Drain current depends on two voltage: VGS and VBS.• VGS controls channel conductivity• VBS controls threshold voltage, which changes drain current when VGS is fixed• Body acts like second gate• This is called body effect
• Transconductance terms required to model transistor:– Transconductance associated with the main gate (gm)– Transconductance associated with the body or second gate (gmb)
– HereBS
tDStGS
BS
Dmb V
VVVVL
WkVIg
∂∂
+−−=∂∂
= )1)((' λ
SBt
SBfBS
tfSBftt
VtrwVofchangeratetheisHere
VVVVVV
...,
22)22(0
χ
χφγφφγ −=+
−=∂∂
⇒−++=
)1()(2
2'
DStGSD VVVL
WkI λ+−=
22
Including Non Ideal Behavior in Small Signal Model• Transconductance terms required to model transistor:
– Therefore, transconductance associated with the body or second gate (gmb) can be expressed as:
– The ratio gmb/gm is an important quantity:
)2(2)/(
22))(/(
1
22)1)()(/(
''
'
SBf
D
SBf
tGSmb
DS
SBf
DStGSmb
VILWk
VVVLWkg
VIf
VVVVLWkg
+=
+−
=
<<
++−
=
φγ
φγ
λ
φλγ
3.01.0
22
−
=+
=
ofrangetheintypicallyofvalueThe
Vgg
SBfm
mb
χ
χφγ
23
Including Non Ideal Behavior in Small Signal Model• Parasitic Elements in Small Signal Model
– Source-body junction capacitance (Csb)– Drain-body junction capacitance (Cdb)
• Here Csb0 and Cdb0 are the source-body and drain-body junction capacitance when VSB and VDB are 0.\
• ψ0 is the built in potential of the junction– Gate-body capacitance (Cgb)
• It models parasitic oxide capacitance between gate contact material and the substrate outside the active device area
• It models coupling from polysilicon and metal interconnects to the substrate– Gate-drain capacitance (Cgd)
• Although this component is considered zero for saturation region, there will be a component due to overlap capacitance between gate and drain
2/1
0
02/1
0
0
11 ⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
ψψDB
dbdb
SB
sbsb
V
CCandV
CC
24
Including Non Ideal Behavior in Small Signal Model• After Including all the parasitic elements small signal model for MOS transistor
will be as shown below:
25
Reference Books
• Analysis and Design of Analog Integrated Circuits (4th Edition) (Hardcover) by Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer
• VLSI Design Techniques for Analog and Digital Circuits (Mcgraw-Hill Series in Electrical Engineering) by R.L. Geiger, P.E. Allen and N.R. Strader, McGraw-Hill, 1990 (ISBN 0-07-023253-9)
