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EE141 EECS141 1 Lecture #3
EE141 EECS141 2 Lecture #3
Discussions start this week (Tomorrow) TA office hours will be held in 514 Cory Labs start next week
Everyone should have an EECS instructional account You should have card key access to 353 Cory be now
Concerns about discussion session Homework #1 is due this Friday Homework #2 to be posted on Friday
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EE141 EECS141 3 Lecture #3
Last lecture Basic metrics for IC design (Started)
Today’s lecture Metrics Continued Design Rules
Reading (1, 2.2, A)
EE141 EECS141 4 Lecture #3
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EE141 EECS141 5 Lecture #3 5
EE141 EECS141 6 Lecture #3
Undefined Region
Noise margin high: NMH = VOH – VIH
Noise margin low: NML = VIL – VOL
Gate Output
Gate Input
NML
NMH
“0”
“1”
VOL
VOH
VIL
VIH
(Stage M) (Stage M+1)
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EE141 EECS141 7 Lecture #3
Absolute noise margin values are not the only things that matter e.g., floating (high impedance) nodes are more
easily disturbed than low impedance nodes (in terms of voltage)
Noise immunity (i.e., how well the gate suppresses noise sources) needs to be considered too
Summary of some key reliability metrics: Noise transfer functions & margin (ideal: gain = ∞, margin =
Vdd/2) Output impedance (ideal: Ro = 0) Input impedance (ideal: Ri = ∞)
EE141 EECS141 8 Lecture #3
Logic Module In Out
delay
How to define delay in a universal way?
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EE141 EECS141 9 Lecture #3
EE141 EECS141 10 Lecture #3
Want a way to characterize the delay of a circuit (roughly) independent of environment
Most common metric: Delay of an inverter driving four copies of itself (tFO4)
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EE141 EECS141 11 Lecture #3
Important model – matches delay of an inverter
tp = ln (2) τ = 0.69 RC
EE141 EECS141 12 Lecture #3
Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)
Peak power: Ppeak = Vsupplyipeak
Average power:
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EE141 EECS141 13 Lecture #3
Want low power and low delay, so how about optimizing the product of the two? So-called “Power-Delay Product”
Power·Delay is by definition Energy Optimizing this pushes you to go as slow as
possible
Alternative gate metric: Energy-Delay Product EDP = (Pav·tp)·tp = E·tp
EE141 EECS141 14 Lecture #3
The voltage on CL eventually settles to VDD
Thus, charge stored on the capacitor is CLVDD This charge has to flow out of the power supply
So, energy is just Q·VDD = (CLVDD)·VDD
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EE141 EECS141 15 Lecture #3
EE141 EECS141 16 Lecture #3
Understanding the design metrics that govern digital design is crucial Cost Robustness Performance/speed Power and energy dissipation
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EE141 EECS141 17 Lecture #3
EE141 EECS141 18 Lecture #3
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EE141 EECS141 19 Lecture #3
EE141 EECS141 20 Lecture #3
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EE141 EECS141 21 Lecture #3
(well contacts)
EE141 EECS141 22 Lecture #3
Interface between designer and process engineer
Guidelines for constructing process masks Unit dimension: Minimum line width
scalable design rules: lambda parameter absolute dimensions (micron rules)
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EE141 EECS141 23 Lecture #3
Intra-layer Widths, spacing, area
Inter-layer Enclosures, distances, extensions,
overlaps Special rules (sub-0.25µm)
Antenna rules, density rules, (area)
EE141 EECS141 24 Lecture #3
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EE141 EECS141 25 Lecture #3
EE141 EECS141 26 Lecture #3
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EE141 EECS141 27 Lecture #3
EE141 EECS141 28 Lecture #3
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EE141 EECS141 29 Lecture #3
EE141 EECS141 30 Lecture #3
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EE141 EECS141 31 Lecture #3
• Dimensionless layout entities • Only topology is important
EE141 EECS141 32 Lecture #3
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EE141 EECS141 33 Lecture #3
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Polysilicon In Out
V DD
GND
PMOS 2λ
Metal 1
NMOS
Contacts
N Well
EE141 EECS141 34 Lecture #3
Connect in Metal
Share power and ground
Abut cells
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EE141 EECS141 35 Lecture #3
From simple to more complex gates …
