LED Cost and Technology Trends: How to enable … to enable massive adoption in general lighting ......

© 2011• 1Copyrights © Yole Développement SA. All rights reserved.


LED Cost and Technology Trends: How to enable massive adoption

in general lightingSEMICON West 2011

Moscone Center, San Francisco – June 13th 2011

45 rue Sainte Geneviève, F-69006 Lyon, FranceTel: +33 472 83 01 80 - Fax: +33 472 83 01 83

Web: http://www.yole.fr

Lumileds OSRAM OKI OSRAMAixtron OSRAMCREELumileds


Content

• Rationale: why are cost reductions necessary?• LED die singulation.• Packaging substrates• Conclusion

Semicon West 2011


Packaged LED: Revenue by Application(Base Scenario)

?

Sources: Yole Développement

General Lighting to take off only if cost/performance can beat incumbent technologies.

Semicon West 2011


Upfront Cost:

Sticker Shock:

<$1 $3-5 $40

All sources: ~ 800 lumensWarm WhiteTier 1 brand

Need to reduce $/lumen !

Semicon West 2011


Cumulated Cost of Light =

Upfront Cost+

Energy Cost+

Maintenance Cost

Semicon West 2011


Cumulated Cost: Examples

$40 LED Bulb:LED cumulated cost remains higher than Fluorescent light sources

Standard A19 Warm white Bulb800 lumen

No maintenance cost (residential use)


Semicon West 2011


Cumulated Cost: Examples

$10 LED Bulb:LED becomes significantly cheaper than other light source + upfront cost more

acceptable trigger for massive market adoption


Semicon West 2011


The Path to Cost Reduction

Cost = $/Lumen

LED performance:• Higher Efficiency (lumen/W)• More light per chip

Manufacturing Efficiency:• Higher equipment throughput• Higher yields• Economy of scale

Semicon West 2011


Testing and Binning: Wafer Level, Higher throughputs

Encapsulation Materials and Optics:

Ageing and optical properties

20 Key Technologies & Research AreasRelative Impact on LED cost of ownership

Contacts/Electrodes:Transparent

contacts/Electrode materials and patterns

Contacts & Electrodes:

p to n layer VIAS

Epitaxy – MOCVD: Higher yields and

Throughputs - Improved Material quality

Epitaxy: Cluster tools - New Epi Technologies

Wafer Level Packaging:

Silicon TSV, Wafer Level Optics

Lithography: Dedicated tools,

Higher Throughput

Mirrors: Improve reflectivity/electrical

properties

Mirrors:Resonant Cavities

Phosphors: Conversion efficiency, Color Rendering – “IP

free” phosphors

Phosphors: Quantum dots

Phosphors

Die SingulationIncreased

throughputs and yields

Substrate Separation: Laser Lift Off, other separation

techniques

Thermal Management: New materials for packaging

LED Performance

Manufacturing Cost

Surface Texturation: Patterned substrates /

Roughening

Surface Texturation: Photonic and Quasi Photonic Crystals

Current Droop / Green Gap /

LED Structures

Alternative substrates

#2: Si Large Diameters

Substrates: 4”, 6”, 8”

Alternative substrates #1:

GaN, ZnO, Si, Engineered substrates


Semicon West 2011


Typical Process Flow:

Epiwafer

Carrier wafer

Epitaxial substrate

Die

Lens

Semicon West 2011

Carrier wafer

Each step represents an opportunity for cost improvement


Typical Process Flow:

Die

Semicon West 2011

Die


LED Singulation:4 different processes can be used for LED die singulation:

LED Epiwafer

Blade Dicing

Diamond Scribing

Scribed Epiwafer

LED dice

Laser Scribing

Breaking

Laser Dicing

Dicing Process

Scribe & Break

1)

2)

3)

4)

Semicon West 2011


Dicing and LED Cost

• Critical Parameters:– Reducing street width increase die/wafers count.– Cutting speed increase equipment throughput– Cutting yields good die per wafers– Performance some processes reduce brightness: lower

die value

Picture: JPSA

Picture: A.L.S.I

Street Width

Kerf LossPicture: JPSA

Scribing Depth

Semicon West 2011


Improving Throughput:

Scribe depth versus scribe speed for a 266nm laser using 1W average power at

30kHz (source: Oxford Lasers)

Materials:• GaN• Sapphire• GaAs• SiC• Si, Ge• Cu, CuW, Mo…

Scribing depth: Indexing speed:

Main Factors influencing Dicing Speed:

Vertical LED chip bonded on metal substrate

Recasting effect on metal after laser scribing

Trade off between speed and depth

Indexing / alignment times are critical to

throughput

Semicon West 2011


Increasing Speed (1): Serial Multibeam Laser Dicing

• Increasing laser dicing speed requireshigher laser energy: damages the components.

• Solution: Serial Multibeams

1st pulse nth pulse

Wafer

Laser Beams

Illustration of Multibeam laser dicing process (source: ALSI)

Multibeam vs. high energy single beam (right) beam splitting technique (ALSI)

Diffractive Optical Element

Expander

Side view of a 650 um thick GaAs wafer scribed with a mutibeam laser (ALSI)

Semicon West 2011


Increasing Speed (2): Parallel cuts

• Due to high alignment and indexing time, increasing the scribing speed has a comparatively limited impact on system throughput:

x6

x2

Comparison of wafer throughput vs. scribing speed:

Hypothesis: 2” wafer, 350 um die, 20 um street width.

Results: a 6x speed increase would lead to a 2x improvement in wafer throughput:

Source: Yole0

1

2

3

4

5

6

7

50 100 150 300

Incr

ease

fact

or

Scribing Speed (mm/s)

Speed increaseWafer Throughput increase

Speed (mm/s) 50 100 150 300

Wafer/hour 9 13 15 18

• For small die sizes, significant throughput improvementsare possible with parallel cuts systems.• Mechanical: Dual Spindle (available)• Laser: Multibeam (coming soon) Concept for a parallel multibeam

scribing system

Semicon West 2011


Reducing Street Width: Stealth dicing

Process overview (Hamamatsu photonics)

Wafer

Sapphire breaking after stealthdicing (Disco)• Drawbacks:

– Higher capital cost.– Despite the name “dicing”, a breaking step is still required for LED due to the small die size.– Not available for all materials. Si and Sapphire OK.

Short-pulse, high-power laser beam weakens the material under the surface wafer is diced “from the inside”

• Benefits:– Much reduced kerf loss small street width– No debris on wafer or contamination on the optics– Clean edges: little/no loss in brightness

Semicon West 2011


Alternative Die Singulation Method: Etching

• Startup “Verticle” developed hexagonalshaped LED chips:

– Improved current spreading– Almost circular beam profile– Increased die count

• Die separation is achieved by chemicaletching after removal of the initialsapphire substrate

• Allows the processing of multiplewafers simultaneously.

Honeycomb chips before separation ( Top) and SEM

Image of separated chip (Bottom).

Singulated chips

Semicon West 2011


Singulation: Conclusions

• Tremendous growth of laser based dicing since 2005: high capital costbut high throughput.

• Laser solutions keep improving are not (yet?) suitable for allstructures/materials.

• Choice is application/material dependent and made on a case by casebasis.

Singulation techniques improving constantly to respond to newchallenges and reduce LED manufacturing cost down.

Semicon West 2011


Performance: Package Substrate

Die

Semicon West 2011


LED Thermal Management: Why?

• LED: up to 40% of the of the energy turned into heat!

Source: Osram

Electric Loss

Quantum Loss

Light Extraction Loss

• LED DON’T like heat, performance decrease:• Brightness, Efficiency• Lifetime• Color stability

Semicon West 2011


Thermal Management

Stay cool!

Semicon West 2011


Thermal ManagementMain design options for high power LEDs (≥1 W)

LED Die

Substrate OnlySi Submount

Substrate

Heat slug Ceramic Silicon(Wafer Level Packaging)

Organic / Heat slug Ceramic

PCB / MCPCB

Optek Lednium Lumileds Luxeon Rebel Viscera Technology Lumileds Luxeon Cree-X-lamp

Semicon West 2011

Chi

p on

Boa

rd

MCPCB


Single Large Die

(1 die, typical dimension: 0.5 to 1.5 mm)

High-Power LED PackagesExamples

Single or Multi “Jumbo Die”

1 to 6 dice, typical dimension 2 to 5 mm each)

Small/medium dice Array

(20 to 100 dice, typical dimension: 250 to 500 um each)

Lumileds

Lumileds

Osram

Cree

Cree

Osram

Osram

LuminusDevice

LuminusDevice

LuminusDevice

Multiple Large Dice

(3 to 25 dice, typical dimension: 0.5 to 1.5 mm each)

Edison Opto

Semicon West 2011


Solder / Metallization

Packaging of an LED at wafer level, rather than assembling the package of each individual unit after wafer dicing.

1) Wafer level preparation of the package substrate

2) Chip to wafer 3) Wafer level interconnect, phosphor deposition, encapsulation, optic.

4) LED package separation.

Packaging wafer

LED wafer

LED die

Mirror coating

Solder Bump

PhosphorWafer Level Optic

Overview of Chip to Wafer LED WLP process

Wafer Level Packaging (WLP):

Wafer Level Packaging

Note: in this example, the LED chips are singulated before being positioned onto the package wafer (=“Chip to Wafer” packaging)

Semicon West 2011



Hymite (technology acquired by Touch Microsystem Technology in 2010)

Courtesy of Hymite

Semicon West 2011



Silicon Base Development IncSilicon Base Development Inc VisEra TechnologyVisEra Technology

Pictures: Company

Pictures: Company, System Plus consulting

Semicon West 2011


WLP operations for high power LEDs

Many LED packaging operations could be carried out at the wafer level:

3D Siliconsubstrates

Embedded Zener diodes

Wafer levelPhosphor

coating

Wafer levelOptics

Bumping atthe wafer level

Wafer to wafer bonding (LED on package substrate)

Wafer levelcoating of

reflective layer

Semicon West 2011

WLP operations for

High Power LEDs


• Wafer Level Manufacturing: cost effective.• …but: Copper-filled TSVs for 3D electrical

redistribution and heat dissipation are still expensive.

• So far only for high performance LEDs• Other options: WLP on ceramic substrates.

Silicon Substrates and WLP

EMC3D TSV Cost of ownership roadmap (courtesy: EVG / EMC3D)

• Silicon: thermal conductivity, further improved by the use of copper-filled Through Silicon Vias (TSV)

• Reliability: monolithic assembly, reduced wire interconnect, good CTE match with GaN• Wafer level testing

Benefits:Benefits:

Cost:Cost:

Semicon West 2011


High Power LED SubstrateMarket Penetration Forecast by substrate type

Yole Développement ©

Note: technology adoption rates for High Power (>1W) LED package only

Semicon West 2011


Conclusion: The Path to Cost Reduction

• Lack of standards: Technology choices application and manufacturer dependent.

• 10x cost reduction in packaged LEDs cost? Not easy but achievable through a combination of: Technology improvements: efficiency + more lumens per chip.

Manufacturing improvements: dedicated LED tools, automation, inline testing.

Economies of scale

Higher integration

Standardization

LED industry maturing and reaching critical mass to enable development of dedicated tools. Semiconductor “veteran” companies bring additional

expertise and “best practices”.

Semicon West 2011

Date post:	28-May-2018
Category:	Documents
Upload:	doankhanh
View:	215 times
Download:	0 times

LED Cost and Technology Trends: How to enable … to enable massive adoption in general lighting ......

Documents