Logic Options Logic

Standard Cells Custom

PLAs

Standard Logic

ASIC Programmable Logic

Gate Arrays

SPLDs CPLDs FPGA

PALs

Programmable Logic Arrays (PLAs)

Any combinational logic function can be realized as a sum of products.

Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. n inputs

AND gates have 2n inputs -- true and complement of each variable

m outputs, driven by large OR gates Each AND gate is “connected” to each output's OR gate.

p AND gates (p<<2n)

PLA - general structure

Ex: 4x3 PLA, 6 product terms

* gate level diagram

PLA - Customary Schematic

PLA - Example

Programmable Array Logic (PALs)

Idea: How beneficial is product sharing? not enough to justify the extra OR array

PALs ==> fixed OR array each AND gate is permanently connected to a

specific OR gate. simpler to manufacture,

less expensive, better performance

PAL - Customary Schematic

PAL - Example PAL16L8

PAL - Example PAL16L8

10 primary inputs 8 outputs, with 7 ANDs per output 1 AND for tri-state enable 6 outputs available as inputs

more inputs, at expense of outputs two-pass logic, helper terms

Note inversion on outputs output is complement of sum-of-products newer PALs have selectable inversion

Designing with PALs

Compare number of inputs and outputs of the problem with available resources in the PAL.

Write equations for each output using ABEL. Compile the ABEL program. Determine whether minimized equations fit in

the available AND terms. If no fit, try modifying equations or providing

“helper” terms.

How to expand PLD architecture? Increase # of inputs and outputs in a SPLD?

e.g., 16V8 --> 20V8 --> 22V10. Why not --> 32V16 --> 128V64 ?

Problems: n times the number of inputs and outputs requires n2

as much chip area -- too costly logic gets slower as the number of inputs to the AND

array increases Solution:

multiple PLDs on one chip with a relatively small programmable interconnect

Less general than a single large PLD, but can use software “fitter” to partition into smaller PLD blocks.

CPLD families Identical individual PLD blocks (Xilinx “FBs”)

replicated in different family members. Different number of PLD blocks Different number of I/O pins

Many CPLDs have fewer I/O pins than macrocells “Buried” Macrocells -- provide needed logic terms

internally but these outputs are not connected externally.

IC package size dictates # of I/O pins but not the total # of macrocells.

Typical CPLD families have devices with differing resources in the same IC package.

Complex Programmable Logic Device

Structure of a CPLD: Small number of PLDs (e.g., “36V18”) on a single chip Programmable interconnect between PLDs

CPLD - section detail

Field-Programmable Gate Array Historically, FPGA and CPLD architectures

began around the same time FPGAs are closer to “programmable ASICs”

-- large emphasis on interconnection routing Timing is difficult to predict -- multiple hops vs. the

fixed delay of a CPLD's switch matrix. But more “scalable” to large sizes.

FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD.

Field-Programmable Gate Array Much larger number of smaller programmable logic blocks. Surrounded by programmable interconnect.

FPGA - Lookup Tables

FPGA - example

Problems: CPLDs/FPGAs Pin locking

Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pin out.

Locking too early may make the resulting circuit slower or not fit at all.

but must lock to prevent redesign of PCB due to minor logic changes late in design process

Running out of resources

Design may “blow up” if it doesn't all fit on a single device. On-chip interconnect resources are much richer than off-

chip; e.g. barrel-shifter example. Larger devices are exponentially more expensive.

Custom Chips

ASIC - Application Specific Integrated Circuit Largest # gates and highest speed Custom chip layout Large design effort >> expensive must sell in sufficient quantities e.g. memory, microprocessors

Standard Cells Rows of logic gates separated by routing

channels

Gate Array Technology Part of the chip is prefabricated, other

parts are custom fabricated

Gate Array Technology - example