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LOGIC SYNTHESIS FOR LOW POWER VLSI DESIGNS
LOGIC SYNTHESIS FOR LOW POWER VLSI DESIGNS
LOGIC SYNTHESIS FOR LOW POWER VLSI DESIGNS
by
Sasan Iman Escalade Co.
& University of Southern California
and
Massoud Pedram University of Southern California
... " SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4613-7490-9 ISBN 978-1-4615-5453-0 (eBook) DOI 10.1007/978-1-4615-5453-0
Copyright © 1998 Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1998 Softcover reprint of the hardcover 1 st edition 1998 AlI rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photocopying, record ing, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC .
Printed an acid-free paper.
To our loving families.
Contents
Preface xiii
Acknowledgments xv
I Background, Terminology, and Power Modeling 1 1 Introduction 3
1.1 Low Power Design Methodology ................................ 5
1.2 Logic Synthesis for Low Power .................................. 7
1.3 Sources of Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
1.4 Physical Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12
1.5 Switching Activities .......................................... 12
1.5.1 Delay model ........................................ 12 1.5.2 Computing switching activities ............................ 13
1.6 Models, Algorithms and Methodologies . . . . . . . . . . . . . . . . . . . . . . . . .. 15
1.7 Outline of the Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17
2 Technology Independent Power Analysis and Modeling 21 2.1 Power Modeling Overview .................................... 21
2.2 Preliminaries and Definitions .................................. 24
2.2.1 Computing switching activities ............................ 24 2.2.2 Power consumption vs. power contribution .................. 24 2.2.3 Load estimation ....................................... 25
2.3 Signal Tracing for Power Analysis .............................. 26
2.3.1 Born-again nodes ...................................... 28 2.3.2 Tracing the load on signals ............................... 29 2.3.3 Power analysis using tracing information .................... 30 2.3.4 Observations ........................................ 31
2.4 Power Models for Node Functions .............................. 31
2.5 Technology Independent Power Model .......................... 33
1/ Two-level Function Optimization for Low Power 41
3 Two-Level Logic Minimization in CMOS Circuits 43 3.1 Power Model for Two-Level Static CMOS Logic .................... 45
3.2 Exact Minimization Algorithms ................................. 46
3.3 Power Prime Implicants ...................................... 47
3.4 Generating the Set of all PPls .................................. 48
3.5 Exact Minimization Algorithm for Low Power ...................... 52
3.6 Upper Bounds on the Expected Number of PPls ................... 52
3.6.1 Implicant signal probabilities as random variables ............. 53 3.6.2 Upper bounds on the number of generated PPls . ............. 55
3.7 Exact Function Minimization for Low Power ....................... 61
3.8 Experimental Results ........................................ 63
4 Two-Level Logic Minimization in PLAs 69 4.1 Power Model for PLA Logic Implementation ....................... 71
4.2 Prime implicants and PLA Power Optimization ..................... 74
4.2.1 Pseudo-NMOS PLA .................................... 74 4.2.2 Dynamic-CMOS PLA ................................... 77
4.3 Two Level Function Minimization ............................... 78
4.3.1 Area optimization ...................................... 79 4.3.2 Power optimization ..................................... 80
4.4 Experimental Results ........................................ 82
11/ Multi-level Network Optimization for Low Power 85 5 Logic Restructuring for Low Power 87
5.1 Algebraic Logic Restructuring .................................. 88
5.2 Common Sub-Expression Extraction ............................ 89
5.2.1 Cube and kernel extraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2.2 Kernel extraction targeting low power. ...................... 90 5.2.3 Cube Extraction Targeting Low Power ...................... 95 5.2.4 Quick power extract .................................... 96
5.3 Function Factorization ........................................ 97
5.3.1 Maximally factored logic expressions ....................... 97 5.3.2 Factorization for low power ............................... 97
5.4 Expression Substitution ..................................... 101
5.5 Selective Collapse ......................................... 102
5.6 Experimental Results ....................................... 103
viii
6 Logic Minimization for Low Power 109 6.1 Power Relevant Don't Care Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.1 Don't care conditions for area. . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.1.1 Computing Don't Care Conditions . . . . . . . . . . . . . . . . . . . 112
6.1.2 Observability don't care conditions for power ................ 114 6.1.3 Observability don't care analysis for power optimization ....... 116
6.1.3.1 Observability don't care analysis for tree networks ...... 116 6.1.3.2 Observability Don't Care Regions ................... 118 6.1.3.3 Using Don't Care Regions in Node Optimization ........ 120
6.1.4 Power relevant observability don't cares for power optimization . 124 6.1.5 Monotonic reduction in global power ...................... 127 6.1.6 Computing power relevant don't cares in DAGs .............. 130 6.1.7 Power relevant satisfiability don't cares for power optimization .. 131
6.2 Node Minimization using Minimal Variable Supports ............... 134
6.2.1 Minimal supports of functions ............................ 134 6.2.1.1 Minimal Literal Supports ........................... 134 6.2.1.2 Reduced Off-sets and Minimal Literal Supports ......... 137 6.2.1.3 Minimal Variable Supports ......................... 139
6.2.2 Node minimization using minimal variable supports ........... 140 6.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7 Technology Dependent Optimization for Low Power 149 Chi-ying Tsui Hong Kong University of Science and Technology
7.1 Technology Dependent Phase of Logic Synthesis ................. 150
7.1.1 prior work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.1.2 Calculation of signal and transition probabilities. . . . . . . . . . . . . . 152
7.2 Low Power Technology Decomposition ......................... 153
7.2.1 Tree decomposition ................................... 154 7.2.2 Bounded-height tree decomposition ....................... 159
7.3 Low Power Technology Mapping .............................. 161
7.3.1 Terminology ....................................... 162 7.3.2 Arrival time and power cost calculation .................... 164 7.3.3 Tree mapping ....................................... 165
7.3.3.1 Postorder traversal ............................... 166 7.3.3.2 Preorder traversal. ............................... 166 7.3.3.3 Timing recalculation .............................. 166 7.3.3.4 Optimality of the tree mapping algorithm .............. 167
7.3.4 DAG mapping ....................................... 167 7.3.5 Experimental results ................................... 168 7.3.6 Discussion on using real delay model ..................... 174 7.3.7 Extension to consider signal correlation at the primary inputs ... 175
ix
7.4 Power Reduction after Technology Mapping ..................... 176
7.4.1 Gate resizing ....................................... 177 7.4.1.1 Timing calculation ................................ 177 7.4.1.2 Gate re-sizing algorithm ........................... 178 7.4.1.3 Experimental results .............................. 179
8 Post Mapping Structural Optimization for Low Power 183 8.1 Signal Substitution ......................................... 184
8.2 Candidate Wire Generation .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
8.3 Cost functions ..................... . . . . . . . . . . . . . . . . . . . . . . 187
8.4 Function Substitutions ....................................... 188
8.4.1 Computing ODCs ..................................... 189 8.4.2 Increasing number of candidate substitute wires ............. 190 8.4.3 Functional simulation to speed up optimization .............. 191
8.5 Experimental results ........................................ 192
IV Power Optimization Methodology 197 9 POSE: Power Optimization and Synthesis Environment 199
(http://atrak.usc.edu/-pose)
9.1 Low Power Design Methodology .............................. 201
9.2 Design Specification for Power ................................ 204
9.2.1 Input Switching Activity ................................. 205 9.2.2 Library Load Values ................................... 205
9.3 Power Estimation .......................................... 207
9.3.1 Computing power under a zero-delay model ................ 207 9.3.1.1 Speed/accuracy trade-offs ......................... 207 9.3.1.2 Computing signal probabilities using semi-local BODs .... 208
9.3.2 Computing switching activities under a real-delay model ....... 209 9.3.3 Effect of optimization on switching activities ................. 210
9.4 Power Estimation Flow ...................................... 211
9.5 Experimental Results ....................................... 214
V Conclusion 225 10 Concluding Remarks 227
10.1 Conclusions ........................................... 228
10.1.1 Two-Level Logic Minimization in CMOS Circuits ............ 228 10.1.2 Two-Level Logic Minimization in PLAs ................... 228 10.1.3 Logic Restructuring for Low Power ...................... 228
x
10.1.4 Logic Minimization for Low Power ....................... 229 10.1.5 Technology Dependent Optimization for Low Power ......... 229 10.1.6 Post Mapping Structural Optimization for Low Power ........ 229 10.1.7 POSE: Power Optimization and Synthesis Environment ..... 230
10.2 Future Directions .......................................... 230
10.2.1 Area-Power Trade-Offs ................................ 231 10.2.2 Delay-Power Trade-Offs ............................... 231
Index 233
xi
Preface
In the past, the major concerns of the VLSI designers were area, speed, cost, and reliability. In recent years, however, this has changed and, increasingly, power is being given comparable weight to area and speed. This is mainly due to the remarkable success of personal computing devices and wireless communication systems, which demand high-speed computation and complex functionality with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under control. The main driving factors for lower power dissipation in these products are the costs associated with packaging and cooling, and circuit reliability.
Although some low power design techniques can be applied manually, the complexity of today's chips is such that tools for hierarchical design capture and automatic design of low-power VLSI circuits are mandatory. The low power design challenge is one that requires abstraction, modeling and optimizations at all levels of design hierarchy, induding the technology, circuit, layout, logic, architectural, and algorithmic levels. Combining optimizations at all these levels easily results in orders of magnitude of power reduction. Such impressive reduction in circuit power will however be possible only if optimization flows and techniques at each level of design hierarchy are developed.
Logic synthesis has matured as a field to be universally accepted and used in every major IC design and production house worldwide. A wealth of research results and a few pioneering commercial tools for low power logic synthesis have appeared in the last couple of years. It is our experience that optimization at the logic (gate) level provide 50-70% power reduction without sacrificing the circuit speed.
A systematic and comprehensive treatment of power modeling and optimization at logic level is lacking today. It is the intention of the present book to occupy this niche area. More precisely, this book provides a detailed presentation of me tho dologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. The book contains detailed descriptions of technology-independent logic transformations and optimizations, technology dec om-
position and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Much of the algorithms described in this book have been implemented and released as part of the POSE package. Interested readers may obtain a copy of the POSE program from the following site: http://atrak.usc.edul-pose . We expect this field to remain active in the foreseeable future. New trends and techniques will emerge, some approaches described in this book will solidify, while others will be improved on; this in view of technological and strategic changes in the world of microelectronics.
The book is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis. Emphasis is given to top-down structured design flow for ASICs. Examples and benchmark results are presented to qualitatively and quantitatively assess the effectiveness of various point tools and techniques used in the overall design flow. The book can also be used as a textbook for teaching an advanced course on low power logic synthesis. Instructors can select various combinations of chapters and augment them with some of the many references included at the end of each chapter and material selected from a standard textbook on logic synthesis (such as the book by Gary D. Hachtel and Fabio Somenzi on Logic Synthesis and Verification Algorithms published by Kluwer Academic Publishers).
We hope that this book will serve as the reference for logic-level power modeling and optimization and will be complemented in the future by similar books written on physical design and system-level design for low power.
Sasan Iman, Santa Clara, California Massoud Pedram, Los Angeles, California September 1997
xiv
Acknowledgments
The work described in this book is part of an on-going research project at the University of Southern California to develop power-savvy design methodologies and tools for effective power analysis and optimization at RT and logic levels. The project is named POSE which stands for Power Optimization and Synthesis Environment.
We would like to acknowledge a number of colleagues and Ph.D. students involved in this project. Specifically, we thank Chi-ying Tsui for the insightful discussions on power optimization techniques for PLA designs. He also developed the algorithms for technology mapping and decomposition and gate re-sizing as described in chapter 7. Designing and implementing the POSE system was a challenging part of this work. Special thanks go to Chih-Shun Ding and Chun-Li Pu for contributing to the system development.
The weekly seminars organized by the USC Low Power CAD group was instrumental in providing the necessary forum for identifying research challenges and putting new ideas to test. Special thanks go to all members of the group, present and past, whose hard work, academic excellence and diligent participation, were essential in sustaining this research forum. We would like to thank Jui-Ming Chang, Cheng-Ta Hsieh, Yung-Te Lai, Jaewon Oh, Bahman Salehi Nobandegani, Kuo-Rueih Ricky Pan, Diana Marculescu, Radu Marculescu, Amir Shaygan Salek, Hirendu Vaishnav, and Qing Wu.
The research described in this book was sponsored in part by DARPA under contract number F33615-95-C1627, by SRC under contract number 94-DJ-559, and by NSF NYI and PECASE awards.
