Low-Noise Amplifier.ppt

8/10/2019 Low-Noise Amplifier.ppt

1/115

1

Low-Noise Amplifier


2/115

2

RF Receiver

BPF1 BPF2LNA

LO

Mixer BPF3 IF Amp

Demodulator

Antenna

RF front end


3/115

3

Low-Noise Amplifier

First gain stage in receiverAmplify weak signal

Significant impact on noise performance

Dominate input-referred noise of front end

Impedance matching

Efficient power transfer Better noise performance

Stable circuit

LNA

subsequent

LNAfrontendG

NFNFNF

1


4/115

4

LNA Design Consideration

Noise performance

Power transfer

Impedance matching

Power consumption

Bandwidth

Stability Linearity


5/115

5

Noise Figure

Definition

As a function of device

G: Power gain of the device

outout

inin

out

in

NS

NS

SNR

SNRNF

source

sourcedevice

NG

NGNNF


6/115

6

NF of Cascaded Stages

Overall NF dominated by NF1

[1] F. Friis, Noise Figure of Radio Receivers,

Proc. IRE, Vol. 32, pp.419-422, July 1944.

Sin/Nin

G1, N1,

NF1

Gi, Ni,

NFi

GK, NK,

NFK

Sout/Nout

12121

3

1

21

11111

K

K

...GGG

NF...GG

NF

G

NFNFNF


7/1157

Simple Model of Noise in MOSFET

fWLC

k

fVox

g )(

2

Flicker noise Dominant at low frequency

Thermal noise

g: empirical constant2/3 for long channel

much larger for short channel

PMOS has less thermal noise

Input-inferred noise

md gkTfI g4)(2

Vg

Id

Vi

fWLC

k

gkTfV

oxm

i g

4)(2


8/1158

Noise Approximation

Thermal noise

1/f noise

Band of interestFrequency

Noise spectral

density

Thermal noise

dominant


9/1159

Power Transfer and Impedance Matching

L

LLss

sdel R

jXRjXR

VP

2

s

ss

XXRRL R

VVPP

LsLs 4

*

0,max

Power delivered to load

Maxim available power

Rs

Vs

jXs jXL

RLI V

Impedance matching Load and source impedances conjugate pair

Real part matched to 50 ohm


10/11510

Available Power

Equal power on load

and source resistors


11/11511

Reflection Coefficient

***

max4

))((4

aaR

IZVIZVRVVP

s

ss

s

ss

s

s

R

IZVa

2

****

max4

))((bb

R

ZIVIZVPPP

s

ssdelref

Rs

Vs

jXs jXL

RLI V

s

s

R

IZVb

2

*

sL

sL

ZZ

ZZ

a

b

*

2

)( ** LLdel

ZZIIP

LIZV


12/11512

Reflection Coefficient

No reflection

Maximum power transfer


13/11513

S-Parameters

Parameters for two-port system analysis Suitable for distributive elements

Inputs and outputs expressed in powers

Transmission coefficients Reflection coefficients


14/11514

S-Parameters

2221212

2121111

aSaSb

aSaSb

a1

b1

b2

a2

S11

S12

S22

S21


15/115

15

S-Parameters S11input reflection coefficient with

the output matched

S21forward transmission gain or

loss

S12reverse transmission or

isolation

S22output reflection coefficient with

the input matched012

222

012

112

021

221

021

111

a

a

a

a

abS

a

bS

a

bS

abS


16/115

16

S-Parameters

SZ1 Z2

Vs1 Vs2

I1

V1

I2

V2

0222

*

22222

01

2

222

*

11112

02

1

111

*

22221

0111

*

11111

11

22

)Re(

)Re(

)Re(

)Re(

ss

ss

VV

VV

ZIV

ZIVS

Z

Z

ZIV

ZIVS

Z

Z

ZIV

ZIVS

ZIV

ZIVS


17/115

17

Stability Condition

Necessary condition

where

Stable iff

where

1||2

||||||1

2112

22

11

2

22

SS

SSK S

21122211 SSSSS

1|| 2 LLS

2

||||||

2

22

2

112112

SSSSL


18/115

18

A First LNA Example

Assume

No flicker noise

ro= infinity

Cgd = 0 Reasonable for appropriate

bandwidth

Effective transconductance

Rs

Vs

Vs

Rs 4kTRs

VgsgmVgs 4kTggm ins

inm

s

omeff

ZR

Zg

V

iG

io


19/115

19

Power Gain

Voltage input Current output

2

22

2

22

2

2

*

*

1

)(1

1)(1

)(1

||

s

T

gss

m

gss

m

gss

gsm

ins

inm

meffss

oo

RCR

g

CRj

g

CjR

Cjg

ZR

ZgG

VV

iiG


20/115

20

Noise Figure Calculation

Power ratio @ output

Device noise + input-induced noise

Input-induced noise

2

2

222

22

2

)/(1

)1(1

)(14

41

gsm

ms

ms

gss

ms

gss

ms

m

in

indevice

CggR

gR

CRgR

CRgkTR

gkT

NG

NGNNF

g

g

g

g

gs

mT

C

g


21/115

21

Unity Current Gain Frequency

Device ioutiin

1

Tin

Touti

in

outi

i

iA

i

iA

T

0dB

fT

Ai

ffrequency


22/115

22

Small-Signal Model of MOSFET

Cgs

Cgd

rds Cdb

Rg: Gate resistance

ri: Channel chargingresistance

Vgs

gmVgs

Cgdi1 i2

ri

Cgs

i1

i2

Cdb

rds

Rg

V1 V2

V1V2


23/115

23

TCalculation

gdgsiggsiggdgs

gdgsigdgs

V CCrRsCsrRCCs

CCrsCCs

V

IY

2

2

01

111

)(1

)(

2

Vgs

gmVgs

Cgdi1 i2

ri

CgsCdb

rds

Rg

V1

Vgs

gmVgs

Cgdi1 i2

ri

Cgs

Rg

V1

gdgsiggsiggdgs

gdgsigdgsim

V CCrRsCsrRCCs

CCrssCCsrg

V

IY

2

2

01

221

)(1

)1(

2


24/115

24

Tof NMOS and PMOS

0.25um CMOS Process*

[2] Tajinder Manku, Microwave CMOS - Device Physics and Design,

IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999.

mgdgsm

T gCC

g

1)(

)(

21

11 T

T

jY

jY

Set:

Solve for T


25/115

25

Noise Performance

Low frequency

Rsgm >> g~ 1

gm>> 1/50 @ Rs= 50 ohm

Power consuming

CMOS technology

gm/IDlower than other tech Tlower than other tech

2

2

1T

ms

msgRgRNF

g

g


26/115

26

Review of First Example

No impedance matching Capacitive input impedance

Output not matched

Power transfer S11=(1-sRCgs)/(1+sRCgs)

S21=2Rgm/(1+sRCgs), R=Rs=RL

Power consumption High power for NF

High power for S21


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27

Impedance Matching for LNA

Resistive termination Series-shunt feedback

Common-gate connection

Inductor degeneration


28/115

28

Resistive Termination

2

/1/1 gsIs

m

CjRR

gG

Current-current power gain

Noise figure

Rs

Vs Is Rs

4kT/Rs

VgsgmVgs

io

RI RI

4kT/RI 4kTggm

2

22

111

T

sm

Ism

s

I

s RgRRg

R

R

RNF

g

g


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29

Comparison with Previous Example

Previous example

Resistive-termination

2

22

11T

sm

I

s

smI

s RgR

R

RgR

RNF

g

g

2

2

1T

ms

ms

gRgR

NF

g

g

Introduced by input

resistance Signal attenuated


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30

Summary - Resistive Termination

Noise performance

Low-frequency approximation

Input matched Rs= RI= R

Broadband input match

Attenuate signal

Introduce noise due to RI

NF > 3 dB (best case)

RgNF m

g4

2


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31

Series-Shunt Feedback

Broadband matching

Could be noisy

Rs

VsRa

RF

RL

Vgs gmVgs

RFiout

Ra

Cgs

Rs

Vs

RL

gsLFaaLm

gsaamLF

inCRRRsRRg

CsRRgRRR

)()(1

)1)((

))((1

)(

))((1))(1(

asgsm

saFsFags

asgsm

sFamout

RRsCg

RRRRRRsC

RRsCgRRRgR


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32

Common-Gate Structure

Rs RL

Vs

Rs 4kTRs

VgsgmVgs

RL

4kTggm

Vs

Rs 4kTRs

Vgs gmVgs

RL

4kTggm

gmgsssm

m

s

outeff

CsRRgg

V

IG

1


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33

Input Impedance of CG Structure

Input impedanceYin=gm+sCgs

Input-impedance matching Low frequency approximation

Direct without passive components

1/gm=Rs=50 ohm


34/115

34

Noise Performance of CG Structure

2

2

2222

222

2

41

)1(1

)()1(4

41

T

gsssm

ms

gsssm

ms

m

in

indevice

CRRggR

CRRggkTR

gkT

NG

NGNNF

gg

g

g

222

22

)()1( gsssmm

effCRRg

gGG

Signal attenuated


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35

Power Transfer of CG Structure

Rs= RL= R = 50 ohm

S11=0, S21=1 @ Low frequency

gss

gss

gsssm

gsssm

sin

sin

CsR

CsR

CsRRg

CsRRg

ZZ

ZZS

2

1

1*

11

gs

gsssm

mLeffL

sC

CsRRg

gRGRS

2

2

1

2221


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36

SummaryCG Structure

Noise performance

No extra resistive noise source

Independent of power consumption

Impedance matching

Broadband input matching

No passive components

Power consumption

gm=1/50 Power transfer

Independent of power consumption


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37

Inductor Degeneration Structure

Rs

VsLs

Lg

Vgs gmVgs

iout

Cgs

Rs

Vs

Lg

Ls

Zin

Vin

iin

gs

sm

gs

sgin

sgs

inmings

ingin

sgsmin

gs

inginin

C

Lg

sCLLsI

sLsCIgIsCIsLI

sLVgIsC

IsLIV

1)(

)

1

(

1

)(1

Zin


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38

Input Matching for ID Structure

Zin=Rs

IM{Zin}=0

RE{Zin}=Rs

gs

sm

gs

sginCLg

sCLLsZ 1)(

gssg CLL )(

120

s

gs

sm RC

Lg

Vgs gmVgs

iout

Cgs

Rs

Vs

LgLs

Zin

gmLs/Cgs


39/115

39

Effective Transconductance

Vgs gmVgs

iout

Cgs

Rs

Vs

LgLsZin

gmLs/Cgs

)()(1

)(

2

sggssmgss

m

ins

gsm

s

outeff

LLCsLgCRsg

ZR

sCg

V

IG


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40

Noise Factor of ID Structure

Calculate NF at 0

22

22

2

)(1

)(4

41

0

smgss

ms

smgss

ms

m

in

indevice

LgCRgR

LgCR

gkTR

gkT

NG

NGNNF

g

g

2222

2

2

)()](1[ smgsssggs

meff

LgCRLLCgGG

= 0 @ 0


41/115

41

Input Quality Factor of ID Structure

CRRII

CII

powerLost

powerStoredQ

1*

*

Cgs

Rs

Vs

LgLs

gmLs/Cgs

C

R

V

L

gsssmgss

gssmsgs

in

CRLgCR

CLgRCCRQ

2

1

)(

1

)/(

11

I


42/115

42

Noise Factor of ID Structure

2

22

11

)(1

0

inms

smgss

ms

QgR

LgCRgR

NF

g

g

)(

1

smgss

inLgCR

Q

Increase power transfer

gmLs/Cgs= Rs

Decrease NF

gmLs/Cgs= 0

Conflict between

Power transfer

Noise performance


43/115

43

Further Discussion on NF

sg

s

sggsms

sm

smgss

ms

LL

L

LLCgR

Lg

LgCRgR

NF

g

g

g

41

)(

1)(41

)(1

2

22

0

Frequency @ 0

2~= 1/Cgs/(Lg+Ls)

Input impedance

matched to Rs

RsCgs=gmLs

Suitable for hand

calculation and design Large Lgand small Ls

Tss RL

gsgs CLL 2

01


44/115

44

Power Transfer of ID Structure

Rs= RL= R = 50 ohm

@

)()(1

)(1

)(1

)(1

2

2

2

2*

11

sggsgsssm

sggs

gsssmsggs

gsssmsggs

sin

sin

LLCsCRLgs

LLCs

CsRLsgLLCs

CsRLsgLLCs

ZZ

ZZS

)()(1

22

221

sggssmgss

LmLeff

LLCsLgCRs

RgRGS

)(1

smgss

inLgCR

Q

gssg CLL )(

120

s

LTinLm

smgss

Lm

R

RjQRgj

LgCRj

RgSS

00

2111 2

)(

2;0


45/115

45

Computing Avwithout S-Para

Rs

VsLs

Lg

)(

2/122

;2

:matchimputandresonanceAt

0

00

0

oos

T

s

ov

sTssgssmo

gsinmgsmossin

sin

YYRj

V

VA

RjVRCjVgI

CjIgVgIRVI

RZ


46/115

46

Power Consumption

DDTgs

ox

DDD VVVL

WCVIP 2)(

2

WLCC oxgs3

2)( Tgsoxm VV

L

WCg

222

2

3Tgsox

gs

m VVL

WC

C

Lg

gs

sms

C

LgR

s

gss

mL

CRg

)/1(3

1

)(3

1

3

)(333

32

0

2222

0

22

202

22

2

2222

sgs

DDs

sg

DDTDDgs

T

sg

DD

s

sDDgs

s

sDD

gs

m

LLL

VRL

LL

VLVC

LP

LL

V

L

RLVC

L

RLV

C

LgP


47/115

47

Power Consumption

)/1(

132

0

22

sgs

s

LLL

RLP

Technology constant

L: minimum feature size

: mobility, avoid mobility saturation region

Standard specification

Rs: source impedance

0: carrier frequency

Circuit parameter

Lg, Ls: gate and source degeneration inductance

sg

s

LL

LNF

g

410


48/115

48

Summary of ID Structure

Noise performance

No resistive noise source

Large Lg

Impedance matching Matched at carrier frequency

Applicable to wideband application, S11


49/115

49

Cascode

Isolation to improve S12

@ high frequency Small range at Vd1

Reduced feedback effectof Cgd

Improve noise

performance

Rs

VsLs

Lg

Vbias

LL

M2

M1

Vd1

Vo


50/115

50

Rs

Vs

Ls

Lg

LL

M1

Vo

Vgs gmVgsCgs

Rs

Vs

Lg

Ls LL

Vo


51/115

51

LNA Design Example (1)

Rs

Vs

Ls

Lg

Ld

M2

M1

Lvdd

Vbias

M4

Lb1

Cb1

Tm

Cm

M3

Lgnd

Lout

Input

bias Off-chip

matching

[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier,IEEE J. Solid-

State Circuits, vol. 32, pp. 745759, May 1997.

Lb2

Cb2Vout

Output

bias

Vdd


52/115

52


Rs

Vs

Ls

Lg

Ld

M2

M1

Lvdd

Vbias

M4

Lb1

Cb1

Tm

Cm

M3

Lgnd

Lout

[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier,IEEE J. Solid-

State Circuits, vol. 32, pp. 745759, May 1997.

Unwanted

parasitics

Supply

filtering


53/115

53

Circuit Details

Two-stage cascoded structure in 0.6 m

First stage

W1= 403 m determined from NF

Ls

accurate value, bondwire inductance

Ld= 7nH, resonating with cap at drain of M2

Second

4.6 dB gain

W3= 200 m


54/115

54

( )


55/115

55


[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer,IEEE J. Solid-State

Circuits, vol. 31, pp 19391944, Dec. 1996.

Cs

M2

M1

M3

Off-chip

matching

Ns

RB

VRF

CB

IREF

IB1

VB1M4M5

M7

M6

Vout1

RX

CX

NL

Off-chip

matching

NF = 1 + K/gmg

m= g

m1+ g

m2

Si lifi d i


56/115

56

Simplified view

LNA D i E l (2)


57/115

57


[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State


Cs

M2

M1

M3Bias

feedback

Ns

RB

VRF

CB

IREF

IB1

VB1M4M5

M7

M6

Vout1

RX

CX

NL

M8

LNA D i E l (2)


58/115

58




Cs

M2

M1

M3Bias

feedback

Ns

RB

VRF

CB

IREF

IB1

VB1M4M5

M7

M6

Vout1

RX

CX

NL

M8

LNA D i E l (2)


59/115

59




Cs

M2

M1

M3Bias

feedback

Ns

RB

VRF

CB

IREF

IB1

VB1M4M5

M7

M6

Vout1

RX

CX

NL

M8VA

DC output = VB1


60/115

60


61/115

61


Objective is to design tunable RF LNA that

would:

Operate over very wide frequency range with very fineselectivity

Achieve a good noise performance

Have a good linearity performance

Consume minimum power


62/115

62

LNA Architecture The cascode architecture

provides a good inputoutput isolation

Transistor M2isolates the

Miller capacitance

Input Impedance is obtained

using the sourcedegeneration inductor Ls

Gate inductor Lgsets the

resonant frequency

The tuning granularity isachieved by the output

matching network

VDD

LSLG

M1

M2

LD

R2

R1

M3

Output to

Mixer

Input to LNA

Matching

Network


63/115

63

Matching Network The output matching tuning

network is composed of avaractor and an inductor.

The LC network is used to

convert the load impedance

into the input impedance of

the subsequent stage.

A well designed matching

network allows for a

maximum power transfer to

the load. By varying the DC voltage

applied to the varactor, the

output frequency is tuned to

a different frequency.


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64

Simulation Results - S11 The input return loss

S11 is less than10dBat a frequency range

between 1.4 GHz and

2GHz

Input return loss


65/115

65

Simulation results - NF The noise figure is 1.8

dB at 1.4 GHz and risesto 3.4 dB at 2 GHz.

Noise Figure


66/115

66

Simulation Results - S22

S22 at 1.7725 GHzS22 at 1.77 GHz

By controlling the voltage applied to the varactor the output frequency

is tuned by 2.5 MHz.The output return loss at 1.77 GHz is 44.73 dB and the output return

loss at 1.7725 GHz 45.69 dB.


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67

Simulation Results - S22

S22 at 1.9975 GHzS22 at 2 GHz

The output return loss at 2 GHz is 26.47 dB and the output return

loss at 1.9975 GHz

26.6 dB.


68/115

68

Simulation Results - S21 The overall gain of

the LNA is 12 dB

S21 at 1.4025 GHz

Simulation Results Linearity


69/115

69

Simulation Results - Linearity

-1dB compression pointIIP3

The third order input intercept is 3.16 dBm

-1 dB compression point ( the output level at which the actual gaindeparts from the theoretical gain) is 12 dBm

From an earlier slide:


70/115

70

From an earlier slide:

fWLC

kfV

ox

g )(2

Flicker noise Dominant at low frequency

Thermal noise

g: empirical constant

2/3 for long channel

much larger for short channel

PMOS has less thermal noise

Input-inferred noise

md gkTfI g4)(2

Vg

Id

Vi

fWLC

k

gkTfV

oxm

i g

4)(2

Not accurate for low voltage short channel devices

Modifications


71/115

71

Modifications

gis called excess noise factor

= 2/3 in long channel

= 2 to 3 (or higher!) in short

channel NMOS (less in PMOS)

gg

mdod

gkTgkTfI 44)(2

Thermonoise

g vs g in short channel


72/115

72

gdovs gmin short channel

g vs g in short channel


73/115

73

gdovs gmin short channel

Fliker noise


74/115

74

Fliker noise Traps at channel/oxide interface randomly

capture/release carriers

Parameterized by Kf and n

Provided by fab (note n 1)

Currently: Kf of PMOS


75/115

75

Induced Gate Noise Fluctuating channel potential couples

capacitively into the gate terminal, causing anoise gate current

dis gate noise coefficient

Typically assumed to be 2g

Correlated to drain noise!

2

2

5

4

d

T

dong gkTi


76/115

76

Input impedance

Set to be real and equal to source resistance:

real

gs

m

gs

ginC

Lg

sCLLssZ

deg

deg

1)()(

gsg CLL )(

1

deg

2

0

s

gs

mR

C

Lgdeg

Output noise current


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77

Output noise current

)14(21)(

222

QcgkTfIdddod g

Noise scaling factor:

)14(214

1 22 Qc dd

Where for 0.18 process

c=-j0.55, g=3, d=6, gdo=2gm,

d= 0.32

g

d

5do

md

g

g

s

g

gss R

LL

CRQ

2

)(

2

1 deg0

0

Noise factor


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78

Noise factor

Noise factor scaling coefficient:

22 )14(212

dd

m

donf Qc

g

g

QK

g

22 )14(2121 ddmdo

T

o Qcg

g

QF g

42

1)(41 02200 Q

CRgRNG

NGNNF

T

gss

msin

indevice g

g

Compare:

Noise factor scaling coefficient versus Q


79/115

79

Noise factor scaling coefficient versus Q

Example


80/115

80

Example

Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz

From

gss CRQ

02

1

fFeQR

Cs

gs 442)2(98.12)50(2

12

10

nH

e

R

g

CRL

T

s

m

gss17.0

98.472

50deg

nHLC

LCLL gs

g

gsg

5.171

)(

1deg2

0deg

2

0

Have We Chosen the Correct Bias Point?


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Have We Chosen the Correct Bias Point?

IIP3 is also a function of Q

If we choose Vgs=1V


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If we choose Vgs=1V

Idens= 175 A/m

From Cgs= 442 fF, W=274m

Ibias= IdensW = 48 mA, too large!

Solution 1: lower Idens=> lower power,

lower fT, lower IIP3

Solution 2: lower W => lower power, lowerCgs, higher Q, higher NF

Lower current density to 100


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Need to verify that IIP3 still OK (once we know Q)



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84

We now need to re-plot the Noise Factor scaling coefficient

- Also plot over a wider range of Q


43.05

2

68.0568.015.1

78.0

d

do

m

d

do

m

g

g

g

g

GHz8.4229.2

78.0

fF

mS

C

g

gs

mT

22 )14(212

11 dd

m

do

T

o QcQg

gF g


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Recall

We previously chose Q = 2, lets now choose Q = 6

- Cuts power dissipation by a factor of 3!- New value of W is one third the old one

mm

W

913

274

R = 50 Ohms Q = 6 f = 1 8 GHz ft =


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Rs 50 Ohms, Q 6, fo 1.8 GHz, ft42.8 GHz

Ibias= IdensW =100A/m*91m=9.1mA Power = 9.1 * 1.8 = 16.4 mW

Noise factor scaling coeff = 10

Noise factor = 1+ wo/wt* 10= 1+ 1.8G/42.8G *10 = 1.42

Noise figure = 10*log(1.42) = 1.52 dB

Cgs=442/3=147fF Ldeg=Rs/wt=0.19nH

Lg=1/(wo^2Cgs)Ldeg = 53 nH

Other architectures of LNAs


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Other architectures of LNAs

Add output load to achieve voltage gain

In practice, use cascode to boost gain

Added benefit of removing Cgd effect


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Differential LNA

Value of Ldeg is now much better controlled

Much less sensitivity to noise from other circuits

But: Twice the power as the single-ended version

Requires differential input at the chip

LNA Employing Current Re-Use


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LNA Employing Current Re Use

PMOS is biased using a current mirrorNMOS current adjusted to match the PMOS current

Note: not clear how the matching network is achieving a 50 Ohm match

Perhaps parasitic bondwire inductance is degenerating the PMOS or

NMOS transistors?

C bi i i d ti


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Combining inductive

degeneration and current reuse

Current reuse to save power

Larger area due to two degeneration

inductor if implemented on chip

NF: 2dB, Power gain: 17.5dB, IIP3: -

6dBm, Id: 8mA from 2.7V power supply

Can have differential version

F. Gatta, E. Sacchi, et al, A 2-dB Noise Figure 900MHz Differential CMOS LNA,

IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452


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At DC, M1 and M2 are in cascode

At AC, M1 and M2 are in cascade

S of M2 is AC shortedGm of M1 and M2 are multiplied.

Same biasing current in M1 & M2

LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNALfrom the February 2004 issue.

IM3 components in the drain

current of the main transistor has


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bao

bmb

amamama

iii

vgi

vgvgvgi

3

3

3

3

2

21

current of the main transistor has

the required information of its

nonlinearity

Auxiliary circuit is used to tune the

magnitude and phase of IM3

components

Addition of main and auxiliary

transistor currents results innegligible IM3 components at

output

Sivakumar Ganesan, Edgar Snchez-sinencio, And Jose Silva-martinezIEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006


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94

MOS in weak inversion has speed problem

MOS transistor in weak inversion acts like bipolar

Bipolar available in TSMC 0.18 technology (not a parasitic BJT)Why not using that bipolar transistor to improve linearity ?

Inter-stage Inductor gain boost


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Inter stage Inductor gain boost

Inter-stage inductor with

parasitic capacitance form

impedance match network between

input stage and cascoded stage

boost gain lower noise figure.

Input match condition will be

affected

Folded cascode


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96

Low supply voltage

Ld reduces or eliminates

Effect of Cgd1

Good fT

Design Procedure for InductiveS D t d LNA


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Source Degenerated LNA

Noise factor equations:

22 )14(212

11 dd

m

do

T

o QcQg

gF g

22 )14(212

1dd

m

donf Qc

Qg

gK g

Targeted Specifications


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98

a ge ed Spec ca o s

Frequency 2.4 GHz ISM Band

Noise Figure 1.6 dB

IIP3 -8 dBm

Voltage gain 20 dB

Power < 10mA from 1.8V

Step 1: Know your process


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p y p

A 0.18um CMOS Process

Process related

tox= 4.1e-9 m

e= 3.9*(8.85e-12) F/m

= 3.274e-2

m^2/V.s Vth= 0.52 V

Noise related

= gm/gdo

d/g~ 2

g~ 3

c = -j0.55

Step 2: Obtain design guide plots


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p g g p

Insights:


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g

gdoincreases all the way with current

density Iden gmsaturates when Idenlarger than

120A/m

Velocity saturation, mobility degradation ----short channel effects

Low gm/current efficiency

High linearity

deviates from long channel value (1)with large Iden

Obtain design guide plots


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g g p

Insights:


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103

g

fTincreases with Vodwhen Vodis small and

saturates after Vod> 0.3V --- short channeleffects

Cgs/W increases slowly after Vod> 0.2V

fTbegins to degrade when Vod> 0.8V

gmsaturates

Cgsincreases

Should keep Vod~0.2 to 0.4 V



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g g p

3-D plot for visual

inspection

2-D plots for

design reference

knfvs input Q and current density

Design trade-offs


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105

g

For fixed Iden, increasing Q will reduce the

size of transistor thus reduce total power ---- noise figure will become larger

For fixed Q, reducing Idenwill reduce

power, but will increase noise factor

For large Iden, there is an optimal Q for

minimum noise factor, but power may be

too high



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g g p

Linearity plots :IIP3 vs. gate overdrive and transistor size

Insights:


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107

g

MOS transistor IIP3 only, when embedded into

actual circuit: Input Q will degrade IIP3

Non-linear memory effect will degrade IIP3

Output non-linearity will degrade IIP3

IIP3 is a very weak function of device size

Generally, large overdrive means large IIP3

But the relationship between IIP3 and gate overdrive

is not monotonic There is a local maxima around 0.1V overdrive

Step 4: Estimate fT


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p T

Small current budget ( < 10mA )

does not allow large gate over drive :

Vod~ 0.2 V ~ 0.4 V

fT~ 40 ~ 44 GHz

Step 4: Determine Iden, Q andCalculate Device Size


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Calculate Device Size

Select Iden= 70 A/m, =>Vod~0.23V

Gm/W~0.4


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If Q = 4, IIP3 will have enough margin:

Estimated IIP3:

IIP3(from curve) 20log(Q) = 8-12 = -4dBm

Specs require: -8 dBm


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Q=4 and Iden= 70A/m meet the

noise factor requirement


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Gm=0.4*128 ~ 50 mS fT = gm/(Cgs*2pi) = 48 GHz

Step 6: Simulation Verification


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Large deviation


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Comparison between targetedspecs and simulation results


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specs and simulation results

Parameter Target Simulated

Noise Figure 1.6 dB 0.8 dB

Drain Current < 10mA 8 mA

Voltage gain 20 dB 21 dB

IIP3 -8 dBm -6.4 dBm

P1dB -20dbm

S11 -17 dB

Power supply 1.8 V 1.8 V

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