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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power ...

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LM73605 Positive Buck LMR14050 Negative Buck TLV2171 TLV2171 TPS7A3301 TPS7A3301 LEVEL SHIFT Circuit Measures LDO input and maintains 1 V dropout at LDO Feedback DAC Positive DAC Negative +24 V Input Feedback -2.5 V to -12 V 1A on each line +2.5 V to 12 V 1A on each line CLK IN SYNC To Buck Regulators TPS7A4701 TPS7A4701 Copyright © 2017, Texas Instruments Incorporated 1 TIDUD98 – September 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Low-Noise, Fixed Drop-Out, ±2.5- to ±12-V OUT , 3-A Power Supply Reference Design for Ultrasound CW Pulser TI Designs: TIDA-01458 Low-Noise, Fixed Drop-Out, ±2.5- to ±12-V OUT , 3-A Power Supply Reference Design for Ultrasound CW Pulser Description This reference design allows a digitally programmable power supply to power an ultrasound transmit circuit for continuous wave (CW) mode from a 24-V bus. There are two outputs adjustable from ±2.5 to ±12 V under user software control. These outputs can provide up to 2 A with very low ripple and noise on both positive and negative regulator outputs. The power supply is scalable for higher output currents up to 3 A by adding more regulators in parallel. The power supplies can also be synchronized to an external clock. Resources TIDA-01458 Design Folder TIDA-01352 Design Folder LMR14050 Product Folder LM73605 Product Folder TPS7A47 Product Folder TPS7A33 Product Folder TLV2171 Product Folder TL431A Product Folder ASK Our E2E Experts Features Separate and Independent Positive and Negative Voltage Power Supplies for CW Mode in Ultrasonic Pulsar Comprises Two High-Performance Buck Regulators for Creating Adjustable Outputs To Reduce Ripple at Outputs High Performance, Low Noise LDOs are Operated as Power Filters to Obtain Lowest Ripple With Minimum Heat Dissipation in LDO (< 100 μV at 1.6-A Load) Adaptive Drop on LDO, Special Circuit Keeps LDO Output Always 1 V Below LDO Input Reduces Power Dissipation in LDO Capable of Switching Frequency Synchronization With Ultrasound Master or System Clock Frequency Helps in Better Harmonics Rejection Modular Design Allowing More Regulator Blocks to be Added Applications Medical Ultrasound Scanners Sonar Imaging Equipment Nondestructive Evaluation Equipment An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information.
Transcript

LM73605Positive Buck

LMR14050Negative Buck

TLV2171

TLV2171TPS7A3301

TPS7A3301

LEVEL SHIFT

Circuit Measures LDO input and maintains 1 V

dropout at LDO

Feedback

DAC Positive

DAC Negative

+24 V Input

Feedback

-2.5 V to -12 V1A on each line

+2.5 V to 12 V1A on each line

CLK IN

SYNC To Buck Regulators

TPS7A4701

TPS7A4701

Copyright © 2017, Texas Instruments Incorporated

1TIDUD98–September 2017Submit Documentation Feedback

Copyright © 2017, Texas Instruments Incorporated

Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

TI Designs: TIDA-01458Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A PowerSupply Reference Design for Ultrasound CW Pulser

DescriptionThis reference design allows a digitally programmablepower supply to power an ultrasound transmit circuitfor continuous wave (CW) mode from a 24-V bus.There are two outputs adjustable from ±2.5 to ±12 Vunder user software control. These outputs canprovide up to 2 A with very low ripple and noise onboth positive and negative regulator outputs. Thepower supply is scalable for higher output currents upto 3 A by adding more regulators in parallel. Thepower supplies can also be synchronized to anexternal clock.

Resources

TIDA-01458 Design FolderTIDA-01352 Design FolderLMR14050 Product FolderLM73605 Product FolderTPS7A47 Product FolderTPS7A33 Product FolderTLV2171 Product FolderTL431A Product Folder

ASK Our E2E Experts

Features• Separate and Independent Positive and Negative

Voltage Power Supplies for CW Mode in UltrasonicPulsar

• Comprises Two High-Performance BuckRegulators for Creating Adjustable Outputs

• To Reduce Ripple at Outputs High Performance,Low Noise LDOs are Operated as Power Filters toObtain Lowest Ripple With Minimum HeatDissipation in LDO (< 100 µV at 1.6-A Load)

• Adaptive Drop on LDO, Special Circuit Keeps LDOOutput Always 1 V Below LDO Input– Reduces Power Dissipation in LDO

• Capable of Switching Frequency SynchronizationWith Ultrasound Master or System ClockFrequency– Helps in Better Harmonics Rejection

• Modular Design Allowing More Regulator Blocks tobe Added

Applications• Medical Ultrasound Scanners• Sonar Imaging Equipment• Nondestructive Evaluation Equipment

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.

±2.5 V to ±100 V

HV Power Supply12 V or 24 V Power Bus from Power Supply Unit

CLK

HV MUX

DEMUXT/R Switch

Transmitter (Pulser or Linear Amplifier)

TGC Circuit

Analog Front End (AFE)

CW Circuit

TX Beamformer

RX Beamformer

BeamformerControl Unit

TX/RX Beam Forming

Front-End Power Supply

Ultr

asou

nd T

rans

duce

r

E-Fuse

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

1 System DescriptionThis design guide describes a power supply for continuous wave (CW) mode. These typically need ±2.5 to±12 V under software control. Budget a current delivery up to 3 A at outputs of DC-DC converters. Inaddition, the power supplies must have a very low level of ripple and noise at the output voltage.

1.1 Basic Ultrasound SystemIn an ultrasound system, the transmitter that generates high-voltage signals to excite a transducer is oneof the most critical components in the entire ultrasonic diagnostic system. There are semiconductordevices available that can generate high-voltage signals to ensure the penetration depth of ultrasonicsignals. A generic system-level block diagram for a cart-based ultrasound scanner is shown in Figure 1.

Figure 1. System-Level Block Diagram for Cart-Based Ultrasound Scanners

The high-voltage pulses (to be transmitted inside human body to get information about blood, organs,tissues, and so on) are bipolar in nature and are transmitted by transmitters (TXs). There are two modesin general:1. Pulse (also known as brightness, or B) mode where high-voltage pulses (–100 V and 100 V, typically)

are transmitted for a particular short time only.2. CW mode where low-voltage (±2.5 to ±10 V, typically) pulses are continuously transmitted.

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

1.2 Key System SpecificationsTable 1 shows the key system specifications.

Table 1. Key System Specifications

PARAMETER SPECIFICATIONSInput voltage (VIN) 24 V ±10%VBUCK positive output voltage range 2.5 to 12 VLoad current capacity positive buck 3 AVBUCK negative output voltage range –2.5 to –12 VLoad current capacity negative buck 3 ALDO (VIN–VO) drop across the LDO 1 V (adjustable through pre-set)External clock synchronization YesExternal sync frequency 400 kHzLDO output current capacity 2 × 1 A positiveLDO output current capacity 2 × 1 A negativeScalability Yes

LM73605Positive Buck

LMR14050Negative Buck

TLV2171

TLV2171TPS7A3301

TPS7A3301

LEVEL SHIFT

Circuit Measures LDO input and maintains 1 V

dropout at LDO

Feedback

DAC Positive

DAC Negative

+24 V Input

Feedback

-2.5 V to -12 V1A on each line

+2.5 V to 12 V1A on each line

CLK IN

SYNC To Buck Regulators

TPS7A4701

TPS7A4701

Copyright © 2017, Texas Instruments Incorporated

System Overview www.ti.com

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

2 System Overview

2.1 Block Diagram

Figure 2. System Block Diagram

Positive Regulator BlockThis reference design uses the LM73605 DC-DC converter as a synchronous buck regulator. The outputis varied by changing the feedback factor of the regulator in response to a DC control voltage the outputcan vary from 2.5 to 12 V and the device can deliver load currents up to 5 A. To eliminate the ripple on thebuck, the TPS7A4701 low-noise LDO is used as a power filter. The voltage drop (Vin-Vo) across the LDOis kept at 1 V. This drop is above the dropout of the regulator and thus the LDO can have low powerdissipation as well as good PSRR performance. This drop across the LDO is maintained for all outputvoltage settings of the buck. This is done by an op amp feedforward circuit that monitors the DC voltage atthe input of the LDO and adjusts the feedback pin of the LDO to keep a fixed Vin-Vo across the regulator.

Negative Regulator BlockThis reference design uses the LMR14050 DC-DC converter setup as an inverting regulator. The output isvaried by changing the feedback factor of the regulator in response to a DC control voltage. The outputcan vary from –2.5 to –12 V and the device can deliver load currents up to 3 A. To eliminate the ripple onthe buck, the TPS7A3301 low-noise LDO is used as a power filter. The voltage drop (Vin-Vo) across theLDO is kept at 1 V. This drop is above the dropout of the regulator and thus the LDO can have low powerdissipation as well as good PSRR performance. This drop across the LDO is maintained for all outputvoltage settings of the buck. This is done by an op amp feedforward circuit that monitors the DC voltage atthe input of the LDO and adjusts the feedback pin of the LDO to keep a fixed Vin-Vo across the regulator.

The system is modular. More DC-DC converter sections that are identical to the ones demonstrated canbe added to increase output current capacity. All sections are driven with the same DC control waveformas well as the sync waveform.

Presets in the board can adjust the dropout to values other than 1 V by the designer.

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

2.2 Highlighted Products

2.2.1 LM73605The LM73605 device is a synchronous step-down DC-DC converter capable of driving 5 A from a supplyvoltage from 3.5- to 36-V DC. It has high efficiency and a high-output accuracy in a small solution size.Peak current mode control is employed. The device has an adjustable frequency and also allowsfrequency synchronization.

2.2.2 LMR14050The LMR14050 device is an integrated 40-V, 5-A step-down regulator with an integrated switching FET.The device has an ultra-low quiescent current of 1 µA in sleep mode. It has an adjustable switchingfrequency range and internal loop compensation .It also has cycle-by-cycle current limit, thermal sensing,and shutdown.

2.2.3 TPS7A4701The TPS7A4701 device is a positive voltage (36 V), ultra-low-noise (4 µVRMS) low-dropout linear regulator(LDO) capable of sourcing a 1-A load.

2.2.4 TPS7A3301The TPS7A3301 device is a negative voltage (–36 V), ultra-low-noise (16-μVRMS, 72-dB PSRR) linearregulator capable of sourcing a maximum load of 1 A.

2.2.5 TLV2171The 36-V TLV2171 device provides a low-power option for cost-conscious industrial and personalelectronics systems requiring an electromagnetic interference (EMI)-hardened, low-noise, single-supplyoperational amplifier (op amp) that operates on supplies ranging from 2.7 V (±1.35 V) to 36 V (±18 V).

0.47µFC1

0.47µFC7

0.47µF

C610µFC5

AGND1

10µFC4

240kR1

47kR3

470R5

0.1µFC15

3

1

2

Q1BC847CLT1G

4.70kR10

0.1µFC12

1.00MR7

4.7pFC13

0R21µFC11

PGND_A

68kR4

4.70kR8

10.0kR11

20kR9

1

23

Q2BSS123

3

1

2

Q4BC857C-7-F

3.3kR15

AGND AGND

BOOT1

VIN2

EN3

RT/SYNC4

FB5

SS6

GND7

SW8

PAD9

U4

LMR14050SDDAR

4.7µFC23

4.7µFC24

59.0kR25

0.1µFC25

22kR24

3.3kR28

1

3

2

D2PDS760-13

1µFC29

1µFC30

AGND

0R31

3

1

2

Q5BC857C-7-F

+3.3V

0.1µFC22

2.2kR21

10µFC19

4.70kR14

3

1

2

Q3BC847CLT1G

10nFC21

3

21

U3TL431ACDBZR

33kR19

180kR18

AGND AGND

2

3

1A

V+

V-

84

U2ATLV2171IDR

5

6

7B

V+

V-

84

U2BTLV2171IDR

0.1µF

C1416V

16V

AGND

16V

AGND

SYNC

+Vo

-Vo

-3.3V

24VIN

PGND_B

PGND_A PGND_APGND_A

AGND

93.1kR58

PGND_A

PGND_A

PGND_A

PGND_A

PGND_APGND_A

PGND_APGND_A

PGND_A

PGND_A

PGND_B

3.3VD3

3.3VD1

PGND_B

PGND_B

PGND_B

PGND_A

10KR20

10KR17

100kR23

100kR26

3

1

2

Q6BC857C-7-F

0.027µFC32

4

1

2

3

J1

TSW-104-07-G-S

3.3VD4

AGND

AGND1 AGND1

AGND1 AGND1

AGND1

AGND1

AGND1

24VIN

B

A

22µFC8

22µFC9

22µFC10

0.1µFC27

47µFC31

L3

XAL7030-222MEB

L4

XAL7030-222MEB

470R29

47µFC62

PGND_B

470µFC2

470µFC26

1

2

J4

1715721

2.2µF

C3

0.022µFC16

2.0kR13

1.00kR12

10µFC20

10µFC17

10µFC18

22µFC33

10R64

100

R65

1µFC63

-Vo

442kR27

33µH

L2

1.00kR49 22kR56

10µFC641.00k

R66

FB

SYNC

PGND_A

3.6kR22

220R30

22pFC65

10µH

L1

100R6

47kR68

47kR67

D9

1N4148W-TP

SW1

SW2

SW3

SW4

SW5

CBOOT6

VCC7

BIAS8

RT9

SS/TRK10

FB11

NC12

NC13

NC14

NC15

PGOOD16

SYNC17

EN18

AGND19

VIN20

VIN21

VIN22

PGND23

PGND24

PGND25

PGND26

NC27

NC28

NC29

NC30

DAP31

U1

LM73605RNPR

2.7kR16

Copyright © 2017, Texas Instruments Incorporated

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

2.3 System Design TheoryThis section explains the design theory and equations for each of the devices used in this referencedesign.

Figure 3. DC-DC Converters Schematic

O CONV 15.7 15 V= - ´

( ) ( )OV 68k 1 V 1M

1 V1M 68k 1M 68k

´ ´+ =

+ +

( ) ( )OV R4 1 V R7

1 VR7 R4 R7 R4

´ ´+ =

+ +

( )O

1 V 1M 68 kV 15.7-V maximum output voltage

68 k

+= =

( )O

R4V 1V

R7 R4= =

+

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

2.3.1 Positive Switching RegulatorsThe LM73605 (U1) is a synchronous buck regulator that can drive 5 A of current. The output voltage istypically set up by R7 and R4. The feedback pin is normally regulated to 1 V. A DC control voltagebetween 0 and 3.3 V applied to Pin 1 of J1 is used to modify the output of the buck regulator from 2.5 to15 V. This voltage is applied to U2B. This is an op amp buffer and its output is connected to a low-passfilter comprising of R8 and C17. The low-pass filter ensures that a pure DC voltage is applied to thefeedback pin. Assume that the control voltage on Pin 1 of JI is 0 V. The output of op amp U2B is also 0 V.

(1)

Assume now that 3-V DC is applied on Pin 1 of J1. The output of the op amp is now 1-V DC. Applying thesuperposition theorem on the feedback pin:

(2)

Therefore, for a DAC control range of 0 3 V, the output voltage varies from 1 to 15.7 V.(3)

This is an approximate equation describing the behavior given the resistors placed R58 on pin 9 of U1sets the operating frequency of the DC-DC converter.

( )STRESS IN OMAXV V V= +

VCC

S1

D

LBuck Regulator

-Vo

Vcc

S1

S2

L-Vo

Circuit FlippedC

DVcc

S1

L

-Vo

Traditional diode form of inverting buck

C

Vo

C

VCC

S1

D

L

Inverting Buck as used in

circuit

C

Rt Resistance (k:)

Sw

itchi

ng F

requ

ency

(kH

z)

10 30 50 70 90 110 1200

500

1000

1500

2000

2500

D007

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

Figure 4 shows that a frequency of 400k is set for a 93k resistor. Transistor Q1 is set up as a buffer and isused to couple the sync signal to the sync pin. With no sync input, the sync pin is ground with a 10kresistor.

Figure 4. RT Resistance versus Frequency

U4 (LMR14050) is a 5-A non-synchronous buck regulator. This regulator is set up as an invertingregulator. As shown in Figure 5, to set up a buck regulator in inverting mode, the bottom of S2 isconnected as a negative output. The output end of the inductor L is grounded. The circuit now looks like atraditional negative regulator.

Figure 5. Basic Functionality of Negative Switching Regulators

Note that the maximum voltage that the device sees is as calculated using Equation 4:

(4)

For VIN = 24 v and VO = –15 V, the device sees 39 V, which is very close to the absolute maximum ratingof the device. Therefore, a maximum of -12 V can be kept at the output.

( )O

O

V 22 k0.75

22k 442 k

V 15 V

´=

+

= -

( )OV R56

0.75 VR27 R56

´=

+

( )O MAXI I 1 D= ´ -

MAX

O

I TOFFI

T

´

=

( )O

V DV

1 D

´=

-

OV TON V TOFF´ = ´

TON TOFF

IL

IS2

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

Figure 6. Theoretical Waveforms for Negative Buck

Regarding Figure 6, assume TON is the time S1 conducts and TOFF is the time S2 conducts.

(5)

Note that IO = Average of IS2.

(6)

Therefore, if VO = –15 V, D = 0.36, IO maximum = 3 A for a 5-A buck switcher. Resistors R27 and R56 areused to set the output voltage. The LMR14050 has a feedback voltage of 0.75 V.

(7)

To adjust the negative output, apply a DC control voltage between 0 and 3 V to Pin 2 of J1.

MIN

0.65 103.6 kV 18 V

3.6 k

´

= =

( )MINV R22

0.65 VR22 R23

´=

+

Frequency (kHz)

RT

(kΩ

)

0 500 1000 1500 2000 25000

20

40

60

80

100

120

140

D008

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

The collector of Q5 adds a voltage to the feedback pin of the LMR14050. When this voltage from thefeedback pin to the device ground equals 0.75 V, the output of the negative converter drops to zero. The0.75 V is obtained through the op amp current source. When the DC voltage applied to pin 3, U2A is 0 V.The current in Q5 = 3.3/R16 or 3.3/3K3 = 1 mA. R66 × 1 mA = 1 V. This is more than the 0.75 V neededto bring the output voltage to zero.

Figure 7. RT versus Frequency

Table 2. Typical Frequency Setting RT Resistance

fSW (kHz) RT (kΩ)200 127.0350 71.5500 49.9750 32.4

1000 23.71500 15.82000 11.52200 10.5

This is an approximate equation describing the behavior given the resistors placed R25 is used to set theoscillator frequency at 400k.

Transistor Q4 is used to couple the sync signals to the RT pin. When there is no sync signal, the transistoris cut off. The Enable pin is driven by transistor Q6. This transistor acts as a level shifter as the Enable pinis referenced to –VO. Resistors R22 and R23 act as a voltage divider and at a minimum supply voltageturn the PNP transistor on

(8)

OUT1

NC2

SENSE/FB3

6P4V24

6P4V15

3P2V6

GND7

1P6V8

0P8V9

0P4V10

0P2V11

0P1V12

EN13

NR14

IN15

IN16

NC17

NC18

NC19

OUT20

PAD21

U5

TPS7A4701RGWR

1µFC38

10µFC39

0.1µFC36

330R34

OUT1

NC2

SENSE/FB3

6P4V24

6P4V15

3P2V6

GND7

1P6V8

0P8V9

0P4V10

0P2V11

0P1V12

EN13

NR14

IN15

IN16

NC17

NC18

NC19

OUT20

PAD21

U6

TPS7A4701RGWR

1µFC46 10µFC47

0.1µFC42

330R40

1µFC48

10.0k

R39

10.0k

R36

10µF

C45

OUT1

FB3

GND7

EN13

NR/SS14

IN15

IN16

OUT20

GND21

U8A

TPS7A3301RGWR

OUT1

FB3

GND7

EN13

NR/SS14

IN15

IN16

OUT20

GND21

U10A

TPS7A3301RGWR

1.2MR43

10.0kR47

1µF

C59

1µF

C53

1.2MR52

10.0kR57

10.0k

R48

0.1µF

C54

AGND

AGND

AGND

AGND

AGND

2

3

1A

V+

V-

84

U9ATLV2171IDR

5

6

7B

V+

V-

84

U9BTLV2171IDR

2

3

1A

V+

V-

84

U7ATLV2171IDR

5

6

7B

V+

V-

84

U7BTLV2171IDR

0.1µF

C4416V

AGND

16V

AGND

0.1µF

C55

0.1µF

C5216V

-3.3V16V

-3.3V

+Vo

-Vo

REGP

REGP

REGP REGP REGP

REGP

REGP

REGP REGP REGP

REGM

1µFC60

1µFC61

REGM

REGM REGM

REGM REGMREGM

REGM

AGND

0R59

0R60

0R61

0R62

REGM

REGP

PGND_B

PGND_A

AGND

NC10

NC11

NC12

NC17

NC18

NC19

NC2

NC4

NC5

NC6

NC8

NC9

U8B

TPS7A3301RGWR

NC10

NC11

NC12

NC17

NC18

NC19

NC2

NC4

NC5

NC6

NC8

NC9

U10B

TPS7A3301RGWR

100kR44

100k

R45

D5

B260A-13-F

D6

B260A-13-F

D7

B260A-13-F

D8

B260A-13-F

AGND

AGND

AGND

1

2 3 4 5

J7

901-144-8RFX

1

2 3 4 5J5

901-144-8RFX

1

2 3 4 5

J6

901-144-8RFX

AGND

AGND

AGND

REGM

REGP

1

2 3 4 5

J8901-144-8RFX

AGND

0R63

AGND1

B

10µFC34

10µFC40

10µFC49

10µFC56

10µFC37

10µFC43

10µFC51

10µFC58

REGM

REGM

REGPREGP

REGP

REGP

REGMREGM

REGM

REGM

47µFC35

47µFC41

47µFC50

47µFC57

10.0kR33

10.0kR37

A

1

2

3

J2

1792876

1

2

3

J3

1792876

100kR32

100kR35

100kR46

100kR55

100k

R41

100k

R38

10.0kR42

180kR50

180k

R53

15.0k

R51

15.0kR54

Copyright © 2017, Texas Instruments Incorporated

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Low-Noise, Fixed Drop-Out, ±2.5- to ±12-VOUT, 3-A Power Supply ReferenceDesign for Ultrasound CW Pulser

2.3.2 Linear Regulators

Figure 8. Linear Regulators Schematic

The LDO section filters out the ripple content in the switching regulators and leaves a very ripple-free andlow-noise output to feed the CW power. It relies on the fact that a linear regulator is an active filter andcan reduce the ripple seen at its input due to its excellent PSRR performance. For this to work well, theLDO must be in the active region well beyond the dropout; however, operating a regulator in the activeregion results in power dissipation [I × (VIN – VO)]. Therefore, to prevent dissipation, it is best to run theregulator just outside its minimum dropout. Because the input voltage of the regulator varies as it is set bysoftware, the hardware circuitry on the board continuously monitors the input voltage, removes the ripple,and adjusts the feedback voltage so that the output voltage is always 1 V lower than input whatever inputis present.

( )IN

CON

16.4 VV

10

-=

IN CONV 1 V 10 15.4- + ´ =

( ) ( )O CON

O CON

O CON

V R2 V R1

R1 R2 R1 R2

V V 101.4 V

11 11

V V 10 15.4 V

´ ´+

+ +

´+ =

+ ´ =

OMAX

1.4 110 kV 15 V

10 k

´

= =

( )OMAXV R2

1.4 VR1 R2

´=

+

R1

R2

Vcon

VinTPS7A4701

Vo

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Figure 9 shows a positive LDO with a control voltage applied to R2.

Figure 9. Positive LDO Controlled Using VCON

Case 1: When VCON = 0 V, let the maximum output voltage be 15 V (VFBK = 1.4 V).

(9)

Case 2: With VCON applied with R1 = 100K, R2 = 10K:

(10)

Assume VO = VIN – 1 and apply in Equation 11:(11)

Equation 11 can be implemented in a differential amplifier: one input is a DC voltage of 16.4 V, the otherbeing the regulator input voltage. The differential amp is set up with a gain of 1/10. In the schematic, U7Ais the differential amplifier. R36, R38, R41, and R42 set up a differential gain of 1/10. R39 and C48 form alow-pass filter that removes any ripple on this line and leaves a DC equal to the average value of voltageat the input. U7B is a buffer and the output of this drives the feedback pin. This system is a feedforwardsystem and must not face any stability issues.

For example: If VIN = 10 V, then the differential amplifier output VCON = (16.4 – 10)/10 = 0.64 V. Now:• VO + 0.64 × 10 = 15.4• VO = 15.4 – 6.4 = 9 V• VO – VIN = 1 V

� �IN CON

INCON

V 1 V 10.9 13.45

14.45 VV

10.9

� � u �

� �

� � � �

� � � �

O CON

O CON

O CON

V R2 V R11.13 V

R1 R2 R1 R2

V 110k V 1.2M1.13 V

1.2M 110k 1.2M 110k

V V 10.9 13.45 V

u u� �

� �

u u� �

� �

� u �

( )OMAX

OMAX

V R21.13 V

R1 R2

1.13 1.3MV

100k

´= -

+

- ´=

R1

R2

Vcon

VinTPS7A3301

Vo

Copyright © 2017, Texas Instruments Incorporated

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Figure 10 assumes a negative LDO with a control voltage applied to R2.

Figure 10. Negative LDO Controlled Using VCON

Case 1: When VCON = 0, let the maximum output voltage be –15 V, VFB = –1.13 V.

Case 2: With VCON applied and with R1 = 1200k, R2 = 110k:

(12)

Assume VO = VIN + 1 and apply in Equation 13:

(13)

OV 14.69 0.475 12 9 V= - ´ = -

� �10 14.450.4 V

10.9

� �

O CON

O

O

V V 10.9 13.45 V

V 0.475 10.9 13.45 V

V 9 V

� u �

� u �

� �� �CON

14.45 10V 0.408 V

10.9

� � � �

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Equation 13 can be implemented in a differential amplifier: one input is a DC voltage of 15.7 V, the otherbeing the regulator input voltage. U9A is a differential amplifier with a gain of –1. This converts thenegative input voltage to a positive output level. U9B is a differential amplifier with a gain 1/10.9 thatcompares the positive output voltage seen on U9A with a fixed DC voltage of –14.45 V. For example: Ifthe VIN of the regulator is –10 V, pin 1 of U9A would be 10 V as U9A is an inverting amplifier with a gain of1. The output of U9B that is a differential amplifier with an attenuation of 1/12 would be as follows:• From Equation 13:

• From Equation 12:

This is VIN + 1. The drop across the LDO is 1 V. Therefore, the drop across the differential amplifier needsto be –0.4 V. The differential amplifier implements

(14)

R47 and C53 form a low-pass filter that removes any ripple present on the input of the LDO. ORing diodesD5, D6, D7, and D8 are used to connect the output with the high-voltage supply. The diodes would blockthe high voltages from reaching the regulators. The control loop is common to all the LDOs, and it ispossible to place many LDOs on the same control loop to share the currents.

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3 Hardware, Testing Requirements, and Test Results

3.1 Required Hardware

Table 3. Connectors, Fuses, and Test Points on Board

REFERENCE DESCRIPTION PINOUT

J4 24-V input 24-VGNDA

J1 VCON + Sync

VCON positiveVCON negative

SyncPGND_A

J2 Positive regulator outputOut_1Reg_POut_2

J3 Negative regulator outputout_1BReg_MOut_2B

J5 +VO SMA +VO

J7 –VO SMA –VO

J6 SMA regulator positive output —J8 SMA regulator positive output —

3.1.1 TIDA-01458 Board ImagesFigure 11 and Figure 12 show the top and bottom views of TIDA-01358 PCB, respectively.

Figure 11. Top View Figure 12. Bottom View

Output Voltage of DC DC Converter

Vol

tage

Dro

p A

cros

s LD

O

0 2 4 6 8 10 12 14 160.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

D002

DC Control

Vol

tage

Out

put

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.00

2

4

6

8

10

12

14

16

D001

Vdc_dcVldoVfinal

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3.2 Testing and ResultsTo test the board, use the following equipment:• 24-V DC input supply rated at 5 A• 5-V variable DC source to provide a control signal to adjust the output voltages• 15-Ω power resistors as well as an electronic load is also needed• 5-V pulses frequency source capable of generating frequencies from 300 to 500 kHz• Oscilloscope (100 MHz)• Spectrum analyzer• Thermal camera

3.2.1 Test 1: Output Voltages as a Function of Control Voltage-Negative Power SupplyA load of 0.8 A is put on the output of the LDO, and the output voltage is observed as a function of DCcontrol voltage.

Figure 13. Output Voltage as Function of DC Control-Negative

3.2.2 Test 2: Voltage Drop Across Negative LDO as a Function of Control VoltageA load of 0.8 A is put on the output of the LDO, and the voltage drop across the LDO is observed forvarying DC-DC converter outputs.

NOTE: Adjust R20 to 14 V.

Figure 14. Voltage Drop Across Negative LDO

Output Voltage of DC DC Converter

Vol

tage

Dro

p A

cros

s LD

O

0 2 4 6 8 10 12 14 160.0

0.2

0.4

0.6

0.8

1.0

1.2

D004

VCONTROL

Vol

tage

Out

put

0.0 0.5 1.0 1.5 2.0 2.50

2

4

6

8

10

12

14

16

D003

Vdc_dcVoVdiode

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3.2.3 Test 3: Output Voltages as a Function of Control Voltage-Positive Power SupplyA load of 0.8 A is put on the output of the LDO, and the output voltage is observed as a function of DCcontrol voltage.

Figure 15. Output Voltage as Function of DC Control-Positive

3.2.4 Test 4: Voltage Drop Across Positive LDO as a Function of Control VoltageA load of 0.8 A is put on the output of the LDO, and the voltage drop across the LDO is observed forvarying DC-DC converter outputs.

NOTE: Adust R17 to 15.47 V.

Figure 16. Voltage Drop Across Positive LDO

Current

Out

put V

olta

ge

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50

2

4

6

8

10

12

14

D006

12 V5 V3.3 V

Load Current

Out

put V

olta

ge

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50

2

4

6

8

10

12

14

D005

12 V5 V3.3 V

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3.2.5 Test 5: Load Regulation Positive DC-DCThe load regulation is given in Figure 17 and Table 4 for different load currents and output voltages.

Figure 17. Load Regulation Positive DC-DC

Table 4. Load Regulation Positive DC-DC Data

CURRENT 12 V 5 V 3.3 V0 12.05 5.00 3.501 11.94 4.85 3.302 12.01 4.85 3.293 12.05 4.86 3.28

3.2.6 Test 6: Load Regulation Negative DC-DC ConverterThe load regulation is given in Figure 18 and Table 5 for different load currents and output voltages.

Figure 18. Load Regulation Negative DC-DC

Table 5. Load Regulation Negative DC-DC Data

CURRENT 12 V 5 V 3.3 V0 11.49 5.05 3.561 11.64 4.95 3.452 11.49 4.86 3.363 11.40 4.76 3.29

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3.2.7 Test 7: Voltage Ripple of Positive Power SupplyLoad current of 0.8 A from the LDO, 12-V output on the LDO

Figure 19. Voltage Ripple at Positive DC-DC Output

Figure 20. Voltage Ripple at Positive LDO Output

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3.2.8 Test 8: Voltage Ripple of Negative Power SupplyThis test shows the output ripple on the DC-DC converter output as well as LDO output with a load of0.8 A on the LDO output.

Figure 21. Voltage Ripple at Negative DC-DC Input

Figure 22. Voltage Ripple at Negative LDO Output

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3.2.9 Test 9: Synchronization Test Positive DC-DCThis test applies an external sync waveform of 3.3-V amplitude to the sync input of the DC-DC converter.The test also observes the switching node of the buck and the sync waveform.

Output voltage for this test is at 12 V with a 2-A load drawn direct on the DC-DC converter.

Figure 23. Sync and Output Switching Waveform of Positive DC-DC at 440 kHz

Figure 24. Sync and Output Switching Waveform of Positive DC-DC at 500 kHz

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3.2.10 Test 10: Synchronization Test Negative DC-DCThis test applies an external sync waveform of 3.3-V amplitude to the sync input of the DC-DC converter.The test also observes the switching node of the buck and the sync waveform.

Output voltage for this test is at –12 V with a 2-A load drawn direct on the DC-DC converter.

Figure 25. Sync and Output Switching Waveform of Negative DC-DC at 440 kHz

Figure 26. Sync and Output Switching Waveform of Negative DC-DC at 500 kHz

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3.2.11 Test 11: Spectrum AnalyzerThe following waveforms are plots on a spectrum analyzer. This test measures the level of the switchingwaveform on the output of the DC-DC converters as well as the LDOs. These plots are for both positiveand negative sections. A load of 1 A is applied on the LDO output and the LDO is maintained at a dropoutof 1 V for both positive and negative circuits.

Figure 27. Spectral Plot of Negative DC-DC Output

Figure 28. Spectral Plot of Negative LDO Output

PSRR = 20 × log(VIN LDO/VOUT LDO)

PSRR = 20 × log(15.8 mv/45.16 µV) = 50.8 dB

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Figure 29. Spectral Plot of Positive DC-DC Output

Figure 30. Spectral Plot of Positive LDO Output

PSRR = 20 × log(VIN LDO/VOUT LDO)

PSRR = 20 × log(8.3 mv/442 µV) = 44.04 dB

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3.2.12 Test 12: Ramp of Control Voltage and Output Voltage LDO-PositiveA signal generator is used to give a ramp waveform on the DC control voltage input. The variation in theoutput voltage on the LDO was seen. A load resistance of 10 Ω was placed on the LDO output.

Figure 31. Ramp Waveform on Control Voltage-Positive DC-DC

A signal generator is used to give a square waveform on the DC control voltage input. The variation in theoutput voltage on the LDO is seen. A load resistance of 10 Ω is placed on the LDO output.

Figure 32. Square Waveform on Control Voltage-Positive DC-DC

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3.2.13 Test 13: Ramp of Control Voltage and Output Voltage LDO-NegativeA signal generator is used to give a ramp waveform on the DC control voltage input. The variation in theoutput voltage on the LDO is seen. A load resistance of 10 Ω is placed on the LDO output.

Figure 33. Ramp Waveform on Control Voltage-Negative LDO

A signal generator is used to give a ramp waveform on the DC control voltage input. The variation in theoutput voltage on the LDO is seen. A load resistance of 10 Ω is placed on the LDO output.

Figure 34. Square Waveform on Control Voltage-Negative LDO

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3.2.14 Test 14: Load Switching of 1-A Load at LDO OutputA 10-Ω load is switched on and off at the LDO output periodically. The output voltage is 9 V.

Figure 35. Load Switching-Positive LDO

A 10-Ω load is switched on and off at the LDO output periodically. The output voltage was –9 V.

Figure 36. Load Switching-Negative LDO-A Figure 37. Load Switching-Negative LDO-B

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3.2.15 Test 15: Temperature TestThis test applies 12 V and 0.8 A on each of the two positive LDOs and –12 V and 0.8 A on each of thetwo negative LDOs.

This test also applies a 0.5-V drop on the positive LDO and a 0.5-V drop across the negative LDO.

Figure 38. Temperature Test

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4 Design Files

4.1 SchematicsTo download the schematics, see the design files at TIDA-01458.

4.2 Bill of MaterialsTo download the bill of materials (BOM), see the design files at TIDA-01458.

4.3 PCB Layout Recommendations

4.3.1 Layout PrintsTo download the layer plots, see the design files at TIDA-01458.

4.4 Altium ProjectTo download the Altium project files, see the design files at TIDA-01458.

4.5 Gerber FilesTo download the Gerber files, see the design files at TIDA-01458.

4.6 Assembly DrawingsTo download the assembly drawings, see the design files at TIDA-01458.

5 Related DocumentationThis reference design did not use any related documentation.

5.1 TrademarksAll trademarks are the property of their respective owners.

6 About the AuthorSANJAY DIXIT is a system architect in the Industrial Systems-Medical Healthcare and Fitness Sector atTexas Instruments, where he is responsible for specifying reference designs.

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