M S Engineering College · 2019. 7. 18. · M S Engineering College Navarathna Agrahara, Sadahalli...

M S Engineering College Navarathna Agrahara, Sadahalli Post

Off. Kempe Gowda International Airport Road,

Bengaluru - 562110, Karnataka, India,

HDL LAB MANUAL

(17ECL58)

Prof. Tejaswini C Associate Professor

Department of Electronics and Communication Engineering

M. S. Engineering College, Bengaluru – 562110

M S Engineering College

Vision

M.S.Engineering College shall blossom into a technical institution of national importance with global network.

Mission

• To be the leading institution in imparting Quality Engineering Education with value systems amongst students to face global challenges.

• To inculcate best engineering practices amongst students through quality education, creativity, innovation and entrepreneurial skills.

• To make the institute to be recognized as among the leading institutions imparting Quality Engineering Education; To produce world class professionals who possess knowledge, skills and necessary values that help them take challenges at a global level

Quality Policy

Striving for Excellence in Quality Engineering Education.

Our commitment to comply with mandatory requirements.

Continually improve the effectiveness and quality management system.

Our commitment to achieve total customer satisfaction by assuring successful completion of the degree with skill sets to solve the Engineering problems

By providing training at all the levels with placement assistance.

Use of modern technology and its conditional up gradation.

Participation of all the stakeholders to meet the expectations.

Department of Electronics and Communication Engineering

Vision

To equip students with strong technical knowledge by logical and innovative thinking in Electronics and Communication Engineering domain to meet expectations of the industry as well as society.

Mission

To educate a new generation of Electronics and Communication Engineers by providing them with a strong theoretical foundation, good design experience and exposure to research and development to meet ever changing and ever demanding needs of the Electronic Industry in particular, along with IT & other inter disciplinary fields in general.

Provide ethical and value based education by promoting activities addressing the societal needs.

To build up knowledge and skills of students to face the challenges across the globe with confidence and ease.

Quality Policy

Our quality policy is to develop an effective source of technical man power with the ability to adapt to an intellectually and technologically changing environment to contribute to the growth of nation with the participative efforts of the management, staff, students and industry while keeping up ethical and moral standards required

Program Outcomes:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice.

7. Environment and sustainability: Understand the impact of the professional engineering Solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.

9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to

engage in independent and life-long learning in the broadest context of technological change.

PSO-Program Specific Objectives

1. An ability to understand the concepts of basic Electronics & Communication Engineering and to apply them to various areas like Signal processing, VLSI, Embedded systems, Communication Systems, Digital & Analog Devices, etc.

2. An ability to solve complex Electronics and Communication Engineering problems, using latest hardware and software tools, along with analytical skills to arrive cost effective and appropriate solutions.

3. Wisdom of social and environmental awareness along with ethical responsibility to have a successful career and to sustain passion and zeal for real-world applications using optimal resources as an Entrepreneur.

Program Educational Objectives

PEO I: To develop the ability among students to understand the concept of core electronics

subjects that will facilitate understanding of new technology.

PEO II: To embed a strong foundation in the engineering fundamentals to solve, analyze and

design real time engineering products.

PEO III: To give exposures to emerging edge technologies, adequate training and

opportunities to work as team on multidisciplinary projects with effective communication

skills and leadership qualities.

HDL LAB

V SEMESTER ELECTRONICS AND COMMUNICATION ENGINEERING

Sub Code

17ECL58

CIE Marks

40

Number of Lecture

Hours/Week

03

SEE Marks 60

RBT Levels L1, L2, L3 Exam Hours 03Hrs

Course Objectives:

This course will enable students to:

Familiarize with the CAD tool to write HDL

programs.

Understand simulation and synthesis of digital

design.

Program FPGAs/CPLDs to synthesize the digital

designs.

Interface hardware to programmable ICs through

I/O ports.

Choose either Verilog or VHDL for a given

Abstraction level.

Note: Programming can be done using any compiler. Download the programs on a

FPGA/CPLD boards such as Apex/Max/Spartan/Sinfi or equivalent and performance testing

may be done using 32 channel pattern generator and logic analyzer apart from verification by

simulation with tools such as Altera /Modelsim or equivalent.

Course Syllabus (As Per VTU CBCS Scheme 2017)

Part–A: PROGRAMMING

1. Write Verilog code to realize all the logic gates

2. Write a Verilog program for the following combinational designs

a. 2 to 4 decoder

b. 8 to 3 (encoder without priority & with priority)

c. 8 to 1 multiplexer.

d. 4 bit binary to gray converter

e. Multiplexer, de-multiplexer, comparator.

3. Write a VHDL and Verilog code to describe the functions of a Full Adder using three

modeling styles.

4. Write a Verilog code to model 32 bit ALU using the schematic diagram shown below

ALU should use combinational logic to calculate an output based on the four bit op-code

input. ALU should pass the result to the out bus when enable line in high, and tri-state the

out bus when the enable line is low. ALU should decode the 4 bit op-code according to the

example given below

OPCODE ALU Operation

1. A+B

2. A-B

3. A Complement

4. A*B

5. A AND B

6. A OR B

7. A NAND B

8. A XOR B

5. Develop the Verilog code for the following flip-flops, SR, D, JK and T.

6. Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and

"any sequence" counters, using Verilog code.

Part–B: INTERFACING (at least four of the following must be covered using

VHDL/Verilog)

1. Write HDL code to display messages on an alpha numeric LCD display.

2. Write HDL code to interface Hex key pad and display the key code on seven segment

display.

3. Write HDL code to control speed, direction of DC and Stepper motor.

4. Write HDL code to accept Analog signal, Temperature sensor and display the data on

LCD or Seven segment display.

5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)

using DAC - change the frequency.

6. Write HDL code to simulate Elevator operation.

Course Outcomes:

At the end of this course, students should be able to:

Write the Verilog /VHDL programs to simulate Combinational circuits in Dataflow,

Behavioral and Gate level Abstractions.

Describe sequential circuits like flip flops and counters in Behavioral description and

obtain simulation waveforms.

Synthesize Combinational and Sequential circuits on programmable ICs and test the

hardware.

Interface the hardware to the programmable chips and obtain the required output.

Conduct of Practical Examination: 1. All laboratory experiments are to be included for practical examination.

2. Strictly follow the instructions as printed on the cover page of answer script for breakup of

marks.

3. Change of experiment is allowed only once and Marks allotted to the procedure part to be

made zero.

LIST OF EXPERIMENTS

CYCLE I Page No MARKS

1 Write Verilog code to realize all the logic gates 9- 18

2 Write a Verilog program for the following combinational designs

a. 2 to 4 decoder

b. 8 to 3 (encoder without priority & with priority)

c. 8 to 1 multiplexer.

d. 4 bit binary to gray converter

e. Multiplexer, de-multiplexer, comparator.

19- 30

3 Write a VHDL and Verilog code to describe the functions of a

Full Adder using three modeling styles. 31- 34

4 Write a Verilog code to model 32 bit ALU 35 - 37

5 Develop the Verilog code for the following flip-flops, SR, D, JK

and T. 38 - 44

6 Design a 4 bit binary, BCD counters (Synchronous reset and

Asynchronous reset ) and “any sequence” counters, using Verilog

code.

45 - 50

CYCLE II

1 Write HDL code to display messages on an alpha numeric LCD display.

51 - 53

2 Write HDL code to control speed, direction of DC and Stepper

motor.

Write HDL code to interface Hex key pad and display the key

code on seven segment display.

54 - 56

3 Write HDL code to generate different waveforms (Sine, Square,

Triangle, Ramp etc.,) using DAC - change the frequency. 57 - 63

4 Write HDL code to simulate Elevator operation.

64 - 68

AVERAGE

Scheme of Evaluation

IA Evaluation

Record

maintenance

(weekly submission)

Conduction of Lab Internals Total

Write up Execution of the

required Result

Viva

20M 5M 10M 5M 40M

HDL Lab:17ECL58 2019-20

Dept. of ECE M.S. Engineering College Page 1

OVERVIEW OF HDL LAB

HDL

In electronics, a hardware description language or HDL is any language from a class of

Computer languages for formal description of electronic circuits. It can describe the circuit's

operation, its design and organization, and tests to verify its operation by means of simulation

HDLs are standard text-based expressions of the spatial, temporal structure and behavior of

electronic systems. In contrast to a software programming language, HDL syntax, semantics

include explicit notations for expressing time and concurrency, which are the attributes of

hardware. Languages whose only characteristic is to express circuit connectivity between a

hierarchies of blocks are properly classified as netlist languages.

HDLs are used to write executable specifications of some piece of hardware. A simulation

program, designed to implement the underlying semantics of the language statements,

coupled with simulating the progress of time, provides the hardware designer with the

ability to model a piece of hardware before it is created physically. It is this execute ability

that gives HDLs the illusion of being programming languages. Simulators capable of supporting

discrete-event and continuous-time (analog) modeling exist, and HDLs targeted for each are

available.

It is certainly possible to represent hardware semantics using traditional programming languages

such as C++, although to function such programs must be augmented with extensive and

unwieldy class libraries. Primarily, however, software programming languages function as a

hardware description language

Using the proper subset of virtually any language, a software program called a synthesizer

can infer hardware logic operations from the language statements and produce an equivalent

netlist of generic hardware primitives to implement the specified behavior. This typically

requires the synthesizer to ignore the expression of any timing constructs in the text.

The two most widely-used and well-supported HDL varieties used in industry are

VHDL (VHSIC HDL)

Verilog

HDL Lab:17ECL58 2019-20


VHDL

VHDL (Very High Speed Integrated Circuit Hardware Description Language) is

commonly used as a design-entry language for field-programmable gate arrays and application-

specific integrated circuits in electronic design automation of digital circuits.

VHDL is a fairly general-purpose language, and it doesn’t require a simulator on which to run

the code. There are a lot of VHDL compilers, which build executable binaries. It can read and

write files on the host computer, so a VHDL program can be written that generates another

VHDL program to be incorporated in the design being developed. Because of this general-

purpose nature, it is possible to use VHDL to write a test bench that verifies with the user,

and compares results with those expected. This is similar to the capabilities of the Verilog

language

VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as

Xilinx) to produce the RTL schematic of the desired circuit. After that, the generated schematic

can be verified using simulation software (such as ModelSim) which shows the waveforms of

inputs and outputs of the circuit after generating the appropriate test bench. To generate an

appropriate test bench for a particular circuit or VHDL code, the inputs have to be defined

correctly. For example, for clock input, a loop process or an iterative statement is required.

The key advantage of VHDL when used for systems design is that it allows the behavior of the

required system to be described (modeled) and verified (simulated) before synthesis tools

translate the design into real hardware (gates and wires). When a VHDL model is

translated into the "gates and wires" that are mapped onto a programmable logic device such

as a CPLD or FPGA, then it is the actual hardware being configured, rather than the

VHDL code being "executed" as if on some form of a processor chip.

Both VHDL and Verilog emerged as the dominant HDLs in the electronics industry while

older and less-capable HDLs gradually disappeared from use. But VHDL and Verilog share

many of the same limitations: neither HDL is suitable for analog/mixed-signal circuit

simulation. Neither possesses language constructs to describe recursively-generated logic

structures

HDL Lab:17ECL58 2019-20


Verilog

Verilog is a hardware description language (HDL) used to model electronic systems. The

language supports the design, verification, and implementation of analog, digital, and mixed -

signal circuits at various levels of abstraction

The designers of Verilog wanted a language with syntax similar to the C programming

language so that it would be familiar to engineers and readily accepted. The language is case-

sensitive, has a preprocessor like C, and the major control flow keywords, such as "if"

and "while", are similar. The formatting mechanism in the printing routines and language

operators and their precedence are also similar

The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces

to define a block of code. The concept of time, so important to a HDL won't be found in C The

language differs from a conventional programming language in that the execution of statements

is not strictly sequential. A Verilog design consists of a hierarchy of modules are defined

with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires

and registers. Concurrent and sequential statements define the behavior of the module by

defining the relationships between the ports, wires, and registers Sequential statements are

placed inside a begin/end block and executed in sequential order within the block. But all

concurrent statements and all begin/end blocks in the design are executed in parallel,

qualifying Verilog as a Dataflow language. A module can also contain one or more instances

of another module to define sub-behavior

A subset of statements in the language is synthesizable. If the modules in a design contains a

netlist that describes the basic components and connections to be implemented in hardware only

synthesizable statements, software can be used to transform or synthesize the design into the net

list may then be transformed into, for example, a form describing the standard cells of an

integrated circuit (e.g. ASIC) or a bit stream for a programmable logic device (e.g. FPGA).

HDL Lab:17ECL58 2019-20


Design using HDL

The vast majority of modern digital circuit design revolves around an HDL

description of the desired circuit, device, or subsystem.

Most designs begin as a written set of requirements or a high-level architectural diagram.

The process of writing the HDL description is highly dependent on the designer's diagram.

The process of writing the HDL description is highly dependent on the designer's

background and the circuit's nature. The HDL is merely the 'capture language'–often begin

with a high-level algorithmic description such as MATLAB or a C++ mathematical model

Control and decision structures are often prototyped in flowchart applications, or entered in a

state-diagram editor. Designers even use scripting languages (such as PERL) to automatically

generate repetitive circuit structures in the HDL language. Advanced text editors (such as

PERL) to automatically generate repetitive circuit structures in the HDL language. Advanced

text editors (such as Emacs) offer editor templates for automatic indentation, syntax-

dependent coloration, and macro-based expansion of entity/architecture/signal declaration.

As the design's implementation is fleshed out, the HDL code invariably must undergo code

review, or auditing. In preparation for synthesis, the HDL description is subject to an array

of automated checkers. The checkers enforce standardized code guidelines, identifying

ambiguous code construct before they can cause misinterpretation by downstream synthesis, and

check for common logical coding errors, such as dangling ports or shorted outputs.

In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis

tool has mapped the HDL description into a gate net list, this net list is passed off to the back -

end stage. Depending on the physical technology (FPGA, ASIC gate-array, ASIC standard-

cell), HDLs may or may not play a significant role in the back-end flow. In general, as the

design flow progresses toward a physically realizable form, the design database becomes

progressively more laden with technology-specific information, which cannot be becomes

progressively more laden with technology-specific information, which cannot be stored in a

generic HDL-description. Finally, a silicon chip is manufactured.

HDL Lab Manual 2019-20


HDL Programming using Xilinx ISE design suite

Xilinx ISE means Xilinx® Integrated Software Environment (ISE), i.e programmable logic

design tool in electronics industry. This Xilinx ® design software suite allows taking

design from design entry through Xilinx device programming. The ISE Project Navigator

manages and processes design through several steps in the ISE design flow. These steps are

Design Entry, Synthesis, Implementation, Simulation/Verification, and Device

Configuration. Xilinx is one of most popular software tool used to synthesize

VHDL/Verilog code.

INTRODUCTION TO FPGA (FIELD PROGRAMMABLE GATE ARRAY)

FPGA contains a two dimensional arrays of logic blocks and interconnections between

logic blocks. Both the logic blocks and interconnects are programmable. Logic blocks

are programmed to implement a desired function and the interconnects are programmed

using the switch boxes to connect the logic blocks.

To implement a complex design (CPU for instance), the design is divided into small sub

functions and each sub function is implemented using one logic block. All the sub

functions implemented in logic blocks must be connected and this is done by

programming the interconnects.

INTERNAL STRUCTURE OF AN FPGA

FPGAs, alternative to the custom ICs, can be used to implement an entire System On one

Chip (SOC). The main advantage of FPGA is ability to reprogram. User can reprogram



an FPGA to implement a design and this is done after the FPGA is manufactured. This

brings the name “Field Programmable.”

Custom ICs are expensive and takes long time to design so they are useful when

produced in bulk amounts. But FPGAs are easy to implement within a short time with

the help of Computer Aided Designing (CAD) tools.

XILINX FPGA

Xilinx logic block consists of one Look Up Table (LUT) and one Flip-flop. An LUT is

used to implement number of different functionality. The input lines to the logic block go

into the LUT and enable it. The output of the LUT gives the result of the logic function

that it implements and the output of logic block is registered or

unregistered output from the LUT.

4-INPUT LUT BASED IMPLEMENTATION OF LOGIC BLOCK.

Xilinx LUT

Part –A Software Experiments

Procedure : 1. Double click on Xilinx Design Suite 13.1 Icon.

2. Select new project in file menu.

3. Enter the project name and location as shown below and press Next .

4. Select the Family, Device, Package and speed as per the requirements and press Next .



5. Create a new source by using new source icon or right click on the device/project folder

to create new source.

6. Select the appropriate source type and enter the file name in New Source Wizard

window and press Next .

7. Enter the architecture name – dataflow/behavioral/structural, port name and select the

direction. This will create .v source file. Press Next and finish the initial project creation.

8. Write complete VHDL/Verilog code implementation and save.

9. Click on implementation and check for syntax using “Check syntax” option under

synthesize tab. If any error, edit and correct VHDL/Verilog code and repeat check syntax

until zero errors.

10. Double click on ISIM simulator by selecting simulation mode to complete the

functional simulation of your design.

Part –B Hardware Interfacing

Procedure :

1. Repeat the steps 1 to 10 from the procedure for software experiments .

2. Make the connection between appropriate FRC’s of the FPGA board and the DIP switch

connector of the GPIOcard-2/

3. Make the connection between appropriate FRC’s of the FPGA board and the LED

connector of the GPIOcard-2.

4. Right click on the device and select “New Source”, Select the option “Implementation

constraint File” and provide the file name and click on next and then hit Finish. This

creates an .ucf file.

6. Double click on the added .ucf file and assign the pin numbers to inputs and outputs

referring to FRC sheet using the syntax as shown.Save the constraint file.

7. Connect USB programmer for FPGA between FPGA kit and USB port of your

computer.

8. Go to process window, select the VHDL or Verilog file and click on “configure target

device”.

9. Click OK for the warning below.

10. Select boundary scan to impact the target device.

11. Right click on the impact window to establish a connection between system and FPGA

by selecting “INTIALIZE CHAIN” option.

12. Both prom device and FPGA device gets identified after step 10 and bypass the

procedure to select only FPGA which of main interest.

13. Now choose device 2(FPGA XC3S400) and hit ok to complete the impact.

14. Now right click on the device to assign a new .bit file by selecting an option “ASSIGN

NEW CONFIGURATION FILE”.



15. Select the corresponding .bit file from the project folder and hit Open .

16. Press ‘No’ on the following dialog box.

17. Finally right click on the device(XC3S400) and implement the program by choosing an

option “PROGRAM”

18. Once again select the FPGA device (XC3S400) by clicking ok and now the program

will be identified and succeeded.



Experiment No 1

Realize all the logic gates Using Verilog code

Objective: - To write and simulate the Verilog code to realize the basic logic gates and to check

the functionality by simulating the design .

Theory :-

Logic gates are the basic building blocks of any digital system. It is an

electronic circuit having one or more than one input and only one output. The relationship

between the input and the output is based on a certain logic. Based on this, logic gates are

named as AND gate, OR gate, NOT gate



Verilog Code:

1.a) Realizing AND gate: module and_gate (a,b,y);

input a,b ; //defines two input port

output y; // defines one output port

and g1(y,a,b); /*gate declaration with predefined keyword or representing

logic OR, g1 is optional user defined gate identifier */

endmodule

Functional table:

Input

A

Input

B

Output

Y

0 0 0

0 1 0

1 0 0

1 1 1

Simulation Results:-

1.b) Realizing OR gate:



Verilog Code :

//Verilog module for OR gate

module or_gate(a,b,y);

input a,b; //defines two input port

output y; // defines one output port

or g1(y,a,b); /*gate declaration with predefined keyword or representing

logic OR, g1 is optional user defined gate identifier */

endmodule

Functional table:

Input

A

Input

B

Output

Y

0 0 0

0 1 1

1 0 1

1 1 1




1.c). Realizing XOR gate:

Verilog Code :

module xor_gate(y,a,b);

input a,b;

output y;

xor g1(y,a,b);

endmodule

Functional table:

Input

a

Input

b

Output

c

0 0 0

0 1 1

1 0 1

1 1 0

Simulation Results



1.d) NOT GATE:

architecture behavioral of not1 is

begin

c<=not a ;

end behavioral;

Verilog Code: module not_gate(a,y);

input a;

output y;

not g1(y,a);

endmodule

Functional table:

Input

A

Output

c

0 1

1 0

Simulation Results



1. e) NAND GATE:

Verilog module for NAND gate

module nand_gate(a,b,y);

input a,b;

output y;

nand g1(y,a,b);

endmodule

Functional table:

Input

A

Input

B

Output

c

0 0 1

0 1 1

1 0 1

1 1 0

Simulation Results



1. f) NOR GATE :

Verilog Code :

module nor_gate(y,a,b);

input a,b;

output y;

nor g1(y,a,b);

endmodule

Functional table:

Input

A

Input

B

Output

c

0 0 0

0 1 0

1 0 0

1 1 1

Simulation Results



1.g) XNOR GATE:

Verilog Code :

module xnor_gate(y,a,b);

input a,b;

output y;

xnor g1(y,a,b);

endmodule

Functional table:

Input

A

Input

B

Output

c

0 0 1

0 1 0

1 0 0

1 1 1

Simulation Results



Verilog Code to Realize all Logic Gates :

Block Diagram

Verilog Code :

module gates(a_in, b_in,

not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op);

input a_in,b_in;

output

not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op;

assign not_op= ~a_in;

assign and_op=a_in&b_in;

assign nand_op=~(a_in&b_in);

assign or_op=a_in|b_in;



assign nor_op=~(a_in|b_in);

assign xor_op=a_in^b_in;

assign xnor_op=~(a_in^b_in);

endmodule

Results:-

Written and simulated the HDL model for Basic logic gates and verified the

response with the truth table and concluded that the basic logic gates design is

working fine.



Experiment No 2:

Realize the following combinational circuits using Verilog Code

(a). 2 to 4 decoder.

(b) 8to 3 encoder without priority &

(c) 8 to 3 encoder with priority) .

(d) 8 to 1 Multipexer

(e) 4 bit binary to gray converter .

(f) Multiplexer, De-Multiplexer, Comparator

Objective: -

To write and simulate the HDL code to realize the Combinational gates and to

check the functionality by simulating the design ISE Simulator.

2 (a). 2 to 4 decoder:

Theory:

A decoder is a multiple input, multiple output logic circuit that converts coded inputs into

coded outputs where the input and output codes are different. The enable inputs must be

ON for the decoder to function, otherwise its outputs assumes a ‘disabled’ output code

word. Decoding is necessary in applications such as data multiplexing, seven segment

display and memory address decoding.

Verilog Code :

module decoder(a, y);

input [1:0] a;

output [3:0] y;

reg [3:0] y;

always @ (a)

case(a)

2’b00: y<= 4’b1110;

2’b01: y<= 4’b1101;

2’b10: y<= 4’b1011;

2:4 Decoder a(0)

a(1)

y(2)

y(1)

y(0)

y(3)



2’b11: y<= 4’b0111;

endcase

endmodule

Functional table:

Input : a

(1downto 0)

Output :

y(1downto 0)

00 1110

01 1101

10 1011

11 0111




2.(b) 8 to 3 encoder without priority:

Theory: An Encoder is a combinational circuit that performs the reverse operation of

Decoder.It has maximum of 2^n input lines and 'n' output lines, hence it encodes the

information from 2^n inputs into an n-bit code. Encoders are used to translate rotary or

linear motion into a digital signal. The priority encoder is the binary representation of the

original number starting from zero of the most significant input bit. They are often used to

control interrupt requests by acting on the highest priority encoder. If two or more inputs

are given at the same time, the input having the highest priority will take precedence.

Verilog Code :

module encoder (din, dout);

input [7:0] din;

output [2:0] dout;

reg [2:0] dout;

always @(din)

begin

if (din ==8'b00000001) dout=3'b000;

else if (din==8'b00000010) dout=3'b001;




else if (din ==8'b00100000) dout=3'b101;



else dout=3'bX ;

end

endmodule

Functional table:

Enable

(input)

din: input

(7 downto 0);

dout: output

(2 downto 0)

0 xxxxxxxx zzz

1 00000001 000

1 00000010 001

1 00000100 010

1 00001000 011

1 00010000 100

1 00100000 101

1 01000000 110

1 Others 111

https://en.wikipedia.org/wiki/Interrupt_request

https://en.wiktionary.org/wiki/precedence




2 (c). 8 to 3 priority encoder with priority

Verilog Code :

module encoder (din, dout);

input [7:0] din;

output [2:0] dout;

reg [2:0] dout;

always @(din)

begin

if (din ==8'b00000001) dout=3'b000;

else if (din==8'b0000001 X) dout=3'b001;

else if (din==8'b000001 XX) dout=3'b010;

else if (din==8'b00001XXX) dout=3'b011;

else if (din==8'b0001XXXX) dout=3'b100;

else if (din ==8'b001XXXXX) dout=3'b101;

else if (din==8'b01XXXXXX) dout=3'b110;

else if (din==8'b1XXXXXXX) dout=3'b111;

else dout=3'bX;

end

endmodule



Functional table:

Enable (input) din: input (7

downto 0);

dout: out

(2 downto 0)

1 xxxxxxxx zzz

0 00000001 000

0 0000001x 001

0 000001xx 010

0 00001xxx 011

0 0001xxxx 100

0 001xxxxx 101

0 01xxxxxx 110

0 Others 111


2 (d) 8 to 1 Multiplexer

Theory : A multiplexer (or mux) is a device that selects between several analog or digital

input signals and forwards it to a single output line. A multiplexer is also called a data

selector. A multiplexer of inputs has select lines, which are used to select which input line

to send to the output.[2]

Multiplexers are mainly used to increase the amount of data that

can be sent over the network within a certain amount of time and bandwidth.

https://en.wikipedia.org/wiki/Analog_signal

https://en.wikipedia.org/wiki/Digital_signal_(electronics)

https://en.wikipedia.org/wiki/Multiplexer#cite_note-2

https://en.wikipedia.org/wiki/Computer_networks

https://en.wikipedia.org/wiki/Bandwidth_(signal_processing)



Verilog Code :

module mux8_1(i_in, sel, y_out); input [7:0]

a_in;

input [2:0] sel;

output y_out;

reg y_out;

always@ (i_in,sel )

begin

case (sel) 3'b000:y_out=i_in[0];

3'b001: y_out=i_in[1];

3'b010: y_out=i_in[2];

3'b011: y_out=i_in[3];

3'b100: y_out=i_in[4];

3'b101: y_out=i_in[5];

3'b110: y_out=i_in[6];

3'b111: y_out=i_in[7];

default: y_out =3'b000;

endcase

end

endmodue

Functional table:

a_in : in std_logic_vector(7 downto 0) :XXXXXXXX

sel y_out

000 a[0]

001 a[1]

010 a[2]

011 a[3]

100 a[4]

101 a[5]

110 a[6]

others a[7]




2 (e). 4 bit binary to gray converter

Block Diagram

Theory :

The “Reflected binary code”, also known as Gray code after Frank Gray. In a Gray code

the adjacent numbers differ by one symbol. The original name reflected binary code is

derived from the fact that the second half of the values are equivalent to the first half in

reverse order, except for the highest bit, which is inverted.



Applications: Some sensors send information in Gray code. These must be converted to

binary in order to do arithmetic operations. Gray codes are widely used to facilitate error

correction in digital communications.

Verilog Code :

module bintogray(b_in, g_op);

input [3:0] b_in;

output [3:0] g_op;

assig_opn g_op[3]=b_in[3];

assig_opn g_op[2]=b_in[3] ^ b_in[2];



endmodule

Functional table:

Decimal Binary Gray

0 0000 0000

1 0001 0001

2 0010 0011

3 0011 0010

4 0100 0110

5 0101 0111

6 0110 0101

7 0111 0100

8 1000 1100

9 1001 1101

10 1010 1111

11 1011 1110

12 1100 1010

13 1101 1011

14 1110 1001

15 1111 1000




2 (f). 4:1 Demultiplexer

Theory : A demultiplexer (or de mux) is a device taking a single input and selecting

signals of the output of the compatible mux, which is connected to the single input, and a

shared selection line. A multiplexer is often used with a complementary demultiplexer on

the receiving end



Verilog code :

module demux(a_in, sel, y_out);

input a_in;

input [1:0] sel;

output [3:0] y_out;

reg [3:0] y_out;

alwaysel @ (a_in or sel)

casele(sel)

2’b00: y_out(0)=a_in;

2’b01: y_out(1)=a_in;

2’b10: y_out(2)=a_in;

2’b11: y_out(3)=a_in;

endcasele

endmodule

Functional Table:

a_in= 0/1

sel : (in) y_out (output)

00 y_out(0)

01 y_out(1)

10 y_out(2)

11 y_out(3)

Simulation results:



2 (g) Comparator

Verilog Code :

module comparator(a_in, b_in, L_op,g_op,e_op);

input [3:0] a_in;

input [3:0] b_in;

output L_op;

output g_op;

output e_op;

reg L_op,g_op,e_op;

always @ (a_in,b_in)

begin

if (a_in<b_in)

L_op=1'b1;

else

L_op=1'b0;

if (a_in>b_in)

g_op=1'b1;

else

g_op=1'b0;

if (a_in==b_in)

e_op=1'b1;

else

e_op=1'b0;

end

endmodule



Functional Table:

a_in:input

(3downto0)

b_in:input

(3downto0) e_op g_op L_op

1111 1100 0 1 0

1111 1111 1 0 0

0000 1111 0 0 1




Experiment No 3:

Realize HDL and Verilog model for Full adder using three different modeling

styles.

Objective : To write and simulate the HDL model for Full adder using three different modeling

styles

Theory :

Full adder is the basic combinational arithmetic block used in digital design the

purpose of this model is to take three inputs (input A, input B and carry in) and

provide the two outputs (sum and carryout).sum will be the arithmetic addition of

all the three inputs and the carryout will be the overflow of value in the sum.

Block Diagram :

Logical Expressions:

sum = a_in xor b_in xor c_in;

carry= (a_in.b_in) + (b_in.c_in)+(a_in.b_in);

Truth Table :



3 (a). Data Flow description

VHDL Code :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity fulladder is

port (a_in, b_in, c_in: in std_logic;

sum, carry: out std_logic);

end fulladder;

architecture dataflow of fulladder is

begin

sum <= a_in xor b_in xor c_in;

carry<= (a_in and b_in) or (b_in and c_in) or (a_in and

b_in);

end dataflow;

Verilog Code :

module fulladder(a_in, b_in, c_in, sum, carry);

input a_in, b_in,c_in;

output sum, carry;

assign sum = a_in^b_in^c_in;

assign carry = (a_in & b_in) | (b_in & c_in) | (a_in & c_in);

endmodule

3(b). Behavioral description

VHDL Code :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity fulladder is

port (abc: in std_logic_vector(2 downto 0);

sum, carry: out std_logic);

end fulladder;

architecture behavioral of fulladder is

begin



process(abc)

begin

case (abc) is

when”000”=>sum<=’0’; carry<=’0’;

when”001”=>sum<=’1’; carry<=’0’;

when”010”=>sum<=’1’; carry<=’0’;

when”011”=>sum<=’0’; carry<=’1’;

when”100”=>sum<=’1’; carry<=’0’;

when”101”=>sum<=’0’; carry<=’1’;

when”110”=>sum<=’0’; carry<=’1’;

when”111”=>sum<=’1’; carry<=’1’;

when others=>null;

end case;

Verilog Code :

module fulladder(abc, sum, carry);

input [2:0] abc;

output sum,carry;

reg sum,carry;

always@(abc)

begin

case (abc)

3’b000:begin sum=1’b0; carry=1’b0;end




3’b100:begin sum=1’b1; carry=1’b0end




endcase

end

endmodule



3(c). Structural Description

Block diagram : (gate level description)

Verilog code

module fa(a_in, b_in, c_in, sum, carry);

input a_in, b_in, c_in;

output sum, carry;

wire s1, s2, s3;

xor x1 (s1, a_in, b_in);

and a1 (s2, a_in, b_in);

xor x2 (sum, s1, c_in);

and a2 (s2, s1, c_in);

or o1 (carry, s2, s3);

endmodule




Experiment No 4:

Realize Verilog model for 32-bit ALU using the schematic diagram shown below

with input A [31:0] and B [31:0].

Objective: - To write and simulate the 32-bit ALU considering the A [31:0] and B [31:0] as two

inputs and to check the functionality by simulating the design using Mentor

graphics Modelsim Simulator.

Theory: -

Arithmetic and Logic Unit (ALU) is the building unit in all the processor. it

performs all the arithmetic and logical operations by taking input.It can be

implemented by using some control inputs to realize all possible arithmetic and

logical operations in a single model a. This consists of the operations like

Arithmetic operations:

Addition

Subtraction

Multiplication

Logical operations:

AND

OR

NAND

XOR

NOT



Functional Table:

Opcode ALU Operation

0 A+B addition

1 A-B Subtraction

2 ~A A Invert

3 A*B multiplication

4 A AND B logical AND

5 A OR B logical OR

6 A NAND B logical NAND

7 A XOR B logical XOR

Expected Response Table:

Input

A=1,B=1

Opcode

000

0001 010 011 100 101 110 111

Output Y 2 0 0 1 1 1 0 0

Verilog Code :

module alu(a, b, opcode, y);

input [31:0] a,b;

input [3:0] opcode;

output [31:0] y;

reg [31:0] y;

always @ (a or b or opcode)

begin

case (opcode )

4'b0000: y=a+b;

4'b0001: y=a-b;

4'b0010: y=~a;

4'b0011: y=a &b;

4'b0100: y=a | b;

4'b0101: y=~(a & b);

4'b0110: y=~(a | b);

4'b0111: y=a ^ b;

4'b1000: y=~(a ^ b);

4'b1001: y=a;

4'b1010: y=32'b00000000000000000000000000000000;

4'b1011: y=32'b11111111111111111111111111111111;

4'b1100: y=a+1;

4'b1101: y=a-1;



4'b1110: y=b+1;

4'b1111: y=b-1;

default: y=32'bX;

endcase

end

endmodule


Results:-

Written and simulated the HDL model for the 32-bit ALU and verified the

simulation results for functional correctness by comparing the .



Experiment No. 5:

Objective: - Develop and simulate the Verilog code for the following flip-flops

SR

JK

D

T

Theory: -

SR flip-flop: A SR flip-flop is the simplest possible memory element. The SR flip flop has

two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.

D flip-flop: This is a flip-flop with a delay (D) equal to exactly equal to one cycle of the

clock. The defect with SR FF is the indeterminate output when the data inputs at S and R

are 1. In order to avoid this the input to R is through an inverter from S so that the input to

R is always the complement of S and never same. The S input is redesignated as D.

JK flip-flop: The JK flip-flop is called a “universal flip flop” because the other flip flops

like D, SR, T can be derived from it. The “racing or race around condition” takes place in a

JK FF when J=1 and K=1 and clock=1.

T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and

K.

S-R flip-flop Truth table:

Block diagram :



Truth Table :

Verilog Code :

module sr_ff(sr, clk, rst, q, qb);

input [1:0]sr;

input rst, clk;

output q,qb;

reg q,qb;

always @ (posedge clk)

begin

if (rst==1)

begin

q=0;

qb=1;

end

else

case (sr)

2'b00: begin q=q; qb=qb; end

2'b01: begin q=0; qb=1; end


2'b11: begin q=1'bx; qb=1'bx; end

default:begin end

endcase

end

endmodule



Simulation Result of SR flip-flop:-

D Flip Flop :

Block diagram:

Truth Table




J-K flip-flop :

Block diagram :



Truth table:

Verilog Code :

module jk_ff(j, k, clk, reset, q, qb);

input [1:0]jk;

input clk,rst;

output q, qb;

reg q, qb;

reg [22:0] div;

reg clkdiv;


begin

div = div+1'b1;

clkdiv = div[22];

end

always @ (posedge clkdiv)

begin

if(rst==1)

begin

q=0;

qb=1;

end

else

case (jk)

2'b00: begin q=q; qb=qb; end



2'b11: begin q=~(q); qb=~(qb); end

default: begin end



endcase

end

endmodule

Simulation Result of JK flip-flop:-

T flip-flop :

Block diagram



Truth Table :

Verilog Code :

module t_ff (t, clk, rst, q, qb);

input t, clk, rst;

output q, qb;

reg q,qb;


begin

div = div+1'b1;

clkdiv = div[22];

end

always @ (posedge clkdiv)

begin

if (rst==1)

begin

q=0;

qb=1;

end

else

case ( t)

1’b0:begin q=q; qb=qb; end

1’b1:begin q=~(q); qb=~(qb); end

default: begin end

endcase

end

endmodule

Results:-

Developed the HDL code for flip flops SR,JK,D,T and simulated the designs and

verified the truth table of all the flip-flops with simulation Results.



Experiment No 6:

Objective: - Design and simulate the Verilog code for a 4-bit binary, BCD counters with

Synchronous Reset

Asynchronous Reset

Any sequence

Theory: -

Basically the counters are the sequential blocks where in we use to generate a

sequence of numbers with respect to the clock counts which is a control signal provided for

the design. Counter can count and store the number of time any particular event or process

have occurred, depending on a clock signal. Counters can be modeled of synchronous or

Asynchronous types based on the clock applied for the design to execute the logic,

Asynchronous counters are those whose output is free from the clock signal. Because the

flip flops in asynchronous counters are supplied with different clock signals, there may be

delay in producing output. Counters can start counting not only from the zero, In fact it can

be initiated to any random value to make a count from some non-zero number and it is also

possible to increment the counter with more than one in one clock period.

6 (a). 4-bit Binary counter with Synchronous Reset

Block diagram :

Verilog Code :

module syncnt(clk, rst, bin_out)

input clk, rst;

output [3:0] bin_out;

reg [3:0] bin_out;


begin

if(rst) begin

bin_out<=4‘b0;

end

else

bin_out<=bin_out +1;

end

endmodule




6 (b). 4 - bit Binary Counter with Asynchronous reset :

Block diagram:

Verilog Code :

module asyncnt(clk, rst, bin_out);

input clk, rst;

output [3:0] bin_out;

reg [3:0] bin_out;

always @ (posedge clk or posedge rst)

begin

if(rst) begin

bin_out<=4'b0;

end



else

bin_out<=bin_out+1;

end

endmodule


6 (c). 4-bit BCD counter with Synchronous reset :

Block diagram :



Verilog Code :

module syncnt_bcd(clk, rst, bcd_out);

input clk, rst;

output [3:0] bcd_out;

reg [3:0] temp;

assign bcd_out=temp;


begin

if(rst)

begin

temp<=4'b0000;

end

else

begin

temp<=temp+1'b1;

if(temp==4'b1001)

temp<=4'b0000;

end

end

endmodule

Simulation Results



6 (d). 4-bit BCD counter with Asynchronous reset :

Block diagram :

Verilog Code :

module Asyncnt_bcd(clk, rst, bcd_out);

input clk, rst;

output [3:0] bcd_out;

reg [3:0] temp;

assign bcd_out=temp;

always @ (posedge clk or posedge rst)

begin

if(rst)

begin

temp<=4'b0000;

end

else

begin

temp<=temp+1'b1;

if(temp==4'b1001)

temp<=4'b0000;

end

end

endmodule

inputs

clk

BCD

Asynchronous

Reset Counter

bcd_out

outputs

rst



Simulation Results :

Result: - Designed and simulated the HDL code for a 4-bit binary, BCD counters with

Synchronous Reset

Asynchronous Reset

And verified the simulation Results for the counting sequence and the

Synchronous and Asynchronous counting.



Hardware Programs

Experiment No 1:-

Write, Implement and Interface the HDL Design to display a message on seven

segment Display and LCD display by accepting input from Hex key pad.

Objective: - To Write, Implement and Interface the HDL Design on FPGA to display a message

on seven segment Display and LCD display by accepting input from Hex key pad.

Theory: -

FPGA (Field Programmable Gate Array) is the prototyping device used very rapidly

in the Industry to check the most of the applications now a day. It is made up of Basic

block called Basic Logic Element (BLE). Which consists of LUT (Look Up Table), Mux

(Multiplexer), and then a Register element (Flip-flop).Because of its fast computing

capability most of the advanced applications will be implemented on FPGA. Once the

Design is programmed in a Bit format onto FPGA using implementing software (Xilinx),

now FPGA will act as a prototype of the design. Since it holds some functionality it can

drive some functionality onto external hard ware with help of set of I/O (input and output)

pins and some control pins available on FPGA, We call this as interfacing of FPGA with

external hard ware like LCD (Liquid Crystal Display) and Seven Segment Display, DC

Motor, Stepper Motor, DAC (Digital to analog converter), Elevator demo board.

VHDL Code:-

entity lcda is

Port ( plcddat : out STD_LOGIC_VECTOR (7 downto 0);

plcdrs,plcdrw,plcden : out STD_LOGIC;

pclk100k : in STD_LOGIC);

end lcda;

architecture Behavioral of lcda is

signal sclkdiv: STD_LOGIC_VECTOR (15 downto 0);

signal sdspclk: STD_LOGIC;

signal tchrl: character;

constant mystr:string:="MSEC";

begin

process(pclk100k)

begin

if(rising_edge(pclk100k))then

sclkdiv<=sclkdiv+1;



end if;

sdspclk<=sclkdiv(15);

plcden<=sclkdiv(15);

end process;

process(sdspclk)

variable vdspseq : integer range 0 to 15;

variable vdspnum : integer range 0 to 15;

variable i1 : integer;

type tlcdtyp is array(0 to 15) of std_logic_vector(7 downto 0);

constant tlcddat :tlcdtyp :=("00111000","00001110","00000010","00000001",

"01000001","01000100","01001101","00100000",

"01000001","01000100","01001101","00100000",

"01000001","01000100","01001101","00100000");

begin

if(falling_edge(sdspclk)) then

vdspseq := vdspseq+1;

end if;

if(falling_edge(sdspclk)) then

if(vdspseq>3) then

vdspnum := vdspnum+1;

end if;

end if;

if (vdspseq<4) then

plcddat<=tlcddat(vdspseq);

vdspnum := 1;

else

plcddat<=tlcddat(vdspseq);

tchrl<=mystr(vdspnum);

plcddat<=std_logic_vector(to_unsigned(character'pos(tchrl),8));

end if;

plcdrw<='0';

if (vdspseq<=4) then

plcdrs<='0';

else

plcdrs<='1';

end if;



end process;

end Behavioral;

Results:-

Written, Implemented the HDL Design on FPGA and Interfaced with seven

segment Display and LCD display and displayed the message by accepting input

from Hex key pad. Found the hard ware working and compared the output.



Experiment No 2

Write, Implement and Interface the HDL Design to control the speed and direction

of DC and Stepper motor.

Objective:

To Write, Implement and Interface the HDL Design to control the speed and

direction of DC and Stepper motor.

2 (a). VHDL Code for controlling the operation of a DC Motor :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dc5 is

port(psw:in std_logic_vector(2 downto 0);

dcm:out std_logic;

clk:in std_logic);

end dc5;

architecture Behavioral of dc5 is

signal sclkdiv:std_logic_vector(11 downto 0);

begin

process (clk)

begin

if(rising_edge(clk))

then

sclkdiv<=sclkdiv+1;

end if;

if(sclkdiv="101110111000")

then

sclkdiv<="000000000000";

end if;

end process;

process(psw,sclkdiv)

variable vdcm:bit;



begin

if(sclkdiv="000000000000")then

vdcm:='1';

end if;

if(psw="000" and sclkdiv="000111110100")then vdcm:='0';

elsif(psw="001" and sclkdiv="001100100000")then vdcm:='0';







end if;

if(vdcm='1') then dcm<='1';

else dcm<='0';

end if;

end process;

end Behavioral;

2 (b). VHDL Code for controlling the operation of a Stepper Motor :

library IEEE;






--library UNISIM;


entity stepnew is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

dir : in STD_LOGIC;

row : in STD_LOGIC_VECTOR (1 downto 0);

dout : out STD_LOGIC_VECTOR (3 downto 0));

end stepnew;

architecture Behavioral of stepnew is

------------signal declarartion statements-------

signal clk_div: std_logic_vector(25 downto 0);

signal clk_int:std_logic;

signal shift_reg:std_logic_vector(3 downto 0);

begin



process(clk)

begin

if rising_edge(clk)then

clk_div<=clk_div+'1';

end if;

end process;

clk_int<=clk_div(25) when row="00" else

clk_div(15) when row="01" else

clk_div(10) when row="10" else

clk_div(10) ;

process(reset,clk_int,dir)

begin

if reset='0'then

shift_reg<="1001";

elsif rising_edge(clk_int) then

if dir='0' then

shift_reg<=shift_reg (0) & shift_reg (3 downto 1);

else

shift_reg<=shift_reg (2 downto 0) & shift_reg (3);

end if;

end if;

end process;

dout<=shift_reg;

end Behavioral;

User constraints file:-

#pin2ucf –

NET "clk" LOC = P77;

NET "dir" LOC = P3;

NET "dout<0>" LOC = P4;




NET "reset" LOC = P9;

NET "row<0>" LOC = P14;

NET "row<1>" LOC = P15;

Results:-

Written, Implemented the HDL Design on FPGA and Interfaced with DC motor and

Stepper motor through Demo boards. Found the hard ware working and compared

the output.



Experiment No 3

Write, Implement and Interface the HDL Design to Generate different wave forms

(sine, square, triangle, ramp etc.,) using DAC change frequency and amplitude.

Objective: - To Write, Implement and Interface the HDL Design to generate different wave

forms (sine, square, triangle, ramp etc.,) using DAC change frequency and

amplitude.

3(a). VHDL Code to generate Sine Wave :

library IEEE;






--library UNISIM;


entity ssine1 is

Port ( clk : in std_logic;

rst : in std_logic;

dac_out : out std_logic_vector(0 to 7));

end ssine1;

architecture Behavioral of ssine1 is

signal c1:std_logic_vector(7 downto 0);

signal I : integer range 0 to 179;

type sine is array(0 to 179)of integer range 0 to 255;

constant value: sine

:=(128,132,136,141,154,150,154,158,163,167,171,175,180,184,188,192,195,199,203,206,2

10,213,216,220,223,226,228,231,234,236,238,241,243,244,246,247,248,249,250,251,252,2

53,254,255,255,255,255,255,254,254,253,252,251,249,246,244,243,241,238,236,234,231,2

28,226,223,220,216,213,210,206,203,199,195,192,188,184,180,175,171,167,163,158,154,1

50,145,141,136,132,128,123,119,114,110,105,101,97,92,88,84,80,75,71,67,64,60,56,52,49,

45,42,39,35,32,29,27,24,21,19,17,14,12,11,09,07,06,04,03,02,01,01,0,0,0,0,0,0,0,0,1,1,2,3,

4,6,7,9,11,12,14,17,19,21,24,27,29,32,35,39,42,45,49,52,56,60,64,67,71,75,80,84,88,92,97,

101,105,110,114,119,123,128);

begin

process(clk,rst)

begin

if(rst='1') then



c1<=(others =>'0');

elsif (clk'event and clk ='1')then

c1<=c1+1;

end if;

end process;

process(c1(3))

begin

if(c1(3)'event and c1(3)='1')then

dac_out<= conv_std_logic_vector(value(I),8);

I<=I+1;

if(I=179) then

I<=0;

end if;

end if;

end process;

end behavioral;

user cionstraints file:-

pin2ucf –


NET "rst" LOC = P15;

NET "dac_out<0>" LOC = P3;








3(b). VHDL Code to generate Square Wave :

entity ssq1 is



Port ( clk : in std_logic;

rst : in std_logic;

dac_out : out std_logic_vector(0 to 7));

end ssq1;

architecture Behavioral of ssq1 is

signal temp:std_logic_vector(3 downto 0);

signal counter:std_logic_vector(0 to 7);

signal en:std_logic;

begin

process (clk)

begin


temp <= temp +'1';

end if;

end process;

process(temp(3),rst)

begin

if rst='1' then

counter<="00000000";

elsif rising_edge(temp(3)) then

if counter<255 and en='0' then

counter<=counter+1;

en<='0';

dac_out<="00000000";

elsif counter=0 then

en<='0';

else

en<='1';

counter<=counter-1;

dac_out<="11111111";

end if;

end if;

end process;

end Behavioral;




#pin2ucf











3(c). VHDL Code to generate Triangular Wave :

library IEEE;






--library UNISIM;


entity stria is


rst : in STD_LOGIC;

dac : out STD_LOGIC_VECTOR (0 to 7));

end stria;

architecture Behavioral of stria is

signal temp:std_logic_vector(3 downto 0):="0000";

signal counter:std_logic_vector(0 to 8):="000000000";

signal en:std_logic;

begin

process(clk)

begin


temp<=temp+'1';

end if;



end process;

process(temp(3))

begin

if rst='1' then counter<="000000000";


counter<=counter+1;

if counter(0)='1' then

dac<=counter( 1 to 8);

else

dac<=not(counter(1 to 8));

end if;

end if;

end process;

end Behavioral;


#pin2ucf



NET "dac<0>" LOC = P3;








3(d). VHDL Code to generate Ramp signal :

library IEEE;








--library UNISIM;


entity ramps1 is


rst : in STD_LOGIC;

dac : out STD_LOGIC_VECTOR (0 to 7));

end ramps1;

architecture Behavioral of ramps1 is

signal temp:std_logic_vector(3 downto 0):="0000";

signal cnt:std_logic_vector(0 to 7):="00000000";

begin

process(clk)

begin


temp<=temp+'1';

end if;

end process;

process(temp(3),cnt)

begin

if rst='1' then cnt<="00000000";


cnt<=cnt+15;

end if;

end process;

dac<=cnt;

end Behavioral;




#pin2ucf











Results :

Written, Implemented the HDL Design on FPGA and Interfaced with DAC to

display the Sine, Square, Triangular, ramp and displayed the output on the

oscilloscope. Found the hard ware working and compared the output.



Experiment No 4

Write, Implement and Interface the HDL Design to check the elevator operations.

Objective: - To Write, Implement and Interface the HDL Design to check the elevator

operations.

VHDL Code for Elevator Control Operations :

library IEEE;






--library UNISIM;


entity TKbele is

port( pkeyret : in std_logic_vector(3 downto 0);

pkeyscn : out std_logic_vector(3 downto 0);

pdspseg : out std_logic_vector(6 downto 0);

pdspmux : out std_logic_vector(3 downto 0);

pclk100k :in std_logic

);

end TKbele;

architecture Behavioral of TKbele is

signal scurflr,skeyflr: integer range 0 to 15;

signal skeyscn :std_logic_vector(3 downto 0);

signal lkeyscn :std_logic_vector(3 downto 0);

signal lkeyret :std_logic_vector(3 downto 0);

signal sclkdiv :std_logic_vector(15 downto 0);

signal sflrclk,skeyclk,skeyhit:std_logic;

begin

--process keyprocess

process(pkeyret) --PRESS KEY RETURN

begin

case pkeyret is



when "1110"=>skeyhit <='1';




when others =>skeyhit <='0';

end case;

end process;

process(skeyhit)

begin

if(rising_edge(skeyhit))then

lkeyscn<=skeyscn;

lkeyret<=pkeyret;

end if;

end process;

process(skeyhit)

begin

if(rising_edge(skeyhit))then

if(lkeyscn="1110" and lkeyret ="1110" )then skeyflr <=0;

elsif(lkeyscn="1110" and lkeyret ="1101" )then skeyflr <=1;















end if;

end if;

end process;

--process clk driver

process(pclk100k)

begin

if(rising_edge(pclk100k))then

sclkdiv<=sclkdiv+1;



end if;

skeyclk<=sclkdiv(6);

sflrclk<=sclkdiv(15);

end process;

-- process for keyscan clkscan

process(skeyclk)

begin

if(rising_edge(skeyclk) )then

if(skeyscn)="1110"then skeyscn<="1101";

elsif(skeyscn)="1101"then skeyscn<="1011";



else skeyscn<="1110";

end if;

pkeyscn<=skeyscn;

end if;

end process;

-- process florr motion

process(sflrclk)

begin

if(rising_edge(sflrclk))then

if(not(skeyflr=scurflr))then

if(skeyflr > scurflr)then scurflr<=scurflr+1;

else scurflr <=scurflr-1;

end if;

end if;

end if;

end process;

--process display 7seg

process(scurflr)

type tseg7 is array(0 to 15)of std_logic_vector(6 downto 0);

constant segval

:tseg7:=("0111111","0000110","1011011","1001111",--seg display "0","1","2","3"

"1100110","1101101","1111101","0000111",--seg display "4","5","6","7"

"1111111","1101111","1110111","1111100",--seg display "8","9","10=A","11=b"

"1011000","1011110","1111001","1110001"--seg display "12=c","13=d","14=e","15=f"

);

begin

pdspseg <=segval(scurflr);

pdspmux <="1110";

end process;



end Behavioral;


pin configurations of elevator

NET "pclk100k” LOC = "P77”;

NET "pdspmux<0>“LOC = "P33”;




NET "pdspseg<0>“LOC = "P41”;







NET "pkeyret<0>“LOC = "P3”;




NET "pkeyscn<0>“LOC = "P9”;




Results:-

Written, Implemented the HDL Design on FPGA and Interfaced with Elevator

Demo board and checked the operations of elevator reflecting on the hard ware.

Found the hard ware working and compared the output.

How to check the output of elevator program

The input “clk100k” is fed from the clock generation circuitry on the board to Pin 77

The input” pkeyret” is the only input we need to configure while checking input.



According to logic we have four states (floors) defined in the program they are

1110, 1011, 1101, and 0111.

In order to execute the logic perfect we need to reset the logic by giving the

pkeyret value other than the value specified above (ex: 1111 or 0000) then the

valid values indicated above.

Then we can see the output “pkeyscn” indicating the present state of the elevator after

every execution

To select the seven segment display we use the pin “pdspmux” on the board

The other output” pdspseg” which is connected to the seven segment display will indicate

the movement of the elevator with the Hexadecimal numbers (0 to F).From the previous

state/floor to the new input/floor configured on the input “pkeyret”.



Viva Questions

1. What type of language is VHDL?

2. What do all VHDL designs begin with?

3. Which block describes a design's interface and behavior?

4. What is the difference between simulation and synthesis?

5. Which data type defines a single logic signal and bus?

6. What two ways can a vector's range be described?

7. What are the IEEE STD_LOGIC_1164 data types for single logic signals and buses?

8. What are the only two values for a Boolean type?

9. What are the numerical data types?

10. What is SUBTYPING used for?

11. What type is use to create a user data type?

12. Create the use data type DAYS and assign it the values: MON, TUE, WED, THU, FRI,

SAT and SUN.

13. Which data type is used for a string of ASCII characters?

14. Which data type includes time units as values?

15. Create the entity block for a three input XOR gate.

16. Which symbol is used to end all VHDL statements?

17. What part of a port declaration defines signals in or out direction?

18. Which VHDL construct is used to define a literal constant in an entity block?

19. Create the integer constant included in an entity block called BUS_SIZE and assign it a

value of 32.

20. Which symbols are used as an assignment operator to assign a literal to an identifier

name?

21. What are the two primary ways to describe a logic circuits function within an

architecture block?

22. Create the architecture block for the 3-input XOR gate of question 21.

23. Which symbols are used to assign an expression's result to an output Interface signal?

24. What are the rules used to define an identifier name?

25. Write the statements that will allow a design to access all the contents of the IEEE

ARITH.

26. How does a transport delay differ from an inertial delay?

27. What is the purpose of a SIGNAL declaration?

28. Where are SIGNAL declarations placed in the design?

29. Write an assignment statement that assigns the contents of s(5) to t(2).

30. What is the purpose of a process' sensitivity list?

31 Under what conditions is a process run?

32 What is an EVENT? What is the difference between event and non-event driven process

execution?

33. Which symbols are used to differentiate between logic 1 & an integer1?

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M S Engineering College · 2019. 7. 18. · M S Engineering College Navarathna Agrahara, Sadahalli...

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