Autumn 1999 Yield Management Solutions20

InspectionF E A T U R E S

New CMP Challenges for Unpatterned Wa f e rInspection at 130 nm

by Hubert Altendorfer, Senior Product Marketing Manager; Lionel Kuhlmann, Senior Research Scientist; Henrik Nielsen, Senior Staff Electrical Engineer; and Mark Nokes, Principal System Design Engineer

Chemical Mechanical Polishing (CMP) has quickly become the standard planarization method in IC manufacturing.H o w e v e r, for CMP to continue to mature and become a viable process for the 0.13 µm generation, it is important to look atsome factors that may affect the CMP process such as variations in wafer surface topography. Currently, traditional waferflatness criteria are used to manage the depth of focus budget in the lithography process. Additional flatness requirements areemerging, demanded by the use of CMP in the early stages of device manufacturing. Topography variations on unpatternedwafers in the nanometer range have shown to adversely affect post CMP uniformity of dielectrics. An automated, high-speedinspection solution is needed to control the wafer quality used for these devices. This paper will discuss how surface topologycould affect IC devices and introduce a solution for such a future inspection step.

range detected by scattered light depends on the opticalc o n figuration and usually collects the signal of surfacefeatures with very high spatial frequency. Darkfie l doptics can collect high spatial frequencies but are insuffi-cient for features that exhibit lower spatial frequency.On the other hand, brightfield optics can detect thelower spatial frequencies required to characterize surfacet o p o l o g y.

A viable solutionThe KLA-Tencor Surfscan SP1 platform, with its second-generation brightfield capability (SNT™ –Surface NanoTopography), can provide quantified results

CMP and surface topographyDepositing a thin dielectric layer onto awafer that exhibits surface topology varia-tions results in a non-uniform film thicknessafter the CMP processing (figure 1). Thisnon-uniformity leads to resistivity variationsresulting in lower performance devices andeventually to a complete device failure.

Therefore, stringent control of startingmaterial for these small topology variationshas to be established. Traditional fla t n e s stools neither have the spatial resolution orthe vertical sensitivity to measure these fea-tures. A fairly sensitive piece of equipmentthat has been used thus far is known as the“Magic Mirror” revealing very small slopevariations on the surface. While the MagicMirror instantaneously produces an image ofthe full surface of the wafer, the results areseldom quantitative for magnitude andextent of a feature, which are critical para-meters to assure that the wafers are withinthe specification limits.

The surface topology contains all the infor-mation of the deviations of a real surfacefrom an ideal reference. The spatial frequency

F i g u re 1. Dielec tric film thickness variations a fter CMP due to sur f a c e

t o p o l o g y.

P r e -C M P

P o s t -C M P

Dielectric layer

S i S i

P a n e l D i s c u s s i o n

“Semiconductor Technology Challenges for CMP”(in conjunction with the 196th Meeting of

The Electrochemical Society)Thursday, October 21, 1999

5:00 PMThe objective of the panel discussion is to evaluate c u rrent state-of-the-art and predict the future re q u i re m e n t sand the review the readiness of the industry at larg e .Panelists re p resenting lithography, capital equipment s e c t o r, technology integration, CMP and process consumable segments of the industry will be present tolead the discussion. Companies re p resented include K L A - Te n c o r, Intel, Motorola, and other leading semiconductor manufacture r s .

196th Meeting of The Electrochemical Society, Inc.Honolulu, Hawaii

October 17-22, 1999Hilton Hawaiian Vi l l a g e

For more details, visit www.electrochem.org/meetings.html

F E A T U R E S

of the wafer surface topography with nanometer heightresolution at exceptionally high throughput. A criticalitem for success is to provide distortion free wafer han-dling during the measurement. Small forces at any partof the wafer will introduce artifacts to the measurement.The SP1 incorporates a proprietary edge handling designthat enables distortion-free wafer handling at all times.

The SP1 Surface NanoTopography design allows orien-tation-independent capture of large features. These fea-tures can be up to several millimeters with only a fewnanometer height. Figures 2, 3 and 4 compare surfacetopography maps produced by the Surfscan SP1’s SNTfeature to those from the HRP-200 profiler and a MagicM i r r o r, respectively. The results clearly show very goodcorrelation with equivalent sensitivity for these longspatial wavelength defects on the Surfscan SP1.Compared to the Magic Mirror, the Surfscan SP1 withSNT has the added benefit of quantifying the surfacet o p o l o g y.

The quantifiable result from the Surfscan SP1 allowsgrading of the wafers based on user definable criteria.The final result presents the number of defects above as p e c i fied height and total surface area covered by thesed e f e c t s .

C o n c l u s i o nIt is essential that variations in wafer surface topologybe detected as design rules move towards 130 nm. This will require a broad range of spatial wavelengthsextending from particles to surface site flatness. As mentioned earlier, detecting the different defect typesrequires the use of several methodologies. These havebeen combined in a single instrument, the Surfscan SP1.The SP1 can rapidly and non-destructively inspectwafers up to 300 mm. It meets the challenge of reliably

detecting particles in the 60 nm range, can separatecrystal originated pits (COPs) from particles and mea-sure surface topology in the nanometer height range.The Surfscan SP1 offers a comprehensive inspectionstrategy for CMP challenges at 130 nm design rules. ❈

c i r cle RS#013

F i g u re 2. Surfscan SP1 SNT height map. F i g u re 3. HRP-200 pro f i l e r. F i g u re 4. Magic Mirror image.