Date post: | 14-May-2015 |
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MATLAB and Simulink for Communications System Design Reference Designs and System Applications
©2013 The Mathworks, Inc.
Today’s Agenda
Accelerating System Development with Model-Based Design
Model-Based Design for Communications
Automatic Code Generation for System Deployment
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©2013 The Mathworks, Inc.
The System Design Challenge
How Can We: Verify our hardware implementation
matches system specification? Iterate our designs faster?
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Algorithm and System Design
FPGA FPGA / MCU
HDL / C / C++
©2013 The Mathworks, Inc.
Solution: Model-Based Design
Design, simulate, and validate algorithms and system models in MATLAB® and Simulink ®
Automatically generate HDL and C code
Verify the hardware implementation against the system model
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MATLAB and Simulink
Algorithm Design and System Design
FPGA
Automatic Code Generation
FPGA / MCU
HDL / C / C++
Verif
y
Generate
©2013 The Mathworks, Inc.
Model-Based Design Overview
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INTEGRATION
IMPLEMENTATION
DESIGN
TEST & VER
IFICATIO
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RESEARCH REQUIREMENTS
ARM FPGA
VHDL, Verilog C, C++
Environment Models
Physical Components
Algorithms
©2013 The Mathworks, Inc.
Model-Based Design Overview
Design and simulate application behavior using expansive library of existing IP for signal processing, communications, motor control, image and video processing, analog, and RF
The MATLAB language can be used for scripting, testing, debugging, and algorithm development
Incorporate Xilinx System Generator IP or custom IP in C/C++ or RTL
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INTEGRATION
RESEARCH REQUIREMENTS
IMPLEMENTATION
ARM FPGA
VHDL, Verilog C, C++
DESIGN
Environment Models
Physical Components
Algorithms
TEST & VER
IFICATIO
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©2013 The Mathworks, Inc.
Model-Based Design Overview
Explore design partitions between hardware and software components
AXI P-core generation for FPGA
ARM-9 Neon instruction replacements for software
Automation scripts for system assembly in Xilinx Platform Studio, Bitgen, and for device programming
Hardware-in-the-loop simulation as free-running or synchronized
Integration with Xilinx tools for design iteration
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INTEGRATION
RESEARCH REQUIREMENTS
IMPLEMENTATION
ARM FPGA
VHDL, Verilog C, C++
DESIGN
Environment Models
Physical Components
Algorithms
TEST & VER
IFICATIO
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©2013 The Mathworks, Inc.
Model-Based Design for Communications Targeting the Zynq SDR Platform
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©2013 The Mathworks, Inc.
Design Flow
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XPS MATLAB and Simulink
Top-Level Model
SDK
Create FSBL & BOOT.BIN
BIT ELF
SDR Reference Design
Subsystem A
Subsystem B
©2013 The Mathworks, Inc.
System Design Components
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Library of building blocks
Integration with RF
Incorporate MATLAB functions
Interactivity and visualization
©2013 The Mathworks, Inc.
Digital Up/Down Converter
Baseband simulation model, no carrier modulation
Assume no channel effects except low-pass filter
Focus on practical FPGA implementation
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©2013 The Mathworks, Inc.
Top-Level Model
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©2013 The Mathworks, Inc.
Automatic Code Generation
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©2013 The Mathworks, Inc.
Why Use Automatic Code Generation?
Continuous tool flow from algorithm design to implementation
Eliminates hand-coding errors
Spec/model updates automatically accounted for
Enables fast deployment on hardware
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©2013 The Mathworks, Inc.
Xilinx System Generator Integration
In1 Out1
Xilinx System Generator Subsystem Simulink Subsystem
In1
Out1
Out2
Out3
Out4
Out5
In1
In2
In3
In4
In5
Out1 1 1
Out1 In1
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©2013 The Mathworks, Inc.
Xilinx System Generator Subsystem Example
Gateway In Block Gateway Out Blocks
Xilinx System Generator Subsystem
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©2013 The Mathworks, Inc.
Xilinx System Generator/MathWorks HDL Coder Interoperability High-level abstraction + device-optimized quality of results
Validate algorithms on hardware using real-world analog data
HDL Coder • Native Simulink blocks • Abstract data types • Floating-to-fixed conversion • Design exploration • HW/SW partitioning
System Generator for DSP • Xilinx DSP blockset • Analog data acquisition • Ethernet HW cosimulation
High-Level Design and Modeling
Optimized Design Using Xilinx DSP Blockset
Tool Interoperability
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©2013 The Mathworks, Inc.
What We Covered
System Development with Model-Based Design
Verification through Simulation
Automatic Code Generation for FPGA and SoC Implementation
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©2013 The Mathworks, Inc.
Topics for Further Study
Analog and RF device modeling and simulation to validate algorithm operation with specific device models Help to determine the right interface devices for your design
Hardware co-simulation to verify algorithm operation with real-world signals
HDL code verification and FPGA-in-the-loop test benches
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©2013 The Mathworks, Inc.
More Information on Model-Based Design for Communications Systems Development MATLAB Central: Communication Systems Reference Curves
by Idin Motedayen-Aval Pilot Directed Continuous Sync of OFDM
by Dick Benson
MathWorks Book Program Contemporary Communication Systems
Using MATLAB and Simulink, 2e , Proakis/Salehi/Bauch
Digital Communications: A Discrete-Time Approach, Rice
Multirate Signal Processing for Communication Systems , Harris
Communications System Toolbox Demos US MIL-STD-188-110B Baseband
End-to-End Link IEEE 802.16-2004 OFDM PHY Link IEEE 802.11a WLAN Physical Layer
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©2013 The Mathworks, Inc.
MathWorks DSP Package for the Zynq-7000 SoC/ Analog Devices Software-Defined Radio Kit Hardware Avnet ZedBoard 7020 Analog Devices AD-FMCOMMS1-EBZ FMC Module
Software MathWorks DSP Design Package MATLAB Simulink HDL Coder MATLAB Coder™ Fixed-Point Designer™ Signal Processing Toolbox™ DSP System Toolbox™
Xilinx ISE® WebPACK software Linux drivers and applications
software HDL source Reference designs
Ordering Information (North America) Part Number: AES-ZSDR-ADI-G-MATW-ANUL (Annual Term License) Part Number: AES-ZSDR-ADI-G-MATW-PERP (Perpetual License)
www.em.avnet.com/adizynqsdr Outside North America: Contact [email protected]
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©2013 The Mathworks, Inc.
Visit the MathWorks Table in the Exhibition Room
Model-based design workflow for communications system design
MATLAB and Simulink
SimRF and other physical modeling tools
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This demo board is available for purchase: www.analog.com/DC13-hardware