May 9, 2001 2

Platform Design ConsiderationsPlatform Design Considerations

Eric RosarioEric Rosario

Intel CorporationIntel Corporation

May 9, 2001 3

AgendaAgenda

GuidelinesGuidelines Measurement TechniquesMeasurement Techniques Testing ResultsTesting Results SummarySummary

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GuidelinesGuidelines

USB 2.0 guidelines are more systematic, detailed USB 2.0 guidelines are more systematic, detailed than 1.x whitepapersthan 1.x whitepapers

The USB 2.0 Platform Design Guideline, Revision The USB 2.0 Platform Design Guideline, Revision 1.0 is available now1.0 is available now– http://developer.intel.com/technology/usb/techlit.htmhttp://developer.intel.com/technology/usb/techlit.htm

Design Guideline areas:Design Guideline areas:– Board routing, placement and layout guidelinesBoard routing, placement and layout guidelines– EMI/EMC solutions EMI/EMC solutions – Front panel USB design guidelinesFront panel USB design guidelines

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Board DesignBoard Design

4 layer sufficient; trace impedance matching is key4 layer sufficient; trace impedance matching is key Propagation Delay Propagation Delay

Maximum Motherboard Trace Length Of 18 InchesMaximum Motherboard Trace Length Of 18 Inches– Cable + Traces Cable + Traces 18 Inches For Front Panel Solutions 18 Inches For Front Panel Solutions

Motherboard Is theToughest Environment

Motherboard Is theToughest Environment

Host Controller Delay (3ns)

Host Controller Delay (3ns)

Cable (26ns) Cable (26ns) Device (1ns)Device (1ns)++ ++

May 9, 2001 6

Board Design GuidelinesBoard Design Guidelines

Board Stack-up:Board Stack-up:– 4 layer, impedance controlled boards required4 layer, impedance controlled boards required– Impedance targets must be specifiedImpedance targets must be specified– Ask your board vendor what they can achieveAsk your board vendor what they can achieve

Classic four-layer stackClassic four-layer stackSignal 1Signal 1

PrepregPrepreg

VCCVCCCoreCoreGroundGround

PrepregPrepreg

Signal 2Signal 2

Example target impedance:Example target impedance:0.005 in trace at 60+/-15%0.005 in trace at 60+/-15%7.5mil traces with 7.5mil7.5mil traces with 7.5milspacing Zdiffspacing Zdiff 90 90

May 9, 2001 7May 17, 2000 7

Routing GuidelinesRouting Guidelines

Control trace widths to obtain target impedanceControl trace widths to obtain target impedance– Ask your board vendor what they can achieveAsk your board vendor what they can achieve– As always, cost is a considerationAs always, cost is a consideration

Maintain strict trace spacing controlMaintain strict trace spacing control Minimize stubsMinimize stubs

D-D-D-D-

D+D+D+D+

15k15k

15k15kCorrect way to connect to resistorsCorrect way to connect to resistors

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MotherboardMotherboard Front PanelDaughter Card

Front PanelDaughter Card

Board DesignBoard Design

Daughtercard at front/side panelDaughtercard at front/side panel– Bypass caps, EMI control components, strain reliefBypass caps, EMI control components, strain relief

Header and cableHeader and cable– Keyed header, cable of limited length andKeyed header, cable of limited length and

matched impedance matched impedance

Front/Side Panel ConnectorsFront/Side Panel Connectors

May 9, 2001 9May 17, 2000 8

Routing GuidelinesRouting Guidelines

Routing over plane splitsRouting over plane splits Creating stubs with test pointsCreating stubs with test points Violating trace spacing guidelinesViolating trace spacing guidelines

Common Routing MistakesCommon Routing Mistakes

Ground or power planeGround or power plane

tptpDon’t cross plane splitsDon’t cross plane splits

Proper routing technique Proper routing technique maintains spacing guidelinesmaintains spacing guidelines

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Measurement TechniquesMeasurement Techniques

Selecting Appropriate Test EquipmentSelecting Appropriate Test Equipment– Accurate measurement of signal quality requires anAccurate measurement of signal quality requires an

o-scope and probes with adequate BW and sample rateo-scope and probes with adequate BW and sample rate

– Proper test fixtures are also importantProper test fixtures are also important

Equipment that will workEquipment that will workScope: TDS 694C - 10GS/s, 3GhzScope: TDS 694C - 10GS/s, 3GhzProbe: P6247 Fet Probe - 4Ghz, .4pF typProbe: P6247 Fet Probe - 4Ghz, .4pF typ

9090

Differential ProbeDifferential Probe

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USB 2.0 test mode software will be used to USB 2.0 test mode software will be used to enable device and host controller testsenable device and host controller tests

USB 2.0 test fixture will be used to provide USB 2.0 test fixture will be used to provide ideal termination for signal quality ideal termination for signal quality measurementmeasurement

Differential signaling requires the use of a Differential signaling requires the use of a differential probedifferential probe

HS RelayHS Relay

Differential ProbeDifferential Probe

Test Mode SW

USB 2.0 test fixtureUSB 2.0 test fixture HS DeviceHS Device

OscilloscopeOscilloscope

Board TestingBoard Testing

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EMIEMI

USB1.X EMI solutions don’t work for USB2USB1.X EMI solutions don’t work for USB2– Low pass filters damage USB 2.0 HS signal qualityLow pass filters damage USB 2.0 HS signal quality

D+

D -

Vcc

USB AConnector

Typical USB 1.1 Termination SchemeTypical USB 1.1 Termination Scheme

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VCC

USB 'A' Connector

D-

D+

Common ModeChoke

EMIEMI

Common mode chokes are a proven USB 2.0Common mode chokes are a proven USB 2.0EMI solutionEMI solution– Refer to the USB 2.0 Design Guideline for solutions Refer to the USB 2.0 Design Guideline for solutions

that work for USB 2.0 FS & HS signal quality that work for USB 2.0 FS & HS signal quality requirementsrequirements

Common ModeCommon ModeChokes are aChokes are a

Defensive Design!!!Defensive Design!!!

Common ModeCommon ModeChokes are aChokes are a

Defensive Design!!!Defensive Design!!!

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EMIEMI

Proper grounding of chassis is crucialProper grounding of chassis is crucial– Connector shell must connect to green wireConnector shell must connect to green wire

ground early and wellground early and well– IO shield must connect securely to chassisIO shield must connect securely to chassis

and receptacleand receptacle 2 wire common mode choke is preferred2 wire common mode choke is preferred

– Blocks common mode EMI from leaving chassisBlocks common mode EMI from leaving chassis– Common mode impedance @ 100 Mhz should beCommon mode impedance @ 100 Mhz should be

< 300 Ohms< 300 Ohms– Differential Impedance @ 100 Mhz should be < 8 OhmsDifferential Impedance @ 100 Mhz should be < 8 Ohms

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ESD, EMCESD, EMC

ESD strikes spread out in time by inductanceESD strikes spread out in time by inductanceof cables and hubs in seriesof cables and hubs in series– Bypass/flyback caps on Vbus near connector helpBypass/flyback caps on Vbus near connector help

Hardware ProtectionHardware Protection– Well-grounded shield Well-grounded shield – Common mode chokeCommon mode choke– Spark gap arrestorsSpark gap arrestors– Shielded cablesShielded cables

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DP1DP1

DM1DM1

1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9

x 10-5

0

0.5

1

1.5

2

2.5

3

3.5

s

V

keyboard glitchkeyboard glitchkeyboard glitchkeyboard glitch

ESD, EMCESD, EMC

Differential squelch/disconnectDifferential squelch/disconnect Pattern matching before connectivityPattern matching before connectivity Sampling over extended times e.g. ChirpSampling over extended times e.g. Chirp Low speed requires cables with at least a foil shieldLow speed requires cables with at least a foil shield

Noise Immunity Built IntoLow-Level Protocol

Noise Immunity Built IntoLow-Level Protocol

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USB2 Validation Motherboard USB2 Validation Motherboard

FrontFrontPanelPanel

Test ChipBack PanelBack Panel

Test ChipTest Chip

Test ResultsTest Results

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Routing Paths Tested Routing Paths Tested

USB ConnectorUSB Connector

MotherboardMotherboard

PCI SLOTPCI SLOT

LANLAN

PCI SLOTPCI SLOT PCI SLOTPCI SLOTPCI SLOTPCI SLOT

South BridgeSouth Bridge

NEC NEC testtest chipchip

Long RouteLong Route

Front Panel HeaderFront Panel Header

Test ResultsTest Results

MotherboardMotherboard

PCI SLOTPCI SLOT

LANLAN

PCI SLOTPCI SLOT PCI SLOTPCI SLOTPCI SLOTPCI SLOT

South BridgeSouth Bridge

USB ConnectorUSB Connector

Short RouteShort Route

NEC test chipNEC test chip

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TP2 TP3

Validation board ResultsValidation board Results

Back Panel Eye Pattern ResultsBack Panel Eye Pattern Results– EMI/ESD componentsEMI/ESD components– Both at A-connector (TP2) and at end of USB cable (TP3)Both at A-connector (TP2) and at end of USB cable (TP3)

(with ideal termination)(with ideal termination)– Three-stack connector on MBThree-stack connector on MB

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18” Shielded, twisted pair

18” ribbon cable

Early Testing ResultsEarly Testing Results

Front Panel Header Cable Options TestedFront Panel Header Cable Options Tested

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Shielded Front Panel CableShielded Front Panel Cable Ribbon Front Panel CableRibbon Front Panel Cable

Validation board ResultsValidation board Results

Front-panel Cable Implementation Eye Pattern ResultsFront-panel Cable Implementation Eye Pattern Results– 18 inch, twisted pair, shielded front panel cable18 inch, twisted pair, shielded front panel cable– 18 inch unshielded front panel “ribbon” cable18 inch unshielded front panel “ribbon” cable

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Validation board ResultsValidation board Results

Front-panel Cable Implementation Eye Pattern ResultsFront-panel Cable Implementation Eye Pattern Results– 18 inch, twisted pair, shielded front panel cable18 inch, twisted pair, shielded front panel cable– 18 inch unshielded front panel “ribbon” cable18 inch unshielded front panel “ribbon” cable

Connector referenceConnector reference

80

72

110

1.4 nsexception window

Shielded, Twisted PairShielded, Twisted PairFront Panel CableFront Panel Cable

114

145

114

RibbonRibbonFront Panel CableFront Panel Cable

Connector referenceConnector reference

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Test ResultsTest Results

USB 2.0 host controller

Back PanelBack Panel

FrontFrontPanelPanel

USB 2.0 Motherboard USB 2.0 Motherboard

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USB 2.0 Board Test Results USB 2.0 Board Test Results

High Speed Back Panel Eye Pattern Results (Figure 1)High Speed Back Panel Eye Pattern Results (Figure 1) High Speed Front Panel Eye Pattern Results with shielded cable (Figure 2)High Speed Front Panel Eye Pattern Results with shielded cable (Figure 2)

Figure 1Figure 1Figure 1Figure 1 Figure 2Figure 2Figure 2Figure 2

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Device turns onHS termination

Reset

USB 2.0 Board Test ResultsUSB 2.0 Board Test Results

CHIRP TestingCHIRP Testing– Measured with single ended probesMeasured with single ended probes– At the A-connector (TP2)At the A-connector (TP2)

Important ParametersImportant Parameters– Reset durationReset duration– CHIRP K amplitudeCHIRP K amplitude– CHIRP K durationCHIRP K duration– HS termination timingHS termination timing– Host CHIRP amplitudeHost CHIRP amplitude

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SummarySummary

USB 2.0 Design Presents New ChallengesUSB 2.0 Design Presents New Challenges– Board layoutBoard layout– Common mode chokesCommon mode chokes– Front Panel SolutionsFront Panel Solutions– Signal Quality MeasurementSignal Quality Measurement– Compliance TestingCompliance Testing

USBIF Is Providing Design Guides In Such AreasUSBIF Is Providing Design Guides In Such Areas

May 9, 2001 27

ReferencesReferences

USB-IF USB-IF – http://www.usb.orghttp://www.usb.org

Platform Design guidePlatform Design guide– http://developer.intel.com/technology/usb/techlit.htmhttp://developer.intel.com/technology/usb/techlit.htm

ContactContact– eric.rosario@intel.comeric.rosario@intel.com– www.tektronics .comwww.tektronics .com– www.agilent.comwww.agilent.com

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Questions?Questions?