MCP621/1S/2/3/4/5/9 Data Sheetww1.microchip.com/downloads/en/DeviceDoc/20002188D.pdf30 pF 100 k 3pF...

MCP621/1S/2/3/4/5/920 MHz, 200 µV Op Amps with mCal

Features:

• Gain-Bandwidth Product: 20 MHz (typical)

• Slew Rate: 30 V/µs

• Low Input Offset: ±200 µV (maximum)

• Low Input Bias Current: 5 pA (typical)

• Noise: 13 nV/Hz, at 1 MHz

• Ease-of-Use:

- Unity-Gain Stable

- Rail-to-Rail Output

- Input Range incl. Negative Rail

- No Phase Reversal

• Supply Voltage Range: +2.5V to +5.5V

• High Output Current: ±70 mA

• Supply Current: 2.5 mA/Ch (typical)

• Low-Power Mode: 5 µA/Ch

• Small Packages: SOT23-5, DFN

• Extended Temperature Range: -40°C to +125°C

Typical Applications:

• Optical Detector Amplifier

• Barcode Scanners

• Multi-Pole Active Filter

• Driving A/D Converters

• Fast Low-Side Current Sensing

• Power Amplifier Control Loops

• Consumer Audio

Design Aids:

• SPICE Macro Models

• FilterLab® Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Description:

The Microchip Technology Inc. MCP621/1S/2/3/4/5/9family of high bandwidth and high slew rate operationalamplifiers features low offset. At power-up, these opamps are self-calibrated using mCal. Some packageoptions also provide a Calibration/Chip Select pin(CAL/CS) that supports a Low-Power mode ofoperation, with offset calibration at the time normaloperation is re-started. These amplifiers are optimizedfor high speed, low noise and distortion, single-supplyoperation with rail-to-rail output and an input thatincludes the negative rail.

This family is offered in single (MCP621 andMCP621S), single with CAL/CS pin (MCP623), dual(MCP622), dual with CAL/CS pins (MCP625), quad(MCP624) and quad with CAL/CS pins (MCP629). Alldevices are fully specified from -40°C to +125°C.

Typical Application Circuit

Photo Detector

CD

CF

RF

VREF

30 pF

100 k

3 pF

ID100 nA

VOUT

MCP622 VREF

26.1 k2.61 k

294270 pF

100 pF

A

B

Detector Amplifier with 350kHz 2nd-order MFB Low pass Filter

High Gain-Bandwidth Op Amp Portfolio

Model Family Channels/Package Gain Bandwidth VOS (max.) IQ/Ch (typ.)

MCP621/1S/2/3/4/5/9 1, 2, 4 20 MHz 0.2 mV 2.5 mA

MCP631/2/3/4/5/9 1, 2, 4 24 MHz 8.0 mV 2.5 mA

MCP651/1S/2/3/4/5/9 1, 2, 4 50 MHz 0.2 mV 6.0 mA

MCP660/1/2/3/4/5/9 1, 2, 3, 4 60 MHz 8.0 mV 6.0 mA

2009-2014 Microchip Technology Inc. DS20002188D-page 1

http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en542042


http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP660


MCP621/1S/2/3/4/5/9

Package Types

MCP621SOIC

MCP622SOIC

VIN+

VIN–

VSS

VDD

VOUT

1

2

3

4

8

7

6

5 VCAL

CAL/CSNC

VINA+

VINA–

VSS

1

2

3

4

8

7

6

5

VOUTAVDD

VOUTB

VINB–

VINB+

MCP625MSOP

VINA+

VINA–

VSS

1

2

3

4

10

9

8

7

VOUTA VDD

VOUTB

VINB–

VINB+

CALA/CSA 5 6 CALB/CSB

MCP6223x3 DFN *

MCP6253x3 DFN *

* Includes Exposed Thermal Pad (EP); see Table 3-1.

VINA+

VINA–

VSS

VOUTB

VINB–

1

2

3

4

8

7

6

5 VINB+

VDDVOUTA

EP9

VSS

VINA+

CALA/CSA

VINB–

VINB+

2

3

4

5

9

8

7

6 CALB/CSB

VOUTBVINA–EP11

1 10 VDDVOUTA

2

MCP6294x4 QFN*

VDD

VINB+

VINA- VIND+

VSS

VIN

B-

VINC+

VO

UT

B

CA

LB

C/C

SB

C

VO

UT

C

VINC-

VO

UTA

CA

LA

D/C

SA

D

VO

UT

D

VIN

D-

VINA+ EP

16

1

15 14 13

3

4

12

11

10

9

5 6 7 8

17

MCP624SOIC, TSSOP

VINA+

VINA-

VDD

1

2

3

4

14

13

12

11

VOUTA VOUTD

VIND-

VIND+

VSS

VINB+ 5 10 VINC+

VINB- 6 9

VOUTB 7 8 VOUTC

VINC-

MCP6212x3 TDFN *

VIN+

VIN–

VSS

VDD

VOUT

1

2

3

4

8

7

6

5 VCAL

CAL/CSNC

EP9

CAL/CS

VIN+

VOUT

VSS

VIN-

MCP623SOT-23-6

VDD1

2

3 4

5

6

VIN+

VOUT

VSS

VIN-

MCP621SSOT-23-5

VDD1

2

3 4

5

DS20002188D-page 2 2009-2014 Microchip Technology Inc.

MCP621/1S/2/3/4/5/9

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD – VSS .......................................................................6.5V

Current at Input Pins ....................................................±2 mAAnalog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0VAll Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3VOutput Short Circuit Current ................................ContinuousCurrent at Output and Supply Pins ..........................±150 mAStorage Temperature ...................................-65°C to +150°CMax. Junction Temperature ........................................ +150°CESD protection on all pins (HBM, MM) 1 kV, 200V

† Notice: Stresses above those listed under “AbsoluteMaximum Ratings” may cause permanent damage tothe device. This is a stress rating only and functionaloperation of the device at those or any otherconditions above those indicated in the operationallistings of this specification is not implied. Exposure tomaximum rating conditions for extended periods mayaffect device reliability.

†† See Section 4.2.2, Input Voltage and CurrentLimits.

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS = VSS (refer to Figure 1-2).

Parameters Sym. Min. Typ. Max. Units Conditions

Input Offset

Input Offset Voltage VOS -200 — +200 µV After calibration (Note 1)

Input Offset Voltage Trim Step Size

VOSTRM — 37 200 µV (Note 2)

Input Offset Voltage Drift VOS/TA — ±2.0 — µV/°C TA = -40°C to +125°C

Power Supply Rejection Ratio PSRR 61 76 — dB

Input Current and Impedance

Input Bias Current IB — 5 — pA

Across Temperature IB — 100 — pA TA = +85°C

Across Temperature IB — 1700 5,000 pA TA = +125°C

Input Offset Current IOS — ±10 — pA

Common Mode Input Impedance

ZCM — 1013||9 — ||pF

Differential Input Impedance ZDIFF — 1013||2 — ||pF

Common Mode

Common Mode Input Voltage Range

VCMR VSS 0.3 — VDD 1.3 V (Note 3)

Common Mode Rejection Ratio CMRR 65 81 — dB VDD = 2.5V, VCM = -0.3 to 1.2V

CMRR 68 84 — dB VDD = 5.5V, VCM = -0.3 to 4.2V

Open-Loop Gain

DC Open-Loop Gain (large signal)

AOL 88 117 — dB VDD = 2.5V, VOUT = 0.3V to 2.2V

AOL 94 126 — dB VDD = 5.5V, VOUT = 0.3V to 5.2V

Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.

2: Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.3: See Figure 2-6 and Figure 2-7 for temperature effects.4: The ISC specifications are for design guidance only; they are not tested.


MCP621/1S/2/3/4/5/9

Output

Maximum Output Voltage Swing VOL, VOH VSS + 20 — VDD 20 mV VDD = 2.5V, G = +2,0.5V Input Overdrive

VOL, VOH VSS + 40 — VDD 40 mV VDD = 5.5V, G = +2,0.5V Input Overdrive

Output Short Circuit Current ISC ±40 ±85 ±130 mA VDD = 2.5V (Note 4)

ISC ±35 ±70 ±110 mA VDD = 5.5V (Note 4)

Calibration Input

Calibration Input Voltage Range VCALRNG VSS + 0.1 — VDD – 1.4 mV VCAL pin externally driven

Internal Calibration Voltage VCAL 0.323VDD 0.333VDD 0.343VDD VCAL pin open

Input Impedance ZCAL — 100 || 5 — k||pF

Power Supply

Supply Voltage VDD 2.5 — 5.5 V

Quiescent Current per Amplifier IQ 1.2 2.5 3.6 mA IO = 0

POR Input Threshold, Low VPRL 1.15 1.40 — V

POR Input Threshold, High VPRH — 1.40 1.65 V

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-2).


AC Response

Gain Bandwidth Product GBWP — 20 — MHz

Phase Margin PM — 60 — ° G = +1

Open-Loop Output Impedance ROUT — 15 —

AC Distortion

Total Harmonic Distortion plus Noise

THD+N — 0.0018 — % G = +1, VOUT = 2VP-P, f = 1 kHz,VDD = 5.5V, BW = 80 kHz

Step Response

Rise Time, 10% to 90% tr — 13 — ns G = +1, VOUT = 100 mVP-P

Slew Rate SR — 10 — V/µs G = +1

Noise

Input Noise Voltage Eni — 20 — µVP-P f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni — 13 — nV/Hz f = 1 MHz

Input Noise Current Density ini 4 — fA/Hz f = 1 kHz

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS = VSS (refer to Figure 1-2).


Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.

2: Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.3: See Figure 2-6 and Figure 2-7 for temperature effects.4: The ISC specifications are for design guidance only; they are not tested.


MCP621/1S/2/3/4/5/9

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).


CAL/CS Low Specifications

CAL/CS Logic Threshold, Low VIL VSS — 0.2VDD V

CAL/CS Input Current, Low ICSL — 0 — nA CAL/CS = 0V

CAL/CS High Specifications

CAL/CS Logic Threshold, High VIH 0.8VDD VDD V

CAL/CS Input Current, High ICSH — 0.7 — µA CAL/CS = VDD

GND Current ISS -3.5 -1.8 — µA Single, CAL/CS = VDD = 2.5V

ISS -8 -4 — µA Single, CAL/CS = VDD = 5.5V

ISS -5 -2.5 — µA Dual, CAL/CS = VDD = 2.5V

ISS -10 -5 — µA Dual, CAL/CS = VDD = 5.5V

CAL/CS Internal Pull-Down Resistor

RPD — 5 — M

Amplifier Output Leakage IO(LEAK) — 50 — nA CAL/CS = VDD, TA = 125°C

POR Dynamic Specifications

VDD Low to Amplifier Off Time(output goes High Z)

tPOFF — 200 — ns G = +1 V/V, VL = VSS,VDD = 2.5V to 0V step to VOUT = 0.1 (2.5V)

VDD High to Amplifier On Time(including calibration)

tPON 100 200 300 ms G = +1 V/V, VL = VSS,VDD = 0V to 2.5V step to VOUT = 0.9 (2.5V)

CAL/CS Dynamic Specifications

CAL/CS Input Hysteresis VHYST— 0.25 — V

CAL/CS Setup Time(between CAL/CS edges)

tCSU 1 — — µs G = +1 V/V, VL = VSS (Notes 2, 3, 4)CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2)

CAL/CS High to Amplifier Off Time(output goes High Z)

tCOFF — 200 — ns G = +1 V/V, VL = VSS,CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2)

CAL/CS Low to Amplifier On Time(including calibration)

tCON — 3 4 ms G = +1 V/V, VL = VSS, MCP621 and MCP625, CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2)

tCON — 6 8 ms G = +1 V/V, VL = VSS, MCP629, CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2)

Note 1: The MCP622 single, MCP625 dual and MCP629 quad have their CAL/CS inputs internally pulled down to VSS (0V).2: This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised

before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode.3: For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously

(within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in Calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled.

4: For the MCP629 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultaneously (within a time much smaller than tCSU) to make all four op amps perform the same function simultaneously, and the maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD (CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow more than the maximum tCON time (8 ms) before the other side is toggled.


MCP621/1S/2/3/4/5/9

1.3 Timing Diagram

FIGURE 1-1: Timing Diagram.

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V,VSS = GND.


Temperature Ranges

Specified Temperature Range TA -40 — +125 °C

Operating Temperature Range TA -40 — +125 °C (Note 1)

Storage Temperature Range TA -65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W

Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W

Thermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/W

Thermal Resistance, 8L-3x3 DFN θJA — 56.7 — °C/W (Note 2)

Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W

Thermal Resistance, 10L-3x3 DFN θJA — 53.3 — °C/W (Note 2)

Thermal Resistance, 10L-MSOP θJA — 202 — °C/W

Thermal Resistance, 14L-SOIC θJA — 95.3 — °C/W

Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W

Thermal Resistance, 16L-4x4-QFN θJA — 45.7 — °C/W (Note 2)

Note 1: Operation must not cause TJ to exceed the Maximum Junction Temperature specification (150°C).2: Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.

High Z

VDD

VOUT

-3 µA (typical)

High Z

ISS

ICS

-3 µA (typical)-2.5 mA (typical)

VPRH VPRL

tPON tPOFF

On

0 nA (typical)

High Z

-3 µA (typical) -2.5 mA (typical)

tCOFF tCON

On

0.7 µA (typical) 0 nA (typical)

CAL/CS VIH VIL

tCSU

Note: For the MCP625 dual and the MCP629 quad, there is an additional constraint on toggling the twoCAL/CS pins close together; see the TCON specification in Table 1-3.


MCP621/1S/2/3/4/5/9

1.4 Test Circuits

The circuit used for most DC and AC tests is shown inFigure 1-2. This circuit can independently set VCM andVOUT; see Equation 1-1. Note that VCM is not thecircuit’s Common mode voltage ((VP + VM)/2), and thatVOST includes VOS plus the effects (on the input offseterror, VOST) of temperature, CMRR, PSRR and AOL.

EQUATION 1-1:

FIGURE 1-2: AC and DC Test Circuit for Most Specifications.

GDM RF RG=

VCM VP VDD 2+ 2=

VOUT VDD 2 VP VM– VOST 1 GDM+ + +=

Where:

GDM = Differential Mode Gain (V/V)

VCM = Op Amp’s Common ModeInput Voltage

(V)

VOST = Op Amp’s Total Input OffsetVoltage

(mV)

VOST VIN– VIN+–=

VDD

RG RF

VOUTVM

CB2

CLRL

VL

CB1

10 k10 k

RG RF

VDD/2VP

10 k10 k

50 pF2 k

2.2 µF100 nF

VIN–

VIN+

CF6.8 pF

CF6.8 pF

MCP62X


MCP621/1S/2/3/4/5/9

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,

VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.

2.1 DC Signal Inputs

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration).

FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage.

FIGURE 2-5: Input Offset Voltage vs. Output Voltage.

FIGURE 2-6: Low Input Common Mode Voltage Headroom vs. Ambient Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0%2%4%6%8%

10%12%14%16%18%20%22%

-80 -60 -40 -20 0 20 40 60 80Input Offset Voltage (µV)

Per

cen

tag

e o

f O

ccu

rre

nce

s 80 SamplesTA = +25°CVDD = 2.5V and 5.5VCalibrated at +25°C

0%2%4%6%8%

10%12%14%16%18%20%22%24%

-10 -8 -6 -4 -2 0 2 4 6 8 10

Input Offset Voltage Drift (µV/°C)

Pe

rcen

tag

e o

f O

ccu

rren

ces 80 Samples

VDD = 2.5V and 5.5VTA = -40°C to +125°CCalibrated at +25°C

0%5%

10%15%20%25%30%35%40%45%50%

-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60Input Offset Voltage Calibration Repeatability

(µV)

Per

cen

tag

e o

f O

ccu

rren

ces 200 Samples

TA = +25°CVDD = 2.5V and 5.5V

CalibrationChanged(-1 step)

No Change(includes noise)

CalibrationChanged(+1 step)

-700

-600

-500

-400

-300

-200

-100

0

100

200

300

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5Power Supply Voltage (V)

Inp

ut

Off

set

Vo

ltag

e (µ

V)

+125°C+85°C+25°C-40°C

Representative PartCalibrated at VDD = 6.5V

-50

-40

-30

-20

-10

0

10

20

30

40

50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Output Voltage (V)

Inp

ut

Off

set

Vo

ltag

e (µ

V)

VDD = 2.5V

VDD = 5.5V

Representative Part

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

-50 -25 0 25 50 75 100 125Ambient Temperature (°C)

Lo

w In

pu

t C

om

mo

nM

od

e H

ead

roo

m (

V)

VDD = 2.5V

1 LotLow (VCMR_L – VSS)

VDD = 5.5V


MCP621/1S/2/3/4/5/9



FIGURE 2-7: High Input Common Mode Voltage Headroom vs. Ambient Temperature.

FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V.

FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V.

FIGURE 2-10: CMRR and PSRR vs. Ambient Temperature.

FIGURE 2-11: DC Open-Loop Gain vs. Ambient Temperature.

FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V.

1.0

1.1

1.2

1.3

1.4


Hig

h In

pu

t C

om

mo

nM

od

e H

ead

roo

m (

V)

VDD = 2.5V

VDD = 5.5V

1 LotHigh (VDD – VCMR_H)

-1000-800-600-400-200

0200400600800

1000

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Input Common Mode Voltage (V)

Inp

ut

Off

se

t V

olt

ag

e (

µV

) VDD = 2.5VRepresentative Part

+125°C+85°C+25°C-40°C

-1000-800-600-400-200

0200400600800

1000

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Input Common Mode Voltage (V)

Inp

ut

Off

se

t V

olt

ag

e (

µV

) VDD = 5.5VRepresentative Part

+125°C+85°C+25°C-40°C

60

65

70

75

80

85

90

95

100

105

110


CM

RR

, PS

RR

(d

B)

PSRR

CMRR, VDD = 5.5V

CMRR, VDD = 2.5V

100

105

110

115

120

125

130


DC

Op

en-L

oo

p G

ain

(d

B)

VDD = 5.5V

VDD = 2.5V

1

10

100

1,000

10,000

25 45 65 85 105 125Ambient Temperature (°C)

Inp

ut

Bia

s, O

ffs

et C

urr

ents

(pA

)

VDD = 5.5VVCM = VCMR_H

| IOS |

IB


MCP621/1S/2/3/4/5/9



FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C.

FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C.

FIGURE 2-15: Input Bias Current vs. Input Voltage (below VSS).

-60

-40

-20

0

20

40

60

80

100

120

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Inp

ut

Bia

s, O

ffse

t C

urr

ents

(pA

)

IB

Representative PartTA = +85°CVDD = 5.5V

IOS

-1000

-500

0

500

1000

1500

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Common Mode Input Voltage (V)

Inp

ut

Bia

s,

Off

set

Cu

rren

ts(p

A)

IB

Representative PartTA = +125°CVDD = 5.5V

IOS

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0Input Voltage (V)

Inp

ut

Cu

rren

t M

agn

itu

de

(A)

+125°C+85°C+25°C-40°C

1m

100µ

10µ

1µ

100n

10n

1n

100p

10p

1p


MCP621/1S/2/3/4/5/9



2.2 Other DC Voltages and Currents

FIGURE 2-16: Ratio of Output Voltage Headroom to Output Current.

FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature.

FIGURE 2-18: Output Short-Circuit Current vs. Power Supply Voltage.

FIGURE 2-19: Supply Current vs. Power Supply Voltage.

FIGURE 2-20: Supply Current vs. Common Mode Input Voltage.

FIGURE 2-21: Power-On Reset Voltages vs. Ambient Temperature.

0

2

4

6

8

10

12

14

1 10 100Output Current Magnitude (mA)

Rat

io o

f O

utp

ut

Hea

dro

om

to

Ou

tpu

t C

urr

ent

(mV

/mA

)

VDD = 2.5V

VDD = 5.5V

VDD – VOH

IOUT

VOL – VSS

-IOUT

0

2

4

6

8

10

12

14

16

18

20


Ou

tpu

t H

ead

roo

m (

mV

)

VDD = 5.5V

VOL – VSS

VDD = 2.5V VDD – VOH

RL = 2 kΩ

-100

-80

-60

-40

-200

2040

6080

100

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Ou

tpu

t S

ho

rt C

ircu

it C

urr

ent

(mA

)

+125°C+85°C+25°C-40°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5


Su

pp

ly C

urr

ent

(mA

/am

pli

fie

r)

+125°C+85°C+25°C-40°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5


Su

pp

ly C

urr

ent

(mA

/am

pli

fie

r)

VDD = 2.5V

VDD = 5.5V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8


PO

R T

rip

Vo

ltag

es

(V

)

VPRL

VPRH


MCP621/1S/2/3/4/5/9



FIGURE 2-22: Normalized Internal Calibration Voltage.

FIGURE 2-23: VCAL Input Resistance vs. Temperature.

0%

5%

10%

15%

20%

25%

30%

33.2

0%

33.2

4%

33.2

8%

33.3

2%

33.3

6%

33.4

0%

33.4

4%

33.4

8%

33.5

2%

Normalized Internal Calibration Voltage;VCAL/VDD

Pe

rcen

tag

e o

f O

ccu

rren

ces

144 SamplesVDD = 2.5V and 5.5V

0

20

40

60

80

100

120

140


Inte

rna

l V

CA

L R

esi

sta

nc

e (

kΩ)


MCP621/1S/2/3/4/5/9



2.3 Frequency Response

FIGURE 2-24: CMRR and PSRR vs. Frequency.

FIGURE 2-25: Open-Loop Gain vs. Frequency.

FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.

FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.

FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Output Voltage.

FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency.

10

20

30

40

50

60

70

80

90

100

1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Frequency (Hz)

CM

RR

, P

SR

R (

dB

)

CMRR

100 1M10k 10M100k1k

PSRR+PSRR-

-20

0

20

40

60

80

100

120

140

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8

Frequency (Hz)

Op

en-L

oo

p G

ain

(d

B)

-240

-210

-180

-150

-120

-90

-60

-30

0

Op

en-L

oo

p P

has

e (°

)

| AOL |

AOL

10 1k 100k 10M1 100 10k 1M 100M

15

20

25

30

35

40

45


Gai

n B

an

dw

idth

Pro

du

ct

(MH

z)

40

45

50

55

60

65

70

Ph

ase

Ma

rgin

(°)PM

GBWP

VDD = 5.5VVDD = 2.5V

15

20

25

30

35

40

45

-0.5 0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


Gai

n B

and

wid

th P

rod

uct

(MH

z)

40

45

50

55

60

65

70

Ph

ase

Mar

gin

(°)

PM

GBWP


15

20

25

30

35

40

45

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Output Voltage (V)

Gai

n B

an

dw

idth

Pro

du

ct(M

Hz)

40

45

50

55

60

65

70

Ph

as

e M

arg

in (

°)

PM

GBWP


0.1

1

10

100

1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08Frequency (Hz)

1k 1M 10M 100M

Op

en-L

oo

p O

utp

ut

Imp

edan

ce (Ω

)

10k 100k

G = 101 V/VG = 11 V/V

G = 1 V/V


MCP621/1S/2/3/4/5/9



FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load.

FIGURE 2-31: Channel-to-Channel Separation vs. Frequency.

0

1

2

3

4

5

6

7

8

9

10

1.0E-11 1.0E-10 1.0E-09Normalized Capacitive Load; CL/GN (F)

Gai

n P

eaki

ng

(d

B)

10p 100p 1n

GN = 1 V/VGN = 2 V/V

GN 4 V/V

50

60

70

80

90

100

110

120

130

140

150

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07Frequency (Hz)

Ch

ann

el-t

o-C

han

nel

Se

par

atio

n (

dB

)

1k 10k 100k

RTIVCM = VDD/2G = +1 V/V

RS = 0ΩRS = 1 kΩ

RS = 10 kΩRS = 100 kΩ

1M 10M


MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.

2.4 Input Noise and Distortion

FIGURE 2-32: Input Noise Voltage Density vs. Frequency.

FIGURE 2-33: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz.

FIGURE 2-34: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz.

FIGURE 2-35: Input Noise plus Offset vs. Time with 0.1 Hz Filter.

FIGURE 2-36: THD+N vs. Frequency.

1.E+1

1.E+2

1.E+3

1.E+4

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7Frequency (Hz)

0.1 100 10k 1MInp

ut

No

ise

Vo

ltag

e D

en

sit

y (n

V/

Hz)

1 1k 100k 10M1010n

100n

1µ

10µ

0

50

100

150

200

250

300

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0


VDD = 5.5V

VDD = 2.5V

Inp

ut

No

ise

Vo

ltag

e D

ensi

ty(n

V/

Hz)

f = 100 Hz

0

5

10

15

20

25

30

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5



Inp

ut

No

ise

Vo

ltag

e D

ensi

ty(n

V/

Hz)

f = 1 MHz

-20

-15

-10

-5

0

5

10

15

20

0 5 10 15 20 25 30 35 40 45Time (min)

Inp

ut

Off

set

+ N

ois

e;V

OS +

en

i(t)

(µV

)

Representative PartAnalog NPBW = 0.1 HzSample Rate = 2 SPS

0.0001

0.001

0.01

0.1

1

1.E+2 1.E+3 1.E+4 1.E+5

Frequency (Hz)

TH

D +

No

ise

(%)

VDD = 5.0VVOUT = 2 VP-P

100 1k 10k 100k

BW = 22 Hz to 80 kHz

BW = 22 Hz to > 500 kHzG = 1 V/VG = 11 V/V


MCP621/1S/2/3/4/5/9



2.5 Time Response

FIGURE 2-37: Non-Inverting Small Signal Step Response.

FIGURE 2-38: Non-Inverting Large Signal Step Response.

FIGURE 2-39: Inverting Small Signal Step Response.

FIGURE 2-40: Inverting Large Signal Step Response.

FIGURE 2-41: The MCP621/1S/2/3/4/5/9 Family Shows No Input Phase Reversal with Overdrive.

FIGURE 2-42: Slew Rate vs. Ambient Temperature.

0 20 40 60 80 100 120 140 160 180 200Time (ns)

Ou

tpu

t V

olt

age

(10

mV

/div

) VDD = 5.5VG = 1

VIN VOUT

0.00.51.01.52.02.53.03.54.04.55.05.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0Time (µs)

Ou

tpu

t V

olt

age

(V

)

VDD = 5.5VG = 1

VIN VOUT

0 100 200 300 400 500 600 700 800Time (ns)

Ou

tpu

t V

olt

ag

e (

10 m

V/d

iv)

VDD = 5.5VG = -1RF = 1 kΩ

VIN

VOUT

0.00.51.01.52.02.53.03.54.04.55.05.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0Time (µs)

Ou

tpu

t V

olt

ag

e (

V)

VDD = 5.5VG = -1RF = 1 kΩ

VIN

VOUT

-1

0

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7 8 9 10Time (ms)

Inp

ut,

Ou

tpu

t V

olt

ages

(V

)VDD = 5.5VG = 2

VOUT

VIN

02468

1012141618202224


Sle

w R

ate

(V

/µs

)

Falling Edge

Rising

VDD = 2.5V

VDD = 5.5V


MCP621/1S/2/3/4/5/9



FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency.

0.1

1

10

1.E+05 1.E+06 1.E+07 1.E+08Frequency (Hz)

Ma

xim

um

Ou

tpu

t V

olt

ag

eS

win

g (

VP

-P)

VDD = 5.5V

VDD = 2.5V

100k 1M 10M 100M


MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.

2.6 Calibration and Chip Select Response

FIGURE 2-44: CAL/CS Current vs. Power Supply Voltage.

FIGURE 2-45: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 2.5V.

FIGURE 2-46: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 5.5V.

FIGURE 2-47: CAL/CS Hysteresis vs. Ambient Temperature.

FIGURE 2-48: CAL/CS Turn-On Time vs. Ambient Temperature.

FIGURE 2-49: CAL/CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5Power Supply Voltage (V)

CA

L/C

S C

urr

ent

(µA

)

CAL/CS = VDD

-1

0

1

2

3

4

5

6

7

8

0 2 4 6 8 10 12 14 16Time (ms)

CA

L/C

S, V

OU

T (

V)

-12

-10

-8

-6

-4

-2

0

2

4

6

Po

we

r S

up

ply

Cu

rren

t;I D

D (

mA

)

VDD = 2.5VG = 1VL = 0V

Op Ampturns on

CAL/CS

Op Ampturns off

Calibrationstarts

IDD

VOUT

-2

0

2

4

6

8

10

12

14

16

0 2 4 6 8 10 12 14 16Time (ms)

CA

L/C

S, V

OU

T (

V)

-12

-10

-8

-6

-4

-2

0

2

4

6

Po

we

r S

up

ply

Cu

rren

t;I D

D (

mA

)

VDD = 5.5VG = 1VL = 0V

Op Ampturns on

CAL/CS

Op Ampturns off

Calibrationstarts

IDD

VOUT

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40


CA

L/C

S H

ys

tere

sis

(V

)

VDD = 2.5V

VDD = 5.5V

0

1

2

3

4

5

6

7

8

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CA

L/C

S T

urn

On

Tim

e (

ms)

0

1

2

3

4

5

6

7

8


CA

L/C

S P

ull

-do

wn

Res

isto

r(M

Ω)

Representative Part


MCP621/1S/2/3/4/5/9



FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage.

FIGURE 2-51: Output Leakage Current vs. Output Voltage.

-7

-6

-5

-4

-3

-2

-1

00.

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5


Neg

ativ

e P

ow

er S

up

ply

Cu

rren

t; I

SS (

µA

)

CAL/CS = VDD

+125°C+85°C+25°C-40°C

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0Output Voltage (V)

Ou

tpu

t L

eak

ag

e C

urr

en

t (A

)

+25°C

+125°C

+85°C

CAL/CS = VDD = 5.5V


2

00

9-2

01

4 M

icroch

ip T

ech

no

log

y Inc.

DS

20

00

21

88

D-p

ag

e 2

0

MC

P621/1S

/2/3/4/5/9

3.

De

TA

DescriptionS

nput (op amp A)

ting Input (op amp A)

ower Supply

ting Input (op amp B)

nput (op amp B)

amp B)

Chip Select Digital Input B and C)

amp C)

nput (op amp C)

ting input (op amp C)

ower Supply

ting input (op amp D)

nput (op amp D)

amp D)

Chip Select Digital Input A and D)

amp A)

hermal Pad (EP);onnected to VSS

Chip Select Digital Input (op amp A)

Chip Select Digital Input (op amp B)

Common Mode Voltage Input

l Connection

0 PIN DESCRIPTIONS

scriptions of the pins are listed in Table 3-1.

BLE 3-1: PIN FUNCTION TABLE

MCP621 MCP621S MCP622 MCP623 MCP624 MCP625 MCP629Symbol

OIC TDFN SOT-23 SOIC DFN SOT-23 SOIC TSSOP MSOP DFN QFN

2 2 4 2 2 4 2 2 2 2 1 VIN–, VINA– Inverting I

3 3 3 3 3 3 3 3 3 3 2 VIN+, VINA+ Non-inver

7 7 5 8 8 6 4 4 10 10 3 VDD Positive P

— — — 5 5 — 5 5 7 7 4 VINB+ Non-inver

— — — 6 6 — 6 6 8 8 5 VINB– Inverting I

— — — 7 7 — 7 7 9 9 6 VOUTB Output (op

— — — — — — — — — — 7 CALBC/CSBC Calibrate/(op amps

— — — — — — 8 8 — — 8 VOUTC Output (op

— — — — — — 9 9 — — 9 VINC– Inverting I

— — — — — — 10 10 — — 10 VINC+ Non-inver

4 4 2 4 4 2 11 11 4 4 11 VSS Negative P

— — — — — — 12 12 — — 12 VIND+ Non-inver

— — — — — — 13 13 — — 13 VINDD– Inverting I

— — — — — — 14 14 — — 14 VOUTD Output (op

— — — — — — — — — — 15 CALAD/CSAD Calibrate/(op amps

6 6 1 1 1 1 1 1 1 1 16 VOUT, VOUTA Output (op

— 9 — — 9 — — — 11 17 EP Exposed Tmust be c

8 8 — — — 5 — — 5 5 — CAL/CS, CALA/CSA

Calibrate/

— — — — — — — — 6 6 — CALB/CSB Calibrate/

5 5 — — — — — — — — — VCAL Calibration

1 1 — — — — — — — — — NC No Interna

MCP621/1S/2/3/4/5/9

3.1 Analog Outputs

The analog output pins (VOUT) are low-impedancevoltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs (VIN+, VIN–, …)are high-impedance CMOS inputs with low biascurrents.

3.3 Power Supply Pins

The positive power supply (VDD) is 2.5V to 5.5V higherthan the negative power supply (VSS). For normaloperation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)supply configuration. In this case, VSS is connected toground and VDD is connected to the supply. VDD willneed bypass capacitors.

3.4 Calibration Common Mode Voltage Input

A low-impedance voltage placed at this input (VCAL)will set the op amps’ Common mode input voltageduring calibration. If this pin is left open, the Commonmode input voltage during calibration is approximatelyVDD/3. The internal resistor divider is disconnectedfrom the supplies whenever the part is not incalibration.

3.5 Calibrate/Chip Select Digital Input

This input (CAL/CS, …) is a CMOS, Schmitt-triggeredinput that affects the Calibration and Low-Powermodes of operation. When this pin goes high, the partis placed into a Low-Power mode and the output isHigh Z. When this pin goes low, a calibration sequenceis started (which corrects VOS). At the end of the cali-bration sequence, the output becomes low-impedanceand the part resumes normal operation.

An internal POR triggers a calibration event when thepart is powered-on, or when the supply voltage dropstoo low. Thus, the MCP622 parts are calibrated, eventhough they do not have a CAL/CS pin.

3.6 Exposed Thermal Pad (EP)

There is an internal connection between the ExposedThermal Pad (EP) and the VSS pin; they must beconnected to the same potential on the Printed CircuitBoard (PCB).

This pad can be connected to a PCB ground plane toprovide a larger heat sink. This improves the packagethermal resistance (JA).


MCP621/1S/2/3/4/5/9

4.0 APPLICATIONS

The MCP621/1S/2/3/4/5/9 family of self-zeroed opamps is manufactured using Microchip’s state-of-the-art CMOS process. It is designed for low-cost, low-power and high-precision applications. Its low supplyvoltage, low quiescent current and wide bandwidthmakes the MCP621/1S/2/3/4/5/9 ideal for battery-powered applications.

4.1 Calibration and Chip Select

These op amps include circuitry for dynamic calibrationof the offset voltage (VOS).

4.1.1 mCal CALIBRATION CIRCUITRY

The internal mCal circuitry, when activated, starts adelay timer (to wait for the op amp to settle to its newbias point), then calibrates the input offset voltage(VOS). The mCal circuitry is triggered at power-up (andafter some power brown-out events) by the internalPOR, and by the memory’s parity detector. Thepower-up time, when the mCal circuitry triggers thecalibration sequence, is 200 ms (typical).

4.1.2 CAL/CS PIN

The CAL/CS pin gives the user a means to externallydemand a Low-Power mode of operation, then tocalibrate VOS. Using the CAL/CS pin makes it possibleto correct VOS as it drifts over time (1/f noise and aging;see Figure 2-35) and across temperature.

The CAL/CS pin performs two functions: it places theop amp(s) in a Low-Power mode when it is held high,and starts a calibration event (correction of VOS) after arising edge.

While in the Low-Power mode, the quiescent current isquite small (ISS = -3 µA, typical). The output is also in aHigh Z state.

During the calibration event, the quiescent current isnear, but smaller than, the specified quiescent current(2.5 mA, typical). The output continues in the High Zstate, and the inputs are disconnected from theexternal circuit, to prevent internal signals fromaffecting circuit operation. The op amp inputs areinternally connected to a Common mode voltage bufferand feedback resistors. The offset is corrected (using adigital state machine, logic and memory), and thecalibration constants are stored in memory.

Once the calibration event is completed, the amplifier isreconnected to the external circuitry. The turn-on time,when calibration is started with the CAL/CS pin, is 5 ms(typical).

There is an internal 5 M pull-down resistor tied to theCAL/CS pin. If the CAL/CS pin is left floating, theamplifier operates normally.

For the MCP625 dual and the MCP629 quad, there isan additional constraint on toggling the two CAL/CSpins close together; see the tCON specification inTable 1-3. If the two pins are toggled simultaneously, orif they are toggled separately with an adequate delaybetween them (greater than tCON), then the CAL/CSinputs are accepted as valid. If one of the two pinstoggles, while the other pin’s calibration routine is inprogress, then an invalid input occurs and the result isunpredictable.

4.1.3 INTERNAL POR

This part includes an internal Power-on Reset (POR) toprotect the internal calibration memory cells. The PORmonitors the power supply voltage (VDD). When thePOR detects a low VDD event, it places the part into theLow-Power mode of operation. When the POR detectsa normal VDD event, it starts a delay counter, thentriggers a calibration event. The additional delay givesa total POR turn-on time of 200 ms (typical); this is alsothe power-up time (since the POR is triggered at powerup).

4.1.4 PARITY DETECTOR

A parity error detector monitors the memory contentsfor any corruption. In the rare event that a parity error isdetected (e.g., corruption from an alpha particle), aPOR event is automatically triggered. This will causethe input offset voltage to be recorrected, and the opamp will not return to normal operation for a period oftime (the POR turn-on time, tPON).

4.1.5 CALIBRATION INPUT PIN

A VCAL pin is available in some options (e.g., the singleMCP621) for those applications that need thecalibration to occur at an internally driven Commonmode voltage other than VDD/3.

Figure 4-1 shows the reference circuit that internallysets the op amp’s Common mode reference voltage(VCM_INT) during calibration (the resistors aredisconnected from the supplies at other times). The5 k resistor provides overcurrent protection for thebuffer.

FIGURE 4-1: Common-Mode Reference’s Input Circuitry.

To op amp during

VCALBUFFER

5 k300 k

150 k

VSS

VDDcalibration

VCM_INT


MCP621/1S/2/3/4/5/9

When the VCAL pin is left open, the internal resistordivider generates a VCM_INT of approximately VDD/3,which is near the center of the input Common modevoltage range. It is recommended that an externalcapacitor from VCAL to ground be added to improvenoise immunity.

When the VCAL pin is driven by an external voltagesource, which is within its specified range, the op ampwill have its input offset voltage calibrated at thatCommon mode input voltage. Make sure that VCAL iswithin its specified range.

It is possible to use an external resistor voltage dividerto modify VCM_INT; see Figure 4-2. The internal circuitryat the VCAL pin looks like 100 k tied to VDD/3. Theparallel equivalent of R1 and R2 should be muchsmaller than 100 k to minimize differences in match-ing and temperature drift between the internal andexternal resistors. Again, make sure that VCAL is withinits specified range.

FIGURE 4-2: Setting VCM with External Resistors.

For instance, a design goal to set VCM_INT = 0.1V whenVDD = 2.5V could be met with: R1 = 24.3 k,R2 = 1.00 k and C1 = 100 nF. This will keep VCALwithin its range for any VDD, and should be closeenough to 0V for ground-based applications.

4.2 Input

4.2.1 PHASE REVERSAL

The input devices are designed to not exhibit phaseinversion when the input pins exceed the supplyvoltages. Figure 2-41 shows an input voltageexceeding both supplies with no phase inversion.

4.2.2 INPUT VOLTAGE AND CURRENT LIMITS

The ESD protection on the inputs can be depicted asshown in Figure 4-3. This structure was chosen toprotect the input transistors, and to minimize input biascurrent (IB). The input ESD diodes clamp the inputswhen they try to go more than one diode drop belowVSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough toallow normal operation, and low enough to bypassquick ESD events within the specified limits.

FIGURE 4-3: Simplified Analog Input ESD Structures.

In order to prevent damage and/or improper operationof these amplifiers, the circuit must limit the currents(and voltages) at the input pins (see Section 1.1“Absolute Maximum Ratings †”). Figure 4-4 showsthe recommended approach to protecting these inputs.The internal ESD diodes prevent the input pins (VIN+and VIN–) from going too far below ground, and theresistors R1 and R2 limit the possible current drawn outof the input pins. Diodes D1 and D2 prevent the inputpins (VIN+ and VIN–) from going too far above VDD, anddump any currents onto VDD. When implemented asshown, resistors R1 and R2 also limit the currentthrough D1 and D2.

FIGURE 4-4: Protecting the Analog Inputs.

It is also possible to connect the diodes to the left of theresistor R1 and R2. In this case, the currents throughthe diodes D1 and D2 need to be limited by some othermechanism. The resistors then serve as in-rush currentlimiters; the DC current into the input pins (VIN+ andVIN–) should be very small.

R1

R2

VSS

VDD

VCALC1

MCP62X

BondPad

BondPad

BondPad

VDD

VIN+

VSS

InputStage

BondPad

VIN–

V1

R1

VDD

D1

R1 >VSS – (minimum expected V1)

2 mA

VOUT

R2 >VSS – (minimum expected V2)

2 mA

V2R2

D2

MCP62X


MCP621/1S/2/3/4/5/9

A significant amount of current can flow out of theinputs (through the ESD diodes) when the Commonmode voltage (VCM) is below ground (VSS); seeFigure 2-15. Applications that are high-impedance mayneed to limit the usable voltage range.

4.2.3 NORMAL OPERATION

The input stage of the MCP621/1S/2/3/4/5/9 op ampsuse a differential PMOS input stage. It operates at lowCommon mode input voltage (VCM), with VCM up toVDD – 1.3V and down to VSS – 0.3V. The input offsetvoltage (VOS) is measured at VCM = VSS – 0.3V andVDD – 1.3V to ensure proper operation. See Figure 2-6and Figure 2-7 for temperature effects.

When operating at very low non-inverting gains, theoutput voltage is limited at the top by the VCM range(< VDD – 1.3V); see Figure 4-5.

FIGURE 4-5: Unity Gain Voltage Limitations for Linear Operation.

4.3 Rail-to-Rail Output

4.3.1 MAXIMUM OUTPUT VOLTAGE

The Maximum Output Voltage (see Figure 2-16 andFigure 2-17) describes the output range for a givenload. For instance, the output voltage swings to within40 mV of the negative rail with a 2 k load tied toVDD/2.

4.3.2 OUTPUT CURRENT

Figure 4-6 shows the possible combinations of outputvoltage (VOUT) and output current (IOUT). IOUT ispositive when it flows out of the op amp into theexternal circuit.

FIGURE 4-6: Output Current.

4.3.2.1 Power Dissipation

Since the output short-circuit current (ISC) is specifiedat ±70 mA (typical), these op amps are capable of bothdelivering and dissipating significant power.Two common loads, and their impact on the op amp’spower dissipation, will be discussed.

Figure 4-7 shows a resistive load (RL) with a DC outputvoltage (VOUT). VL is RL’s ground point, VSS is usuallyground (0V) and IOUT is the output current. The inputcurrents are assumed to be negligible.

FIGURE 4-7: Diagram for Resistive Load Power Calculations.

The DC currents are:

EQUATION 4-1:

The DC op amp power is:

EQUATION 4-2:

The maximum op amp power, for resistive loads at DC,occurs when VOUT is halfway between VDD and VL, orhalfway between VSS and VL:

EQUATION 4-3:

VIN

VDD

VOUT

VSS VIN

VOUT

VDD 1.3V–

MCP62X

-0.50.00.51.01.52.02.53.03.54.04.55.05.56.0

-80

-60

-40

-20 0 20 40 60 80

IOUT (mA)

VO

UT (

V)

RL = 10Ω

RL = 100ΩRL = 2 kΩ

VOH Limited

VOL Limited

-IS

C L

imite

d

+I S

C L

imite

d

(VDD = 5.5V)

VDD

VOUT

RL

VL

IDD

ISS

IOUT

VSS

MCP62X

IOUT

VOUT VL–RL

--------------------------=

IDD IQ max 0 IOUT, +

ISS I– Q min 0 IOUT, +

Where:

IQ = Quiescent supply current for one op amp (mA/amplifier)

VOUT = A DC value (V)

POA IDD VDD VOUT– ISS VSS VOUT– +=

max POA IDD VDD VSS– =

max

2VDD VL– VL VSS–

4RL------------------------------------------------------------------+


MCP621/1S/2/3/4/5/9

Figure 4-7 shows a capacitive load (CL), which isdriven by a sine wave with DC offset. The capacitiveload causes the op amp to output higher currents athigher frequencies. Because the output rectifies IOUT,the op amp’s dissipated power increases (even thoughthe capacitor does not dissipate power).

FIGURE 4-8: Diagram for Capacitive Load Power Calculations.

The output voltage is assumed to be:

EQUATION 4-4:

The op amp’s currents are:

EQUATION 4-5:

The op amp’s instantaneous power, average powerand peak power are:

EQUATION 4-6:

The power dissipated in a package depends on thepowers dissipated by each op amp in that package:

EQUATION 4-7:

The maximum ambient-to-junction temperature rise(TJA) and junction temperature (TJ) can be calculatedusing the maximum expected package power (PPKG),ambient temperature (TA) and the package thermalresistance (JA) found in Table 1-4:

EQUATION 4-8:

The worst-case power derating for the op amps in aparticular package can be easily calculated:

EQUATION 4-9:

Several techniques are available to reduce TJA for agiven package:

• Reduce JA

- Use another package

- Improve the PCB layout (ground plane, etc.)

- Add heat sinks and air flow

• Reduce max (PPKG)

- Increase RL

- Decrease CL

- Limit IOUT using RISO (see Figure 4-9)

- Decrease VDD

CL

VDD

VOUT

IDD

ISS

IOUT

VSS

MCP62X

VOUT VDC VAC t sin+=

Where:

VDC = DC offset (V)

VAC = Peak output swing (VPK)

= Radian frequency (2 f) (rad/s)

IOUT CL

dVOUT

dt----------------- VACCL t cos= =

IDD IQ max 0 IOUT, +ISS I– Q min 0 IOUT, +

Where:

IQ = Quiescent supply current for one op amp (mA/amplifier)

POA IDD VDD VOUT– ISS VSS VOUT– +=

ave POA VDD VSS– IQ

4VAC fCL

------------------------+

=

max POA VDD VSS– IQ 2VAC fCL+ =

PPKG POA

k 1=

n

=

Where:

n = Number of op amps in package (1 or 2)

TJA PPKGJA=

TJ TA TJA+=

PPKG

TJmax TA–JA

--------------------------

Where:

TJmax = Absolute maximum junction temperature (°C)

TA = Ambient temperature (°C)


MCP621/1S/2/3/4/5/9

4.4 Improving Stability

4.4.1 CAPACITIVE LOADS

Driving large capacitive loads can cause stabilityproblems for voltage feedback op amps. As the loadcapacitance increases, the feedback loop’s phasemargin decreases and the closed-loop bandwidth isreduced. This produces gain peaking in the frequencyresponse, with overshoot and ringing in the stepresponse. See Figure 2-30. A unity gain buffer (G = +1)is the most sensitive to capacitive loads, though allgains show the same general behavior.

When driving large capacitive loads with these opamps (e.g., > 10 pF when G = +1), a small seriesresistor at the output (RISO in Figure 4-9) improves thefeedback loop’s phase margin (stability) by making theoutput load resistive at higher frequencies. Thebandwidth will be generally lower than the bandwidthwith no capacitive load.

FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads.

Figure 4-10 gives recommended RISO values fordifferent capacitive loads and gains. The x-axis is thenormalized load capacitance (CL/GN), where GN is thecircuit’s noise gain. For non-inverting gains, GN and theSignal Gain are equal. For inverting gains, GN is1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-10: Recommended RISO Values for Capacitive Loads.

After selecting RISO, double check the resulting fre-quency response peaking and step response over-shoot. Modify RISO’s value until the response isreasonable. Bench evaluation and simulations with theMCP621/1S/2/3/4/5/9 SPICE macro model are helpful.

4.4.2 GAIN PEAKING

Figure 4-11 shows an op amp circuit that representsnon-inverting amplifiers (VM is a DC voltage and VP isthe input) or inverting amplifiers (VP is a DC voltageand VM is the input). The capacitances CN and CGrepresent the total capacitance at the input pins; theyinclude the op amp’s Common mode input capacitance(CCM), board parasitic capacitance and any capacitorplaced in parallel.

FIGURE 4-11: Amplifier with Parasitic Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/V),which causes an increase in gain at high frequencies.CG also reduces the phase margin of the feedbackloop, which becomes less stable. This effect can bereduced by either reducing CG or RF.

CN and RN form a low-pass filter that affects the signalat VP. This filter has a single real pole at 1/(2RNCN).

The largest value of RF that should be used dependson noise gain (see GN in Section 4.4.1 “CapacitiveLoads”) and CG. Figure 4-12 shows the maximumrecommended RF for several CG values.

FIGURE 4-12: Maximum Recommended RF vs. Gain.

Figures 2-37 and 2-38 show the small signal and largesignal step responses at G = +1 V/V. The unity gainbuffer usually has RF = 0 and RG open.

Figures 2-39 and 2-40 show the small signal and largesignal step responses at G = -1 V/V. Since the noisegain is 2 V/V and CG 10 pF, the resistors werechosen to be RF = RG = 1k and RN = 500.

RISO

VOUT

CL

RG RF

RNMCP62X

1

10

100

1,000

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08Normalized Capacitance; CL/GN (F)

Rec

om

men

ded

RIS

O (Ω

)

GN = +1

GN +2

1p 100p 1n 10n10p

VP

RF

VOUT

RNCN

VMRG CG

MCP62X

1.E+02

1.E+03

1.E+04

1.E+05

1 10 100Noise Gain; GN (V/V)

Max

imu

m R

eco

mm

end

ed R

F

(Ω)

GN > +1 V/V

100

10k

100k

1k

CG = 10 pFCG = 32 pF

CG = 100 pFCG = 320 pF

CG = 1 nF


MCP621/1S/2/3/4/5/9

It is also possible to add a capacitor (CF) in parallel withRF to compensate for the destabilizing effect of CG.This makes it possible to use larger values of RF.The conditions for stability are summarized inEquation 4-10.

EQUATION 4-10:

4.5 Power Supply

With this family of operational amplifiers, the powersupply pin (VDD for single supply) should have a localbypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mmfor good high-frequency performance. Surface mount,multilayer ceramic capacitors, or their equivalent,should be used.

These op amps require a bulk capacitor (i.e., 2.2 µF orlarger) within 50 mm to provide large, slow currents.Tantalum capacitors, or their equivalent, may be a goodchoice. This bulk capacitor can be shared with othernearby analog parts as long as crosstalk through thesupplies does not prove to be a problem.

4.6 High Speed PCB Layout

These op amps are fast enough that a little extra carein the PCB (Printed Circuit Board) layout can make asignificant difference in performance. Good PC boardlayout techniques will help you achieve theperformance shown in the specifications and TypicalPerformance Curves; it will also help you minimizeEMC (Electro-Magnetic Compatibility) issues.

Use a solid ground plane. Connect the bypass localcapacitor(s) to this plane with minimal length traces.This cuts down inductive and capacitive crosstalk.

Separate digital from analog, low-speed from high-speed, and low-power from high-power. This willreduce interference.

Keep sensitive traces short and straight. Separatethem from interfering components and traces. This isespecially important for high-frequency (low rise time)signals.

Sometimes, it helps to place guard traces next to victimtraces. They should be on both sides of the victimtrace, and as close as possible. Connect guard tracesto ground plane at both ends, and in the middle for longtraces.

Use coax cables, or low-inductance wiring, to route thesignal and power to and from the PCB. Mutual and self-inductance of power wires is often a cause of crosstalkand unusual behavior.

4.7 Typical Applications

4.7.1 POWER DRIVER WITH HIGH GAIN

Figure 4-13 shows a power driver with high gain(1 + R2/R1). The MCP621/1S/2/3/4/5/9 op amp’s short-circuit current makes it possible to drive significantloads. The calibrated input offset voltage supportsaccurate response at high gains. R3 should be small,and equal to R1||R2, in order to minimize the biascurrent induced offset.

FIGURE 4-13: Power Driver.

4.7.2 OPTICAL DETECTOR AMPLIFIER

Figure 4-14 shows a transimpedance amplifier, usingthe MCP621 op amp, in a photo detector circuit. Thephoto detector is a capacitive current source. The opamp’s input Common mode capacitance (9 pF, typical)and Differential capacitance (2 pF, typical) act in paral-lel with CD. RF provides enough gain to produce 10 mVat VOUT. CF stabilizes the gain and limitsthe transimpedance bandwidth to about 0.51 MHz.RF’s parasitic capacitance (e.g., 0.15 pF for a0603 SMD) acts in parallel with CF.

FIGURE 4-14: Transimpedance Amplifier for an Optical Detector.

fF fGBWP 2GN2 , GN1 GN2<We need:

GN1 1 RF RG+=

GN2 1 CG CF+=

fF 1 2RFCF =

fZ fF GN1 GN2 =

Given:

fF fGBWP 4GN1 , GN1 GN2>R1 R2

VIN

VDD/2 VOUT

R3 RL

MCP62X

PhotoDetector

CD

CF

RF

VDD/2

30pF

100 k

3 pF

ID100 nA

VOUT

MCP621


MCP621/1S/2/3/4/5/9

4.7.3 H-BRIDGE DRIVER

Figure 4-15 shows the MCP622 dual op amp used asa H-bridge driver. The load could be a speaker or a DCmotor.

FIGURE 4-15: H-Bridge Driver.

This circuit automatically makes the noise gains (GN)equal, when the gains are set properly, so that thefrequency responses match well (in magnitude and inphase). Equation 4-11 shows how to calculate RGT andRGB so that both op amps have the same DC gains;GDM needs to be selected first.

EQUATION 4-11:

Equation 4-12 gives the resulting Common mode andDifferential mode output voltages.

EQUATION 4-12:

RFRF

VIN

VOT

RFRGBVOB

VDD/2

RGTRL

½ MCP622

½ MCP622

GDM

VOT VOB–VIN VDD 2–-------------------------------- 2 V/V

RGT

RF

GDM 2 1–---------------------------------=

RGB

RF

GDM 2-------------------=

VOT V+OB

2---------------------------

VDD

2-----------=

VOT V–OB

GDM VIN

VDD

2-----------–

=


MCP621/1S/2/3/4/5/9

5.0 DESIGN AIDS

Microchip provides the basic design aids needed forthe MCP621/1S/2/3/4/5/9 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for theMCP621/1S/2/3/4/5/9 op amps is available on theMicrochip web site at www.microchip.com. This modelis intended to be an initial design tool that works well inthe op amp’s linear region of operation over thetemperature range. See the model file for informationon its capabilities.

Bench testing is a very important part of any design andcannot be replaced with simulations. Also, simulationresults using this macro model need to be validated bycomparing them to the data sheet specifications andcharacteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovativesoftware tool that simplifies analog active filter (usingop amps) design. Available at no cost from theMicrochip web site at www.microchip.com/filterlab, theFilter-Lab design tool provides full schematic diagramsof the filter circuit with component values. It alsooutputs the filter circuit in SPICE format, which can beused with the macro model to simulate actual filterperformance.

5.3 Microchip Advanced Part Selector (MAPS)

MAPS is a software tool that helps efficiently identifyMicrochip devices that fit a particular designrequirement. Available at no cost from the Microchipweb site at www.microchip.com/maps, the MAPS is anoverall selection tool for Microchip’s product portfoliothat includes Analog, Memory, MCUs and DSCs. Usingthis tool, a customer can define a filter to sort featuresfor a parametric search of devices and exportside-by-side technical comparison reports. Helpful linksare also provided for data sheets, purchase andsampling of Microchip parts.

5.4 Analog Demonstration and Evaluation Boards

Microchip offers a broad spectrum of AnalogDemonstration and Evaluation Boards that aredesigned to help customers achieve faster time tomarket. For a complete listing of these boards and theircorresponding user’s guides and technical information,visit the Microchip web site atwww.microchip.com/analog tools.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1




• Active Filter Demo Board Kit

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV

5.5 Application Notes

The following Microchip Application Notes areavailable on the Microchip web site at www.microchip.com/appnotes and are recommended as supplementalreference resources.

• ADN003: “Select the Right Operational Amplifier for your Filtering Circuits” (DS21821)

• AN722: “Operational Amplifier Topologies and DC Specifications” (DS00722)

• AN723: “Operational Amplifier AC Specifications and Applications” (DS00723)

• AN884: “Driving Capacitive Loads With Op Amps” (DS00884)

• AN990: “Analog Sensor Conditioning Circuits – An Overview” (DS00990)

• AN1177: “Op Amp Precision Design: DC Errors” (DS01177)

• AN1228: “Op Amp Precision Design: Random Noise” (DS01228)

• AN1332: “Current Sensing Circuit Concepts and Fundamentals” (DS01332)

Some of these application notes, and others, are listedin the design guide:

• “Signal Chain Design Guide” (DS21825)


www.microchip.com/filterlab



www.microchip.com

www.microchip.com

www.microchip.com/analogtools

www.microchip.com/analogtools

http://www.microchip.com/wwwcategory/TaxonomySearch.aspx?show=Application%20Notes&ShowField=no

http://www.microchip.com/wwwcategory/TaxonomySearch.aspx?show=Application%20Notes&ShowField=no

http://www.microchip.com/maps/main.aspx???

http://www.microchip.com/maps/main.aspx???

MCP621/1S/2/3/4/5/9

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

Device Code

MCP622T-E/MF DABL

Note: Applies to 8-Lead 3x3 DFN

Example:5-Lead SOT-23 (MCP621S)

8-Lead TDFN (2 x 3) (MCP621) Example:

8-Lead DFN (3x3) (MCP622) Example

6-Lead SOT-23 ( MCP623) Example

XXNN YU25

XXNN JB25

AAY12925

DABL1129256


MCP621/1S/2/3/4/5/9

Package Marking Information (Continued)

14-Lead SOIC (.150”) (MCP624) Example

14-Lead TSSOP (MCP624)

10-Lead DFN (3x3) (MCP625)

10-Lead MSOP (MCP625) Example:

Device Code

MCP625T-E/MF BAFA

Note: Applies to 10-Lead 3x3 DFN

8-Lead SOIC (150 mil) (MCP621, MCP622) Example:

Example

Example

NNN

MCP621ESN ^^1129

2563e

BAFA1129256

625EUN129256

MCP624

E/SL ^^1129256

3e

YYWWNNN

XXXXXXXX 624E/ST1129256

16-Lead QFN (4x4) (MCP629) Example

PIN 1 PIN 1 629E/ML ^^129256

3e


MCP621/1S/2/3/4/5/9

!"!#$! !% #$ !% #$ # & ! ! !# "'(

)*+ ) # &#,$ --#$##

.# #$ #/ !- 0 # 1/ %## !###+22---2/

3# 44"" 4# 5 56 7

5$8 %1 5 (4 !1# ()*6$# ! 4 !1# )*6, 9 # : (! !1/ / ; : #!%% : (6, <!# " : ! !1/ <!# " : ;6, 4 # : .#4 # 4 : =.## 4 ( : ;.# > : >4 !/ ; : =4 !<!# 8 : (

φ

Nb

E

E1

D

1 2 3

e

e1

A

A1

A2 c

L

L1

- *)


MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


MCP621/1S/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Notes:1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.


Units MILLIMETERSDimension Limits MIN NOM MAX

Number of Pins N 6Pitch e 0.95 BSCOutside Lead Pitch e1 1.90 BSCOverall Height A 0.90 – 1.45Molded Package Thickness A2 0.89 – 1.30Standoff A1 0.00 – 0.15Overall Width E 2.20 – 3.20Molded Package Width E1 1.30 – 1.80Overall Length D 2.70 – 3.10Foot Length L 0.10 – 0.60Footprint L1 0.35 – 0.80Foot Angle 0° – 30°Lead Thickness c 0.08 – 0.26Lead Width b 0.20 – 0.51

b

E

4N

E1

PIN 1 ID BYLASER MARK

D

1 2 3

e

e1

A

A1

A2 c

LL1

φ

Microchip Technology Drawing C04-028B


MCP621/1S/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9

!"#$%&'**+,./0!"

.# #$ #/ !- 0 # 1/ %## !###+22---2/


MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9

'1#,4+/057

.# #$ #/ !- 0 # 1/ %## !###+22---2/


MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9


UN


MCP621/1S/2/3/4/5/9


UN


MCP621/1S/2/3/4/5/9

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9

.# #$ #/ !- 0 # 1/ %## !###+22---2/


MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9



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MCP621/1S/2/3/4/5/9




MCP621/1S/2/3/4/5/9

APPENDIX A: REVISION HISTORY

Revision D (July 2014)

The following is the list of modifications:

1. Updated the title of the document.

2. Added the High Gain-Bandwidth Op AmpPortfolio table and updated all sections onpage 1.

Revision C (August 2011)


1. Added the MCP621S and MCP623 amplifiers tothe product family and the related informationthroughout the document.

2. Added the 2x3 TDFN (8L) package option forMCP621, SOT-23 (5L) package for MCP621Sand SOT-23 (6L) package option for MCP623and the related information throughout thedocument.

3. Updated Section 6.0 “Packaging Informa-tion” with markings for the new additions.Added the corresponding SOT-23 (5L), SOT-23(6L) and 2x3 TDFN (8L) package options andrelated information.

4. Updated table description and examples inProduct Identification System.

Revision B (June 2011)


1. Added the MCP624 and MCP629 amplifiers tothe product family and the related informationthroughout the document.

2. Added the corresponding SOIC (14L), TSSOP(14L) and QFN (16L) package options andrelated information.

Revision A (June 2009)

• Original Release of this Document.

MCP621/1S/2/3/4/5/9


PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP621: Single Op AmpMCP621T: Single Op Amp (Tape and Reel)

(SOIC)MCP621S: Single Op Amp (SOT-23)MCP622: Dual Op AmpMCP622T: Dual Op Amp (Tape and Reel)

(DFN and SOIC)MCP623T: Single Op Amp (Tape and Reel) (SOT-23)MCP624: Quad Op AmpMCP624T: Quad Op Amp (Tape and Reel)

(TSSOP and SOIC)MCP625: Dual Op AmpMCP625T: Dual Op Amp (Tape and Reel)

(DFN and MSOP)MCP629: Quad Op AmpMCP629T: Quad Op Amp (Tape and Reel)

(QFN)

Temperature Range:

E = -40°C to +125°C

Package: CHY = Plastic Small Outline (SOT-23), 6-leadMF = Plastic Dual Flat, No Lead (3x3 DFN),

8-lead, 10-leadML = Plastic Quad Flat, No Lead Package (4x4 QFN),

(4x4x0.9 mm), 16-leadMNY = Plastic Dual Flat, No Lead (2x3 TDFN),

8-leadOT = Plastic Small Outline (SOT-23), 5-leadSN = Plastic Small Outline, (3.90 mm), 8-leadST = Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),

14-lead SL = Plastic Small Outline, Narrow, (3.90 mm SOIC),

14-leadUN = Plastic Micro Small Outline, (MSOP), 10-lead

* Y = Nickel palladium gold manufacturing designator. Only available on the TDFN package.

Examples:

a) MCP621T-E/SN: Tape and Reel,Extended temperature,8LD SOIC package

b) MCP621T-E/MNY: Tape and Reel,Extended temperature,8LD TDFN package

c) MCP621ST-E/OT: Tape and Reel,Extended temperature,5LD SOT-23 package

d) MCP622T-E/MF: Tape and Reel,Extended temperature,8LD DFN package

e) MCP622T-E/SN: Tape and Reel,Extended temperature,8LD SOIC package

f) MCP623T-E/CHY: Tape and Reel,Extended temperature,6LD SOT-23 package

g) MCP624T-E/SL: Tape and Reel,Extended temperature,14LD SOIC package

h) MCP624T-E/ST: Tape and Reel,Extended temperature,14LD TSSOP package

i) MCP625T-E/MF: Tape and Reel,Extended temperature,10LD DFN package

j) MCP625T-E/UN: Tape and Reel,Extended temperature,10LD MSOP package

k) MCP629T-E/ML: Tape and Reel,Extended temperature,16LD QFN package

PART NO. -X /XX

PackageTemperatureRange

Device

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

2009-2014 Microchip Technology Inc.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2009-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-63276-381-5

Microchip received ISO/TS-16949:2009 certification for its worldwide

DS20002188D-page 61

headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.com

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Houston, TX Tel: 281-894-5983

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San Jose, CA Tel: 408-735-9110

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03/25/14

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