Memorias Part IV

7/29/2019 Memorias Part IV

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Professor: Jaime Velasco-Medina

Bionanoelectronics Group

Digital System Design

Course


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Digital System Design

Course


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Jaime Velasco-Medina Digital System Design Course 3

Digital System Design Course


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Introduction-

Motivation

Memories Register File

SRAM, DRAM, Flash

New memory devices

Hardware Design:

Data Path Functions

Multipliers, Dividers

Square root, Logarithm

Trigonometric Functions

EmbeddedProcessors

UV5 Processor

NIOS II ProcessorSimulation Practices

Quartus II Tools

Modelsim

DSDC

710013M

FSMs

Controllers

Sequencers

Hardware Design:Control Units


Counters, Sequence detector

Code converter, Motor control

Light controller, n-bit shift-reg.

Vender machine, LFSR

Hardware Design:

Sequential Circuits

Sequential CircuitsLatches, Flip-flops

Counters, Registers

Shift registers, LFSR


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Jaime Velasco-Medina. 2011. All Rights

Reserved.


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Lecture 3-3

Chip Memories
http://www.kenneyjacob.com/wp-content/uploads/2007/11/ist2_588391_multicore_cpu_generic_isolated.jpg


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Flash

Flash

Flash


8/54Jaime Velasco-Medina Digital System Design Course 8

1. Memory-Storage H ierarchy

Access speedHigh

Cost per bitHigh

CapacityLow

Primarystorage

Secondarystorage

Low Low High

CPU

registers

CPUcache

DRAM

Magnetictape

Magneticdisk

Optical disc

Comparison of

storage devices in

terms of cost and

access speedFlash memorysolid-state

disk



2. Cell Structure for F lash Memory

Currentflows from source to drain when asufficient negative charge is

placed on the dielectric material, preventing current flow through the wordline. This is the logical 0 state.

When the dielectric materialis not charged, current flows between the bit and

word lines, which is the logical 1 state.

Word Line

Current Flow

BitLine Control Gate

Floating Gate

Drain Source

DielectricMaterial



2. F lash Memory Cell

Current Flow

(-)(-)(-)(-) Negatively charged electrons

Control Gate

Floating Gate

Word Line

Thin Oxide Layer

Drain Source

BitLine

0(-)(-)(-)(-)(-)(-)(-)



2. F lash Memory Cell

Current Flow

(-)(-)(-)(-) Negatively charged electrons

Control Gate

Floating Gate

Word Line

Thin Oxide Layer

Drain Source

BitLine

1



3. Flash Memory Character istics:Small and large block f lash memory

Flash memorypage andblocksizes are growing

Small block Large block

Page size 512+16 Bytes 2K~8K Bytes

Block size 16K Bytes 128K~256K Bytes

Used for... 1G Bytes

Throughput Low High

Small block now switches to large block



3. F lash Memory Character istics:NOR-type & NAND-type

NOR-type NAND-type

Access unitByte (random read,

sequential write)Page (serial access)

Cost Higher Lower

XIP support Yes NoWrite 8MB/s 20MB/s

Purpose

XIP media (such as

EPROM, EEPROM,

EAROM, and DRAM)

Nonvolatile secondary storage

media (such as hard disk)



3. Single-Level-Cell and Mul ti -Level Cell F lash Memory

MLC has gained its momentum in cost and capacity!

SLC Flash MLC Flash

Cell level 1 2 or 4

Cost17.2 USD /

16G Bytes

5.25 USD /

16G Bytes

Chip density Lower Higher

Access speed Higher Lower

Average cell endurance104~105

W-E cycles*

103~104

W-E cycles

Partial programming Yes (4 times) No (1 time)

Sequential utilization

constraint of pages in a blockNo Yes

*Write-Erase Cycles



D

S

G

3. NOR F lash Array

NOR array, a cell, i.e. a FG transistoris identified by a WL

BL cross

SingleNOR Flash = FG MOSFET


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D

S

G

Source-linesW

ord-lines(WL

)

Bit-lines (BL)

3. NOR F lash Array


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3. NAND F lash Array

NAND Flash cells are organized in strings

Each string is comprised of32/64 cells, connected in series

High density, i.e. high capacity is thus achieved


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3. NAND F lash Array

Bit-lines

SelectTransisto

rs16Word-lines

BSL

GSL


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3. NAND vs NOR Flash M emory

NOR NAND

Capacity 1mb - 32mb 16mb - 512mb

XIP Yes No

Performance Very slow erase

Slow write/fast read

Fast erase/write/read

(long initial latency/fast serial read)

Life span Less than 10% of

NAND

Over 10 times more than NOR

Interface Full memory interface I/O (CLE, ALE, OLE signal toggle)

Access mode Random access Sequential access

Ideal usage Code storage Data storage

Erase block 64kb128kb 8kb64kb

Price High Low


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3. NAND F lash Memory

Why NAND flash memory?

NAND offers

Extremely high cell densities

High capacity

Fast write and erase rates

Low cost

Cost efficientNAND flash memory architecture forXIP (execute-in-place)


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1 Block

4. F lash Memory: NAND F lash Archi tecture

Cache register

Page register

2048 blocks

DQ7

DQ0

1 page = (4K + 224) bytes

1 block = 128 pages

4320 bytes

Page size

4096 224

127

126

43

2

1

Page 0


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4. F lash Memory: NAND F lash Archi tecture

Main data

I/O bus

1 Block =

128 pages

4096 bytes 224 bytes

Spare data

SpareregisterData register


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4. NAND F lash Archi tecture

Block 0Block 1

Block 2

Block 3

1 Page = 2KB

1 Block = 64 pages(128KB)

Write onepage

Erase oneblock


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Current (mA) Random Access (16bit)

Memory $/Gb idle active read write erase

Mobile SDRAMLow power SRAM

Fast SRAMNOR

NAND

48320

6149621

0.50.005

50.030.01

753

653210

90ns55ns

10ns200ns

10.1us

90ns55ns

10ns210.5us200.5us

N.A.N.A.

N.A.12 sec

2 ms

4. Memory Device Character istics

Mobile SDRAM

Good performance & price, but high power consumption

Low-powerSRAM & Fast SRAM

Very good performance, but high cost

NOR & NAND

Cost, power consumption, read/write/erase performance


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4. NAND XIP

NAND flash characteristics

Structure Fixed number of blocks & 32 pages in eachblock

Each page consists of512bytes data &16 bytes spare data for auxiliary

information (bad block id. or ECC data)

Read/write/erase Read/write is performed inpage unit

Erase is performed inblock unit

Reliability

Bad block management

EDC/ECC for bit-flipping

Main data

I/O bus

1 Block=32 pages

512 bytes 16 bytes

Spare data

SpareregisterData register


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5. F lash M emory Problems:

The primary form ofsolid-state non-volatile memory in use today is flash

memory, which is finding use in most roles that used to be filledby hard

drives.

Flash, however, has a number of problems that have led to many efforts to

introduce products to replace it.

Flash is based on the floating gate concept, essentially a modified transistor.

In the floating gate transistor, the gate is attached to a layer that traps

electrons, leaving it switched on (oroff) for extended periods of time.

The floating gate can be re-writtenby passing a large current through the

emitter-collector circuit.


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5. F lash M emory Problems:

It is this large current that is flash's primary drawback, and for a number of

reasons

Each application of the currentphysically degrades the cell, such that the cell

will eventually be unwritable.

Write cycles on the order of105 to 106are typical, limiting flash applications

to roles where constant writing is not common.

The current also requires an external circuitto generate, using a systemknown as a charge pump.

Thepump requires a fairly lengthy charging processes so that writing is much

slower than reading; the pump also requires much more power.

Flash is an "asymmetrical" system, much more so than conventional RAM or

hard drives.

The floating gate suffers leakage that slowly releases the charge. This is

countered through the use ofpowerful surrounding insulators, but these

require a certain physical size.


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5. F lash Cell Scaling Challenges

BasicNAND structure has changed little over time

Main scaling issues:

Few-electron problem

Capacitance limitations

Tunnel and interpoly charge retention

Voltage isolation

Parasitic charge trapping

Read and write noise

State of the art: 25nm NAND


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5. Going 3-D: Three Major Options

Deck-by-deck NANDSOI for upper decks

Vertical NANDVertical cells arranged in vertical strings

Cross-pointRRAM (Resistive RAM) cells: non-volatile memory

Deck-by-Deck

NAND

Vertical NANDCross-point

RRAM


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Memory

devices

New Memory

Devices


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1. New Era Emerging for Memory?

Convergence of many factors/pressures:

Increasing importance ofmemory to user experience.

Our lives are becoming one big shared database, with IOPs (input/output

operations per second) becoming more important than MIPs (million

instructions per second)

BothNAND and DRAMfacing scaling challenges

No hard wall, but increasing complexity

Explosion ofnew memory storage concepts

New storage physics are enabling new usage models

Evolving memory hierarchy

New features, relentless cost reduction, and need forI/O performance are

remaking the memory hierarchy

Memory is moving from a support role to a system role


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2. Al ternative New-Memory Concepts

Explosion ofnew memory concepts:

New storage materials, new storage concepts

Many ideas, varying functionality/cost, most unproven

FeRAM or FRAM (Ferroelectric RAM):

PCM (Phase Change Memory)

CBRAM (Conductive-Bridging RAM):

Polymer FeRAM

MRAM

MOx-RRAM

PolymerRRAM

CNT

Molecular


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FRAM : Ferroelectr ic Random Access Memory

PZT (Pb {ZrTi}O3),perovskite-type structure (ABO3) is commonly used as a

ferroelectric material.

An electric polarization of PZT (shift up/down of Zr/Ti atom) remains after

applying and removing an external electric field, from which a non-volatile

property results.

As a result, thepower consumption required fordata storage is very low.

ElectricField

:Pb :O :Zr/Ti

PZT Crystal Structure


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Carbon Nanostructures

The benefits of FRAM include:

FRAM is 30,000 times faster than E2PROM

FRAM provides 1 million times higher endurance over E2PROM

FRAM offers 200 times lower power consumption than E2PROM

FRAM integrates excellent tamper-prevention techniques

SRAM/DRAM FLASH E2PROM FUJITSU FRAM

Fast unlimitedread/writeaccess

Fast unlimitedR/W access

Slow blockaccess ROM

Fast unlimitedR/W access

Non-volatileVolatile

Power requiredNon-volatile Non-volatile


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2.1 Ferroelectr ic RAM : FeRAM

FeRAM or FRAM (Ferroelectric RAM): is a random access memory similar

in construction to DRAM but uses a ferroelectric layerinstead of a dielectric

layerto achieve non-volatility.

Thebasic idea is that a dielectric, which is normally insulating, can be

made to conduct through a filament orconduction path formed after

application of a sufficiently high voltage.

Advantages overFlash include: lower power, faster write performanceand a much greater maximum number(exceeding 1016 for 3.3 V devices)

ofwrite-erase cycles.

Disadvantages of FeRAM are much lower storage densities than Flash

devices, storage capacity limitations, and higher cost.


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2.2 Conductive-Br idging RAM: CBRAM

CBRAM (Conductive-Bridging RAM) is a new form ofnon-volatile

computer memory

Theprogrammable metallization cell, orPMC

Infineon Technologies, who licensed the technology PCM in 2004, refers

to it as conductive-bridging RAM

PMC is based on thephysical re-location of ions within a solid

electrolyte.

A PMC memory cell is made oftwo solid metal electrodes, one relatively

inert (e.g., tungsten) the otherelectrochemically active (e.g., silver or

copper), with a thin film of the electrolytebetween them.

A control transistorcan also be included in each cell..


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2.2 CBRAM vs RRAM

CBRAM differs from RRAM in that forCBRAM metal ions dissolve readily

in the material between the two electrodes, while forRRAM, the material

between the electrodes requires a high electric field causing local damage

akin to dielectric breakdown, producing a trail of conducting defects

(sometimes called a "filament").

Hence for CBRAM, one electrode must provide the dissolving ions, while for

RRAM, a one-time "forming" step is required to generate the local damage.


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2.3 Phase Change Memory: PCM

Of the emerging RRAMs, PCM is the most mature:

Already in low-volume production

Demonstrated at Gb density vs. other EM at Mb density

Announced by multiple memory companies

PCM has been heavily studied for 10+ years:

Widely publishedlots of good-quality technical content

Chalcogenide-based material understanding is fairly mature

Many active researchers in both industry and academia

Provides insight into other emerging-materials systems:

Many of the RRAMs share similar attributes with PCM


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2.3 Phase Change Memory Concept

Storing mechanism:

Amorphous/polycrystal phases of achalcogenide alloy; example shown

is Ge2Sb2Te5 (GST)

Sensing mechanism:

Resistance change of the GST

Writing mechanism:

Self-heating due to current flow

(Joule effect)

Cell structure:

1 diode, 1 resistor (1D/1R)

Amorphous Crystalline

High resistivity Low resistivity

V

I

Temperature

Time

T

TX

2 3 Wh Ph Ch M i l I i


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2.3 Why Phase Change Mater ials are I nteresting

Amorphous and crystallinephase structures are similar

Easy transition between phase states

Material contains voids and vacancies

Easy movement of atoms

Volume ofcrystalline and amorphous phase closely matched

Large set of materials to choose from for best performance

2 3 Wh Ph Ch M t i l I t ti


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2.3 Why Phase Change Mater ials are I nteresting

Terao, Japanese Journal of Applied Physics 48 (2009) 080001Flash Memory Summit 2011

Ge2Sb2Te5Crystal Liquid Amorphous Crystal

6R

4R8R

10R

2 4 CMO M C ll


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2.4 CMOx Memory Cell

Two terminal memory cells are severely limited by stray

currents.

Some type ofselect device must be used.

Extra select devices (1T or 1D) add complexity orcell area

CMOx Cross-point Memory is engineered to replaceNAND

2 4 CMO M C ll


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2 4 CMO M C ll


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CMOx uses Oxygen physics to surpass NAND

2 4 CMO M C ll


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Phase Charge

MRAM

RRAM

Memristor

CMOx NAND

NOR

DRAM

NAND

Logic?

3 More Esoter ic Storage Technologies?


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Tunneling Magnetic Junction RAM (TMJ-RAM):

Speed of SRAM, densityofDRAM, non-volatile

New field calledSpintronics:combination ofquantum spinand

electronics

Same technology used inhigh-density disk-drives

MEMs storage devices:

Large magnetic sled floatingon top of lots of littleread/write heads

Micromechanical actuatorsmove the sled back and forth over the

heads

3. More Esoter ic Storage Technologies?

3 1 Tunneling Magnetic Junction


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3.1 Tunneling Magnetic Junction

Current

H

ReadLine

WriteLine

Magnetic

Memory CellSize < 1m

3 2 MEMS based Storage


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3.2 MEMS-based Storage

Magnetic sled floats on array of read/write heads

Approx 250 Gbit/in2

Data rates:

IBM: 250 MB/s w 1000 heads

CMU: 3.1 MB/s w 400 heads

Electrostatic actuators move media around to align it withheads

Sweep sled 50m in < 0.5s

Capacity estimated to be in the 1-10GB in 10cm2



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http://www.chips.ece.cmu.edu

On-chip Magnetic Storage using MEMS

Read/Write

tips

Magnetic

Media

Actuators



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X

Y

Sled only

moves over

the area of a

single square

One probe tip

per square

Each tip

accesses data

at the same

relative position



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Read/write

tips

Media

Bits stored

underneath

each tip

side view

3 3 Molecular-Electronic Memory


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Nano-circuit architecture

Molecular-Electronic MemoryUS patents 6128214, 6256767, 6314019

-10

-5

0

5

10

-2.0 -1.0 0.0 1.0

C

urrent(mA)

Voltage (V)

molecular switch

3.3 Molecular-Electronic Memory

3 4 Storage: Atomic Memory


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3.4 Storage: Atomic Memory

Linear & flat memory

Storage today is linearortwo-

dimensional.

Three D storage holds an

enormous promise.

Blu-Ray DVD is 5.25 with

25GB on a side. (Blue is

400nm, Red is 650nm).

This density is 250nm per bit!

Atomic memory

Avogadros number = 6 x 1023

Iron has atomic mass of56 (so an

Avogadros number ofiron atoms

weighs 1 gram)

Iron is 9 times denser than water, soa cc of iron weighs 9g

1023atoms in 1cc of iron.

Five atoms are about 25 nm.

About 100 Petabytes in a mm3 if 125

atoms per bit.


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New Memory

devices

New Memory

devices

New Memory

devices

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